| blob | 7911f14c2157ac0b4369c56476464026d87ce4f3 |
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
24 #else
25 #include "proc-v7-2level.S"
26 #endif
28 ENTRY(cpu_v7_proc_init)
29 ret lr
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
37 ret lr
38 ENDPROC(cpu_v7_proc_fin)
40 /*
41 * cpu_v7_reset(loc)
42 *
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
46 *
47 * - loc - location to jump to for soft reset
48 *
49 * This code must be executed using a flat identity mapping with
50 * caches disabled.
51 */
52 .align 5
53 .pushsection .idmap.text, "ax"
54 ENTRY(cpu_v7_reset)
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
59 isb
60 bx r0
61 ENDPROC(cpu_v7_reset)
62 .popsection
64 /*
65 * cpu_v7_do_idle()
66 *
67 * Idle the processor (eg, wait for interrupt).
68 *
69 * IRQs are already disabled.
70 */
71 ENTRY(cpu_v7_do_idle)
72 dsb @ WFI may enter a low-power mode
73 wfi
74 ret lr
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
79 ALT_UP_B(1f)
80 ret lr
81 1: dcache_line_size r2, r3
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
83 add r0, r0, r2
84 subs r1, r1, r2
85 bhi 2b
86 dsb ishst
87 ret lr
88 ENDPROC(cpu_v7_dcache_clean_area)
90 string cpu_v7_name, "ARMv7 Processor"
91 .align
93 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94 .globl cpu_v7_suspend_size
95 .equ cpu_v7_suspend_size, 4 * 9
96 #ifdef CONFIG_ARM_CPU_SUSPEND
97 ENTRY(cpu_v7_do_suspend)
98 stmfd sp!, {r4 - r10, lr}
99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
101 stmia r0!, {r4 - r5}
102 #ifdef CONFIG_MMU
103 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
104 #ifdef CONFIG_ARM_LPAE
105 mrrc p15, 1, r5, r7, c2 @ TTB 1
106 #else
107 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
108 #endif
109 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
110 #endif
111 mrc p15, 0, r8, c1, c0, 0 @ Control register
112 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
113 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
114 stmia r0, {r5 - r11}
115 ldmfd sp!, {r4 - r10, pc}
116 ENDPROC(cpu_v7_do_suspend)
118 ENTRY(cpu_v7_do_resume)
119 mov ip, #0
120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
121 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
122 ldmia r0!, {r4 - r5}
123 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
125 ldmia r0, {r5 - r11}
126 #ifdef CONFIG_MMU
127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
128 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
129 #ifdef CONFIG_ARM_LPAE
130 mcrr p15, 0, r1, ip, c2 @ TTB 0
131 mcrr p15, 1, r5, r7, c2 @ TTB 1
132 #else
133 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
134 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
135 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
136 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
137 #endif
138 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
139 ldr r4, =PRRR @ PRRR
140 ldr r5, =NMRR @ NMRR
141 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
142 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
143 #endif /* CONFIG_MMU */
144 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
145 teq r4, r9 @ Is it already set?
146 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
147 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
148 isb
149 dsb
150 mov r0, r8 @ control register
151 b cpu_resume_mmu
152 ENDPROC(cpu_v7_do_resume)
153 #endif
155 /*
156 * Cortex-A8
157 */
158 globl_equ cpu_ca8_proc_init, cpu_v7_proc_init
159 globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin
160 globl_equ cpu_ca8_reset, cpu_v7_reset
161 globl_equ cpu_ca8_do_idle, cpu_v7_do_idle
162 globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
163 globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext
164 globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size
165 #ifdef CONFIG_ARM_CPU_SUSPEND
166 globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend
167 globl_equ cpu_ca8_do_resume, cpu_v7_do_resume
168 #endif
170 /*
171 * Cortex-A9 processor functions
172 */
173 globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
174 globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
175 globl_equ cpu_ca9mp_reset, cpu_v7_reset
176 globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
177 globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
178 globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
179 globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
180 .globl cpu_ca9mp_suspend_size
181 .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
182 #ifdef CONFIG_ARM_CPU_SUSPEND
183 ENTRY(cpu_ca9mp_do_suspend)
184 stmfd sp!, {r4 - r5}
185 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
186 mrc p15, 0, r5, c15, c0, 0 @ Power register
187 stmia r0!, {r4 - r5}
188 ldmfd sp!, {r4 - r5}
189 b cpu_v7_do_suspend
190 ENDPROC(cpu_ca9mp_do_suspend)
192 ENTRY(cpu_ca9mp_do_resume)
193 ldmia r0!, {r4 - r5}
194 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
195 teq r4, r10 @ Already restored?
196 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
197 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
198 teq r5, r10 @ Already restored?
199 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
200 b cpu_v7_do_resume
201 ENDPROC(cpu_ca9mp_do_resume)
202 #endif
204 #ifdef CONFIG_CPU_PJ4B
205 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
206 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
207 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
208 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
209 globl_equ cpu_pj4b_reset, cpu_v7_reset
210 #ifdef CONFIG_PJ4B_ERRATA_4742
211 ENTRY(cpu_pj4b_do_idle)
212 dsb @ WFI may enter a low-power mode
213 wfi
214 dsb @barrier
215 ret lr
216 ENDPROC(cpu_pj4b_do_idle)
217 #else
218 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
219 #endif
220 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
221 #ifdef CONFIG_ARM_CPU_SUSPEND
222 ENTRY(cpu_pj4b_do_suspend)
223 stmfd sp!, {r6 - r10}
224 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
225 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
226 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
227 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
228 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
229 stmia r0!, {r6 - r10}
230 ldmfd sp!, {r6 - r10}
231 b cpu_v7_do_suspend
232 ENDPROC(cpu_pj4b_do_suspend)
234 ENTRY(cpu_pj4b_do_resume)
235 ldmia r0!, {r6 - r10}
236 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
237 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
238 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
239 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
240 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
241 b cpu_v7_do_resume
242 ENDPROC(cpu_pj4b_do_resume)
243 #endif
244 .globl cpu_pj4b_suspend_size
245 .equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
247 #endif
249 /*
250 * __v7_setup
251 *
252 * Initialise TLB, Caches, and MMU state ready to switch the MMU
253 * on. Return in r0 the new CP15 C1 control register setting.
254 *
255 * This should be able to cover all ARMv7 cores.
256 *
257 * It is assumed that:
258 * - cache type register is implemented
259 */
260 __v7_ca5mp_setup:
261 __v7_ca9mp_setup:
262 __v7_cr7mp_setup:
263 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
264 b 1f
265 __v7_ca7mp_setup:
266 __v7_ca12mp_setup:
267 __v7_ca15mp_setup:
268 __v7_b15mp_setup:
269 __v7_ca17mp_setup:
270 mov r10, #0
271 1: adr r12, __v7_setup_stack @ the local stack
272 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
273 bl v7_invalidate_l1
274 ldmia r12, {r0-r5, lr}
275 #ifdef CONFIG_SMP
276 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
277 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
278 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
279 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
280 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
281 mcreq p15, 0, r0, c1, c0, 1
282 #endif
283 b __v7_setup_cont
285 __v7_pj4b_setup:
286 #ifdef CONFIG_CPU_PJ4B
288 /* Auxiliary Debug Modes Control 1 Register */
289 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
290 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
291 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
293 /* Auxiliary Debug Modes Control 2 Register */
294 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
295 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
296 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
297 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
298 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
299 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
300 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
302 /* Auxiliary Functional Modes Control Register 0 */
303 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
304 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
305 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
307 /* Auxiliary Debug Modes Control 0 Register */
308 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
310 /* Auxiliary Debug Modes Control 1 Register */
311 mrc p15, 1, r0, c15, c1, 1
312 orr r0, r0, #PJ4B_CLEAN_LINE
313 orr r0, r0, #PJ4B_INTER_PARITY
314 bic r0, r0, #PJ4B_STATIC_BP
315 mcr p15, 1, r0, c15, c1, 1
317 /* Auxiliary Debug Modes Control 2 Register */
318 mrc p15, 1, r0, c15, c1, 2
319 bic r0, r0, #PJ4B_FAST_LDR
320 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
321 mcr p15, 1, r0, c15, c1, 2
323 /* Auxiliary Functional Modes Control Register 0 */
324 mrc p15, 1, r0, c15, c2, 0
325 #ifdef CONFIG_SMP
326 orr r0, r0, #PJ4B_SMP_CFB
327 #endif
328 orr r0, r0, #PJ4B_L1_PAR_CHK
329 orr r0, r0, #PJ4B_BROADCAST_CACHE
330 mcr p15, 1, r0, c15, c2, 0
332 /* Auxiliary Debug Modes Control 0 Register */
333 mrc p15, 1, r0, c15, c1, 0
334 orr r0, r0, #PJ4B_WFI_WFE
335 mcr p15, 1, r0, c15, c1, 0
337 #endif /* CONFIG_CPU_PJ4B */
339 __v7_setup:
340 adr r12, __v7_setup_stack @ the local stack
341 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
342 bl v7_invalidate_l1
343 ldmia r12, {r0-r5, lr}
345 __v7_setup_cont:
346 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
347 and r10, r0, #0xff000000 @ ARM?
348 teq r10, #0x41000000
349 bne 3f
350 and r5, r0, #0x00f00000 @ variant
351 and r6, r0, #0x0000000f @ revision
352 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
353 ubfx r0, r0, #4, #12 @ primary part number
355 /* Cortex-A8 Errata */
356 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
357 teq r0, r10
358 bne 2f
359 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
361 teq r5, #0x00100000 @ only present in r1p*
362 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
363 orreq r10, r10, #(1 << 6) @ set IBE to 1
364 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
365 #endif
366 #ifdef CONFIG_ARM_ERRATA_458693
367 teq r6, #0x20 @ only present in r2p0
368 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
369 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
370 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
371 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
372 #endif
373 #ifdef CONFIG_ARM_ERRATA_460075
374 teq r6, #0x20 @ only present in r2p0
375 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
376 tsteq r10, #1 << 22
377 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
378 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
379 #endif
380 b 3f
382 /* Cortex-A9 Errata */
383 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
384 teq r0, r10
385 bne 3f
386 #ifdef CONFIG_ARM_ERRATA_742230
387 cmp r6, #0x22 @ only present up to r2p2
388 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
389 orrle r10, r10, #1 << 4 @ set bit #4
390 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
391 #endif
392 #ifdef CONFIG_ARM_ERRATA_742231
393 teq r6, #0x20 @ present in r2p0
394 teqne r6, #0x21 @ present in r2p1
395 teqne r6, #0x22 @ present in r2p2
396 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
397 orreq r10, r10, #1 << 12 @ set bit #12
398 orreq r10, r10, #1 << 22 @ set bit #22
399 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
400 #endif
401 #ifdef CONFIG_ARM_ERRATA_743622
402 teq r5, #0x00200000 @ only present in r2p*
403 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
404 orreq r10, r10, #1 << 6 @ set bit #6
405 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
406 #endif
407 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
408 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
409 ALT_UP_B(1f)
410 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
411 orrlt r10, r10, #1 << 11 @ set bit #11
412 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
413 1:
414 #endif
416 /* Cortex-A15 Errata */
417 3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
418 teq r0, r10
419 bne 4f
421 #ifdef CONFIG_ARM_ERRATA_773022
422 cmp r6, #0x4 @ only present up to r0p4
423 mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
424 orrle r10, r10, #1 << 1 @ disable loop buffer
425 mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
426 #endif
428 4: mov r10, #0
429 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
430 #ifdef CONFIG_MMU
431 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
432 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
433 ldr r5, =PRRR @ PRRR
434 ldr r6, =NMRR @ NMRR
435 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
436 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
437 #endif
438 dsb @ Complete invalidations
439 #ifndef CONFIG_ARM_THUMBEE
440 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
441 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
442 teq r0, #(1 << 12) @ check if ThumbEE is present
443 bne 1f
444 mov r5, #0
445 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
446 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
447 orr r0, r0, #1 @ set the 1st bit in order to
448 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
449 1:
450 #endif
451 adr r5, v7_crval
452 ldmia r5, {r5, r6}
453 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
454 #ifdef CONFIG_SWP_EMULATE
455 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
456 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
457 #endif
458 mrc p15, 0, r0, c1, c0, 0 @ read control register
459 bic r0, r0, r5 @ clear bits them
460 orr r0, r0, r6 @ set them
461 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
462 ret lr @ return to head.S:__ret
463 ENDPROC(__v7_setup)
465 .align 2
466 __v7_setup_stack:
467 .space 4 * 7 @ 12 registers
469 __INITDATA
471 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
472 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
473 #ifndef CONFIG_ARM_LPAE
474 define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
475 define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
476 #endif
477 #ifdef CONFIG_CPU_PJ4B
478 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
479 #endif
481 .section ".rodata"
483 string cpu_arch_name, "armv7"
484 string cpu_elf_name, "v7"
485 .align
487 .section ".proc.info.init", #alloc
489 /*
490 * Standard v7 proc info content
491 */
492 .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
493 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
494 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
495 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
496 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
497 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
498 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
499 initfn \initfunc, \name
500 .long cpu_arch_name
501 .long cpu_elf_name
502 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
503 HWCAP_EDSP | HWCAP_TLS | \hwcaps
504 .long cpu_v7_name
505 .long \proc_fns
506 .long v7wbi_tlb_fns
507 .long v6_user_fns
508 .long v7_cache_fns
509 .endm
511 #ifndef CONFIG_ARM_LPAE
512 /*
513 * ARM Ltd. Cortex A5 processor.
514 */
515 .type __v7_ca5mp_proc_info, #object
516 __v7_ca5mp_proc_info:
517 .long 0x410fc050
518 .long 0xff0ffff0
519 __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
520 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
522 /*
523 * ARM Ltd. Cortex A9 processor.
524 */
525 .type __v7_ca9mp_proc_info, #object
526 __v7_ca9mp_proc_info:
527 .long 0x410fc090
528 .long 0xff0ffff0
529 __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
530 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
532 /*
533 * ARM Ltd. Cortex A8 processor.
534 */
535 .type __v7_ca8_proc_info, #object
536 __v7_ca8_proc_info:
537 .long 0x410fc080
538 .long 0xff0ffff0
539 __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
540 .size __v7_ca8_proc_info, . - __v7_ca8_proc_info
542 #endif /* CONFIG_ARM_LPAE */
544 /*
545 * Marvell PJ4B processor.
546 */
547 #ifdef CONFIG_CPU_PJ4B
548 .type __v7_pj4b_proc_info, #object
549 __v7_pj4b_proc_info:
550 .long 0x560f5800
551 .long 0xff0fff00
552 __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
553 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
554 #endif
556 /*
557 * ARM Ltd. Cortex R7 processor.
558 */
559 .type __v7_cr7mp_proc_info, #object
560 __v7_cr7mp_proc_info:
561 .long 0x410fc170
562 .long 0xff0ffff0
563 __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
564 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
566 /*
567 * ARM Ltd. Cortex A7 processor.
568 */
569 .type __v7_ca7mp_proc_info, #object
570 __v7_ca7mp_proc_info:
571 .long 0x410fc070
572 .long 0xff0ffff0
573 __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
574 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
576 /*
577 * ARM Ltd. Cortex A12 processor.
578 */
579 .type __v7_ca12mp_proc_info, #object
580 __v7_ca12mp_proc_info:
581 .long 0x410fc0d0
582 .long 0xff0ffff0
583 __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup
584 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
586 /*
587 * ARM Ltd. Cortex A15 processor.
588 */
589 .type __v7_ca15mp_proc_info, #object
590 __v7_ca15mp_proc_info:
591 .long 0x410fc0f0
592 .long 0xff0ffff0
593 __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup
594 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
596 /*
597 * Broadcom Corporation Brahma-B15 processor.
598 */
599 .type __v7_b15mp_proc_info, #object
600 __v7_b15mp_proc_info:
601 .long 0x420f00f0
602 .long 0xff0ffff0
603 __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup
604 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
606 /*
607 * ARM Ltd. Cortex A17 processor.
608 */
609 .type __v7_ca17mp_proc_info, #object
610 __v7_ca17mp_proc_info:
611 .long 0x410fc0e0
612 .long 0xff0ffff0
613 __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup
614 .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
616 /*
617 * Qualcomm Inc. Krait processors.
618 */
619 .type __krait_proc_info, #object
620 __krait_proc_info:
621 .long 0x510f0400 @ Required ID value
622 .long 0xff0ffc00 @ Mask for ID
623 /*
624 * Some Krait processors don't indicate support for SDIV and UDIV
625 * instructions in the ARM instruction set, even though they actually
626 * do support them. They also don't indicate support for fused multiply
627 * instructions even though they actually do support them.
628 */
629 __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
630 .size __krait_proc_info, . - __krait_proc_info
632 /*
633 * Match any ARMv7 processor core.
634 */
635 .type __v7_proc_info, #object
636 __v7_proc_info:
637 .long 0x000f0000 @ Required ID value
638 .long 0x000f0000 @ Mask for ID
639 __v7_proc __v7_proc_info, __v7_setup
640 .size __v7_proc_info, . - __v7_proc_info