?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.1.18
[linux/fpc-iii.git] / arch / mips / alchemy / common / usb.c
blob297805ade849811f7baeb982d22066f5b973013e
1 /*
2 * USB block power/access management abstraction.
3 *
4 * Au1000+: The OHCI block control register is at the far end of the OHCI memory
5 * area. Au1550 has OHCI on different base address. No need to handle
6 * UDC here.
7 * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
8 * as well as the PHY for EHCI and UDC.
9 *
10 */
11
12 #include <linux/clk.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/syscore_ops.h>
18 #include <asm/cpu.h>
19 #include <asm/mach-au1x00/au1000.h>
20
21 /* control register offsets */
22 #define AU1000_OHCICFG 0x7fffc
23 #define AU1550_OHCICFG 0x07ffc
24 #define AU1200_USBCFG 0x04
25
26 /* Au1000 USB block config bits */
27 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
28 #define USBHEN_CE (1 << 3) /* OHCI block clock enable */
29 #define USBHEN_E (1 << 2) /* OHCI block enable */
30 #define USBHEN_C (1 << 1) /* OHCI block coherency bit */
31 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
32
33 /* Au1200 USB config bits */
34 #define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
35 #define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */
36 #define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */
37 #define USBCFG_SSD (1 << 23) /* serial short detect en */
38 #define USBCFG_PPE (1 << 19) /* HS PHY PLL */
39 #define USBCFG_UCE (1 << 18) /* UDC clock enable */
40 #define USBCFG_ECE (1 << 17) /* EHCI clock enable */
41 #define USBCFG_OCE (1 << 16) /* OHCI clock enable */
42 #define USBCFG_FLA(x) (((x) & 0x3f) << 8)
43 #define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */
44 #define USBCFG_GME (1 << 6) /* OTG mem access */
45 #define USBCFG_DBE (1 << 5) /* UDC busmaster enable */
46 #define USBCFG_DME (1 << 4) /* UDC mem enable */
47 #define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */
48 #define USBCFG_EME (1 << 2) /* EHCI mem enable */
49 #define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */
50 #define USBCFG_OME (1 << 0) /* OHCI mem enable */
51 #define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\
52 USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \
53 USBCFG_GME | USBCFG_DBE | USBCFG_DME | \
54 USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \
55 USBCFG_OME)
56
57 /* Au1300 USB config registers */
58 #define USB_DWC_CTRL1 0x00
59 #define USB_DWC_CTRL2 0x04
60 #define USB_VBUS_TIMER 0x10
61 #define USB_SBUS_CTRL 0x14
62 #define USB_MSR_ERR 0x18
63 #define USB_DWC_CTRL3 0x1C
64 #define USB_DWC_CTRL4 0x20
65 #define USB_OTG_STATUS 0x28
66 #define USB_DWC_CTRL5 0x2C
67 #define USB_DWC_CTRL6 0x30
68 #define USB_DWC_CTRL7 0x34
69 #define USB_PHY_STATUS 0xC0
70 #define USB_INT_STATUS 0xC4
71 #define USB_INT_ENABLE 0xC8
72
73 #define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */
74 #define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */
75 #define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */
76
77 #define USB_DWC_CTRL2_PHY1RS 0x04 /* set to enable PHY1 */
78 #define USB_DWC_CTRL2_PHY0RS 0x02 /* set to enable PHY0 */
79 #define USB_DWC_CTRL2_PHYRS 0x01 /* set to enable PHY */
80
81 #define USB_DWC_CTRL3_OHCI1_CKEN (1 << 19)
82 #define USB_DWC_CTRL3_OHCI0_CKEN (1 << 18)
83 #define USB_DWC_CTRL3_EHCI0_CKEN (1 << 17)
84 #define USB_DWC_CTRL3_OTG0_CKEN (1 << 16)
85
86 #define USB_SBUS_CTRL_SBCA 0x04 /* coherent access */
87
88 #define USB_INTEN_FORCE 0x20
89 #define USB_INTEN_PHY 0x10
90 #define USB_INTEN_UDC 0x08
91 #define USB_INTEN_EHCI 0x04
92 #define USB_INTEN_OHCI1 0x02
93 #define USB_INTEN_OHCI0 0x01
94
95 static DEFINE_SPINLOCK(alchemy_usb_lock);
96
97 static inline void __au1300_usb_phyctl(void __iomem *base, int enable)
98 {
99 unsigned long r, s;
100
101 r = __raw_readl(base + USB_DWC_CTRL2);
102 s = __raw_readl(base + USB_DWC_CTRL3);
103
104 s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN |
105 USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN;
106
107 if (enable) {
108 /* simply enable all PHYs */
109 r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
110 USB_DWC_CTRL2_PHYRS;
111 __raw_writel(r, base + USB_DWC_CTRL2);
112 wmb();
113 } else if (!s) {
114 /* no USB block active, do disable all PHYs */
115 r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
116 USB_DWC_CTRL2_PHYRS);
117 __raw_writel(r, base + USB_DWC_CTRL2);
118 wmb();
119 }
120 }
121
122 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
123 {
124 unsigned long r;
125
126 if (enable) {
127 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */
128 wmb();
129
130 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */
131 r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
132 : USB_DWC_CTRL3_OHCI1_CKEN;
133 __raw_writel(r, base + USB_DWC_CTRL3);
134 wmb();
135
136 __au1300_usb_phyctl(base, enable); /* power up the PHYs */
137
138 r = __raw_readl(base + USB_INT_ENABLE);
139 r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1;
140 __raw_writel(r, base + USB_INT_ENABLE);
141 wmb();
142
143 /* reset the OHCI start clock bit */
144 __raw_writel(0, base + USB_DWC_CTRL7);
145 wmb();
146 } else {
147 r = __raw_readl(base + USB_INT_ENABLE);
148 r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1);
149 __raw_writel(r, base + USB_INT_ENABLE);
150 wmb();
151
152 r = __raw_readl(base + USB_DWC_CTRL3);
153 r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
154 : USB_DWC_CTRL3_OHCI1_CKEN);
155 __raw_writel(r, base + USB_DWC_CTRL3);
156 wmb();
157
158 __au1300_usb_phyctl(base, enable);
159 }
160 }
161
162 static inline void __au1300_ehci_control(void __iomem *base, int enable)
163 {
164 unsigned long r;
165
166 if (enable) {
167 r = __raw_readl(base + USB_DWC_CTRL3);
168 r |= USB_DWC_CTRL3_EHCI0_CKEN;
169 __raw_writel(r, base + USB_DWC_CTRL3);
170 wmb();
171
172 r = __raw_readl(base + USB_DWC_CTRL1);
173 r |= USB_DWC_CTRL1_HSTRS;
174 __raw_writel(r, base + USB_DWC_CTRL1);
175 wmb();
176
177 __au1300_usb_phyctl(base, enable);
178
179 r = __raw_readl(base + USB_INT_ENABLE);
180 r |= USB_INTEN_EHCI;
181 __raw_writel(r, base + USB_INT_ENABLE);
182 wmb();
183 } else {
184 r = __raw_readl(base + USB_INT_ENABLE);
185 r &= ~USB_INTEN_EHCI;
186 __raw_writel(r, base + USB_INT_ENABLE);
187 wmb();
188
189 r = __raw_readl(base + USB_DWC_CTRL1);
190 r &= ~USB_DWC_CTRL1_HSTRS;
191 __raw_writel(r, base + USB_DWC_CTRL1);
192 wmb();
193
194 r = __raw_readl(base + USB_DWC_CTRL3);
195 r &= ~USB_DWC_CTRL3_EHCI0_CKEN;
196 __raw_writel(r, base + USB_DWC_CTRL3);
197 wmb();
198
199 __au1300_usb_phyctl(base, enable);
200 }
201 }
202
203 static inline void __au1300_udc_control(void __iomem *base, int enable)
204 {
205 unsigned long r;
206
207 if (enable) {
208 r = __raw_readl(base + USB_DWC_CTRL1);
209 r |= USB_DWC_CTRL1_DCRS;
210 __raw_writel(r, base + USB_DWC_CTRL1);
211 wmb();
212
213 __au1300_usb_phyctl(base, enable);
214
215 r = __raw_readl(base + USB_INT_ENABLE);
216 r |= USB_INTEN_UDC;
217 __raw_writel(r, base + USB_INT_ENABLE);
218 wmb();
219 } else {
220 r = __raw_readl(base + USB_INT_ENABLE);
221 r &= ~USB_INTEN_UDC;
222 __raw_writel(r, base + USB_INT_ENABLE);
223 wmb();
224
225 r = __raw_readl(base + USB_DWC_CTRL1);
226 r &= ~USB_DWC_CTRL1_DCRS;
227 __raw_writel(r, base + USB_DWC_CTRL1);
228 wmb();
229
230 __au1300_usb_phyctl(base, enable);
231 }
232 }
233
234 static inline void __au1300_otg_control(void __iomem *base, int enable)
235 {
236 unsigned long r;
237 if (enable) {
238 r = __raw_readl(base + USB_DWC_CTRL3);
239 r |= USB_DWC_CTRL3_OTG0_CKEN;
240 __raw_writel(r, base + USB_DWC_CTRL3);
241 wmb();
242
243 r = __raw_readl(base + USB_DWC_CTRL1);
244 r &= ~USB_DWC_CTRL1_OTGD;
245 __raw_writel(r, base + USB_DWC_CTRL1);
246 wmb();
247
248 __au1300_usb_phyctl(base, enable);
249 } else {
250 r = __raw_readl(base + USB_DWC_CTRL1);
251 r |= USB_DWC_CTRL1_OTGD;
252 __raw_writel(r, base + USB_DWC_CTRL1);
253 wmb();
254
255 r = __raw_readl(base + USB_DWC_CTRL3);
256 r &= ~USB_DWC_CTRL3_OTG0_CKEN;
257 __raw_writel(r, base + USB_DWC_CTRL3);
258 wmb();
259
260 __au1300_usb_phyctl(base, enable);
261 }
262 }
263
264 static inline int au1300_usb_control(int block, int enable)
265 {
266 void __iomem *base =
267 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
268 int ret = 0;
269
270 switch (block) {
271 case ALCHEMY_USB_OHCI0:
272 __au1300_ohci_control(base, enable, 0);
273 break;
274 case ALCHEMY_USB_OHCI1:
275 __au1300_ohci_control(base, enable, 1);
276 break;
277 case ALCHEMY_USB_EHCI0:
278 __au1300_ehci_control(base, enable);
279 break;
280 case ALCHEMY_USB_UDC0:
281 __au1300_udc_control(base, enable);
282 break;
283 case ALCHEMY_USB_OTG0:
284 __au1300_otg_control(base, enable);
285 break;
286 default:
287 ret = -ENODEV;
288 }
289 return ret;
290 }
291
292 static inline void au1300_usb_init(void)
293 {
294 void __iomem *base =
295 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
296
297 /* set some sane defaults. Note: we don't fiddle with DWC_CTRL4
298 * here at all: Port 2 routing (EHCI or UDC) must be set either
299 * by boot firmware or platform init code; I can't autodetect
300 * a sane setting.
301 */
302 __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
303 wmb();
304 __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
305 wmb();
306 __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
307 wmb();
308 __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
309 wmb();
310 /* set coherent access bit */
311 __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
312 wmb();
313 }
314
315 static inline void __au1200_ohci_control(void __iomem *base, int enable)
316 {
317 unsigned long r = __raw_readl(base + AU1200_USBCFG);
318 if (enable) {
319 __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
320 wmb();
321 udelay(2000);
322 } else {
323 __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
324 wmb();
325 udelay(1000);
326 }
327 }
328
329 static inline void __au1200_ehci_control(void __iomem *base, int enable)
330 {
331 unsigned long r = __raw_readl(base + AU1200_USBCFG);
332 if (enable) {
333 __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
334 wmb();
335 udelay(1000);
336 } else {
337 if (!(r & USBCFG_UCE)) /* UDC also off? */
338 r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
339 __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
340 wmb();
341 udelay(1000);
342 }
343 }
344
345 static inline void __au1200_udc_control(void __iomem *base, int enable)
346 {
347 unsigned long r = __raw_readl(base + AU1200_USBCFG);
348 if (enable) {
349 __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
350 wmb();
351 } else {
352 if (!(r & USBCFG_ECE)) /* EHCI also off? */
353 r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
354 __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
355 wmb();
356 }
357 }
358
359 static inline int au1200_usb_control(int block, int enable)
360 {
361 void __iomem *base =
362 (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
363
364 switch (block) {
365 case ALCHEMY_USB_OHCI0:
366 __au1200_ohci_control(base, enable);
367 break;
368 case ALCHEMY_USB_UDC0:
369 __au1200_udc_control(base, enable);
370 break;
371 case ALCHEMY_USB_EHCI0:
372 __au1200_ehci_control(base, enable);
373 break;
374 default:
375 return -ENODEV;
376 }
377 return 0;
378 }
379
380
381 /* initialize USB block(s) to a known working state */
382 static inline void au1200_usb_init(void)
383 {
384 void __iomem *base =
385 (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
386 __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
387 wmb();
388 udelay(1000);
389 }
390
391 static inline int au1000_usb_init(unsigned long rb, int reg)
392 {
393 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
394 unsigned long r = __raw_readl(base);
395 struct clk *c;
396
397 /* 48MHz check. Don't init if no one can provide it */
398 c = clk_get(NULL, "usbh_clk");
399 if (IS_ERR(c))
400 return -ENODEV;
401 if (clk_round_rate(c, 48000000) != 48000000) {
402 clk_put(c);
403 return -ENODEV;
404 }
405 if (clk_set_rate(c, 48000000)) {
406 clk_put(c);
407 return -ENODEV;
408 }
409 clk_put(c);
410
411 #if defined(__BIG_ENDIAN)
412 r |= USBHEN_BE;
413 #endif
414 r |= USBHEN_C;
415
416 __raw_writel(r, base);
417 wmb();
418 udelay(1000);
419
420 return 0;
421 }
422
423
424 static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
425 {
426 void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
427 unsigned long r = __raw_readl(base + creg);
428 struct clk *c = clk_get(NULL, "usbh_clk");
429
430 if (IS_ERR(c))
431 return;
432
433 if (enable) {
434 if (clk_prepare_enable(c))
435 goto out;
436
437 __raw_writel(r | USBHEN_CE, base + creg);
438 wmb();
439 udelay(1000);
440 __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
441 wmb();
442 udelay(1000);
443
444 /* wait for reset complete (read reg twice: au1500 erratum) */
445 while (__raw_readl(base + creg),
446 !(__raw_readl(base + creg) & USBHEN_RD))
447 udelay(1000);
448 } else {
449 __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
450 wmb();
451 clk_disable_unprepare(c);
452 }
453 out:
454 clk_put(c);
455 }
456
457 static inline int au1000_usb_control(int block, int enable, unsigned long rb,
458 int creg)
459 {
460 int ret = 0;
461
462 switch (block) {
463 case ALCHEMY_USB_OHCI0:
464 __au1xx0_ohci_control(enable, rb, creg);
465 break;
466 default:
467 ret = -ENODEV;
468 }
469 return ret;
470 }
471
472 /*
473 * alchemy_usb_control - control Alchemy on-chip USB blocks
474 * @block: USB block to target
475 * @enable: set 1 to enable a block, 0 to disable
476 */
477 int alchemy_usb_control(int block, int enable)
478 {
479 unsigned long flags;
480 int ret;
481
482 spin_lock_irqsave(&alchemy_usb_lock, flags);
483 switch (alchemy_get_cputype()) {
484 case ALCHEMY_CPU_AU1000:
485 case ALCHEMY_CPU_AU1500:
486 case ALCHEMY_CPU_AU1100:
487 ret = au1000_usb_control(block, enable,
488 AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
489 break;
490 case ALCHEMY_CPU_AU1550:
491 ret = au1000_usb_control(block, enable,
492 AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
493 break;
494 case ALCHEMY_CPU_AU1200:
495 ret = au1200_usb_control(block, enable);
496 break;
497 case ALCHEMY_CPU_AU1300:
498 ret = au1300_usb_control(block, enable);
499 break;
500 default:
501 ret = -ENODEV;
502 }
503 spin_unlock_irqrestore(&alchemy_usb_lock, flags);
504 return ret;
505 }
506 EXPORT_SYMBOL_GPL(alchemy_usb_control);
507
508
509 static unsigned long alchemy_usb_pmdata[2];
510
511 static void au1000_usb_pm(unsigned long br, int creg, int susp)
512 {
513 void __iomem *base = (void __iomem *)KSEG1ADDR(br);
514
515 if (susp) {
516 alchemy_usb_pmdata[0] = __raw_readl(base + creg);
517 /* There appears to be some undocumented reset register.... */
518 __raw_writel(0, base + 0x04);
519 wmb();
520 __raw_writel(0, base + creg);
521 wmb();
522 } else {
523 __raw_writel(alchemy_usb_pmdata[0], base + creg);
524 wmb();
525 }
526 }
527
528 static void au1200_usb_pm(int susp)
529 {
530 void __iomem *base =
531 (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR);
532 if (susp) {
533 /* save OTG_CAP/MUX registers which indicate port routing */
534 /* FIXME: write an OTG driver to do that */
535 alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
536 alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
537 } else {
538 /* restore access to all MMIO areas */
539 au1200_usb_init();
540
541 /* restore OTG_CAP/MUX registers */
542 __raw_writel(alchemy_usb_pmdata[0], base + 0x00);
543 __raw_writel(alchemy_usb_pmdata[1], base + 0x04);
544 wmb();
545 }
546 }
547
548 static void au1300_usb_pm(int susp)
549 {
550 void __iomem *base =
551 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
552 /* remember Port2 routing */
553 if (susp) {
554 alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
555 } else {
556 au1300_usb_init();
557 __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);
558 wmb();
559 }
560 }
561
562 static void alchemy_usb_pm(int susp)
563 {
564 switch (alchemy_get_cputype()) {
565 case ALCHEMY_CPU_AU1000:
566 case ALCHEMY_CPU_AU1500:
567 case ALCHEMY_CPU_AU1100:
568 au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp);
569 break;
570 case ALCHEMY_CPU_AU1550:
571 au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp);
572 break;
573 case ALCHEMY_CPU_AU1200:
574 au1200_usb_pm(susp);
575 break;
576 case ALCHEMY_CPU_AU1300:
577 au1300_usb_pm(susp);
578 break;
579 }
580 }
581
582 static int alchemy_usb_suspend(void)
583 {
584 alchemy_usb_pm(1);
585 return 0;
586 }
587
588 static void alchemy_usb_resume(void)
589 {
590 alchemy_usb_pm(0);
591 }
592
593 static struct syscore_ops alchemy_usb_pm_ops = {
594 .suspend = alchemy_usb_suspend,
595 .resume = alchemy_usb_resume,
596 };
597
598 static int __init alchemy_usb_init(void)
599 {
600 int ret = 0;
601
602 switch (alchemy_get_cputype()) {
603 case ALCHEMY_CPU_AU1000:
604 case ALCHEMY_CPU_AU1500:
605 case ALCHEMY_CPU_AU1100:
606 ret = au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR,
607 AU1000_OHCICFG);
608 break;
609 case ALCHEMY_CPU_AU1550:
610 ret = au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR,
611 AU1550_OHCICFG);
612 break;
613 case ALCHEMY_CPU_AU1200:
614 au1200_usb_init();
615 break;
616 case ALCHEMY_CPU_AU1300:
617 au1300_usb_init();
618 break;
619 }
620
621 if (!ret)
622 register_syscore_ops(&alchemy_usb_pm_ops);
623
624 return ret;
625 }
626 arch_initcall(alchemy_usb_init);
Linux with added FPC-III support