2 * Alchemy Db1550/Pb1550 board support
4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/gpio.h>
10 #include <linux/i2c.h>
11 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/flash.h>
21 #include <asm/bootinfo.h>
22 #include <asm/mach-au1x00/au1000.h>
23 #include <asm/mach-au1x00/au1xxx_eth.h>
24 #include <asm/mach-au1x00/au1xxx_dbdma.h>
25 #include <asm/mach-au1x00/au1xxx_psc.h>
26 #include <asm/mach-au1x00/au1550_spi.h>
27 #include <asm/mach-au1x00/au1550nd.h>
28 #include <asm/mach-db1x00/bcsr.h>
32 static void __init
db1550_hw_setup(void)
37 /* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
38 * as well as PSC1_SYNC for AC97 on PB1550.
40 v
= alchemy_rdsys(AU1000_SYS_PINFUNC
);
41 alchemy_wrsys(v
| 1 | SYS_PF_PSC1_S1
, AU1000_SYS_PINFUNC
);
43 /* reset the AC97 codec now, the reset time in the psc-ac97 driver
44 * is apparently too short although it's ridiculous as it is.
46 base
= (void __iomem
*)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR
);
47 __raw_writel(PSC_SEL_CLK_SERCLK
| PSC_SEL_PS_AC97MODE
,
48 base
+ PSC_SEL_OFFSET
);
49 __raw_writel(PSC_CTRL_DISABLE
, base
+ PSC_CTRL_OFFSET
);
51 __raw_writel(PSC_AC97RST_RST
, base
+ PSC_AC97RST_OFFSET
);
55 int __init
db1550_board_setup(void)
57 unsigned short whoami
;
59 bcsr_init(DB1550_BCSR_PHYS_ADDR
,
60 DB1550_BCSR_PHYS_ADDR
+ DB1550_BCSR_HEXLED_OFS
);
62 whoami
= bcsr_read(BCSR_WHOAMI
); /* PB1550 hexled offset differs */
63 switch (BCSR_WHOAMI_BOARD(whoami
)) {
64 case BCSR_WHOAMI_PB1550_SDR
:
65 case BCSR_WHOAMI_PB1550_DDR
:
66 bcsr_init(PB1550_BCSR_PHYS_ADDR
,
67 PB1550_BCSR_PHYS_ADDR
+ PB1550_BCSR_HEXLED_OFS
);
68 case BCSR_WHOAMI_DB1550
:
74 pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \
75 "Daughtercard ID %d\n", get_system_type(),
76 (whoami
>> 4) & 0xf, (whoami
>> 8) & 0xf, whoami
& 0xf);
82 /*****************************************************************************/
84 static struct mtd_partition db1550_spiflash_parts
[] = {
88 .size
= MTDPART_SIZ_FULL
,
92 static struct flash_platform_data db1550_spiflash_data
= {
94 .parts
= db1550_spiflash_parts
,
95 .nr_parts
= ARRAY_SIZE(db1550_spiflash_parts
),
99 static struct spi_board_info db1550_spi_devs
[] __initdata
= {
101 /* TI TMP121AIDBVR temp sensor */
102 .modalias
= "tmp121",
103 .max_speed_hz
= 2400000,
109 /* Spansion S25FL001D0FMA SPI flash */
110 .modalias
= "m25p80",
111 .max_speed_hz
= 2400000,
115 .platform_data
= &db1550_spiflash_data
,
119 static struct i2c_board_info db1550_i2c_devs
[] __initdata
= {
120 { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */
121 { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
122 { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
125 /**********************************************************************/
127 static void au1550_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
,
130 struct nand_chip
*this = mtd
->priv
;
131 unsigned long ioaddr
= (unsigned long)this->IO_ADDR_W
;
133 ioaddr
&= 0xffffff00;
135 if (ctrl
& NAND_CLE
) {
136 ioaddr
+= MEM_STNAND_CMD
;
137 } else if (ctrl
& NAND_ALE
) {
138 ioaddr
+= MEM_STNAND_ADDR
;
140 /* assume we want to r/w real data by default */
141 ioaddr
+= MEM_STNAND_DATA
;
143 this->IO_ADDR_R
= this->IO_ADDR_W
= (void __iomem
*)ioaddr
;
144 if (cmd
!= NAND_CMD_NONE
) {
145 __raw_writeb(cmd
, this->IO_ADDR_W
);
150 static int au1550_nand_device_ready(struct mtd_info
*mtd
)
152 return alchemy_rdsmem(AU1000_MEM_STSTAT
) & 1;
155 static struct mtd_partition db1550_nand_parts
[] = {
159 .size
= 8 * 1024 * 1024,
163 .offset
= MTDPART_OFS_APPEND
,
164 .size
= MTDPART_SIZ_FULL
168 struct platform_nand_data db1550_nand_platdata
= {
172 .nr_partitions
= ARRAY_SIZE(db1550_nand_parts
),
173 .partitions
= db1550_nand_parts
,
177 .dev_ready
= au1550_nand_device_ready
,
178 .cmd_ctrl
= au1550_nand_cmd_ctrl
,
182 static struct resource db1550_nand_res
[] = {
186 .flags
= IORESOURCE_MEM
,
190 static struct platform_device db1550_nand_dev
= {
192 .num_resources
= ARRAY_SIZE(db1550_nand_res
),
193 .resource
= db1550_nand_res
,
196 .platform_data
= &db1550_nand_platdata
,
200 static struct au1550nd_platdata pb1550_nand_pd
= {
201 .parts
= db1550_nand_parts
,
202 .num_parts
= ARRAY_SIZE(db1550_nand_parts
),
203 .devwidth
= 0, /* x8 NAND default, needs fixing up */
206 static struct platform_device pb1550_nand_dev
= {
207 .name
= "au1550-nand",
209 .resource
= db1550_nand_res
,
210 .num_resources
= ARRAY_SIZE(db1550_nand_res
),
212 .platform_data
= &pb1550_nand_pd
,
216 static void __init
pb1550_nand_setup(void)
218 int boot_swapboot
= (alchemy_rdsmem(AU1000_MEM_STSTAT
) & (0x7 << 1)) |
219 ((bcsr_read(BCSR_STATUS
) >> 6) & 0x1);
221 gpio_direction_input(206); /* de-assert NAND CS# */
222 switch (boot_swapboot
) {
223 case 0: case 2: case 8: case 0xC: case 0xD:
225 pb1550_nand_pd
.devwidth
= 1;
227 case 1: case 3: case 9: case 0xE: case 0xF:
228 /* x8 NAND, already set up */
229 platform_device_register(&pb1550_nand_dev
);
233 /**********************************************************************/
235 static struct resource au1550_psc0_res
[] = {
237 .start
= AU1550_PSC0_PHYS_ADDR
,
238 .end
= AU1550_PSC0_PHYS_ADDR
+ 0xfff,
239 .flags
= IORESOURCE_MEM
,
242 .start
= AU1550_PSC0_INT
,
243 .end
= AU1550_PSC0_INT
,
244 .flags
= IORESOURCE_IRQ
,
247 .start
= AU1550_DSCR_CMD0_PSC0_TX
,
248 .end
= AU1550_DSCR_CMD0_PSC0_TX
,
249 .flags
= IORESOURCE_DMA
,
252 .start
= AU1550_DSCR_CMD0_PSC0_RX
,
253 .end
= AU1550_DSCR_CMD0_PSC0_RX
,
254 .flags
= IORESOURCE_DMA
,
258 static void db1550_spi_cs_en(struct au1550_spi_info
*spi
, int cs
, int pol
)
261 bcsr_mod(BCSR_BOARD
, 0, BCSR_BOARD_SPISEL
);
263 bcsr_mod(BCSR_BOARD
, BCSR_BOARD_SPISEL
, 0);
266 static struct au1550_spi_info db1550_spi_platdata
= {
267 .mainclk_hz
= 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */
269 .activate_cs
= db1550_spi_cs_en
,
272 static u64 spi_dmamask
= DMA_BIT_MASK(32);
274 static struct platform_device db1550_spi_dev
= {
276 .dma_mask
= &spi_dmamask
,
277 .coherent_dma_mask
= DMA_BIT_MASK(32),
278 .platform_data
= &db1550_spi_platdata
,
280 .name
= "au1550-spi",
281 .id
= 0, /* bus number */
282 .num_resources
= ARRAY_SIZE(au1550_psc0_res
),
283 .resource
= au1550_psc0_res
,
286 /**********************************************************************/
288 static struct resource au1550_psc1_res
[] = {
290 .start
= AU1550_PSC1_PHYS_ADDR
,
291 .end
= AU1550_PSC1_PHYS_ADDR
+ 0xfff,
292 .flags
= IORESOURCE_MEM
,
295 .start
= AU1550_PSC1_INT
,
296 .end
= AU1550_PSC1_INT
,
297 .flags
= IORESOURCE_IRQ
,
300 .start
= AU1550_DSCR_CMD0_PSC1_TX
,
301 .end
= AU1550_DSCR_CMD0_PSC1_TX
,
302 .flags
= IORESOURCE_DMA
,
305 .start
= AU1550_DSCR_CMD0_PSC1_RX
,
306 .end
= AU1550_DSCR_CMD0_PSC1_RX
,
307 .flags
= IORESOURCE_DMA
,
311 static struct platform_device db1550_ac97_dev
= {
312 .name
= "au1xpsc_ac97",
313 .id
= 1, /* PSC ID */
314 .num_resources
= ARRAY_SIZE(au1550_psc1_res
),
315 .resource
= au1550_psc1_res
,
319 static struct resource au1550_psc2_res
[] = {
321 .start
= AU1550_PSC2_PHYS_ADDR
,
322 .end
= AU1550_PSC2_PHYS_ADDR
+ 0xfff,
323 .flags
= IORESOURCE_MEM
,
326 .start
= AU1550_PSC2_INT
,
327 .end
= AU1550_PSC2_INT
,
328 .flags
= IORESOURCE_IRQ
,
331 .start
= AU1550_DSCR_CMD0_PSC2_TX
,
332 .end
= AU1550_DSCR_CMD0_PSC2_TX
,
333 .flags
= IORESOURCE_DMA
,
336 .start
= AU1550_DSCR_CMD0_PSC2_RX
,
337 .end
= AU1550_DSCR_CMD0_PSC2_RX
,
338 .flags
= IORESOURCE_DMA
,
342 static struct platform_device db1550_i2c_dev
= {
343 .name
= "au1xpsc_smbus",
344 .id
= 0, /* bus number */
345 .num_resources
= ARRAY_SIZE(au1550_psc2_res
),
346 .resource
= au1550_psc2_res
,
349 /**********************************************************************/
351 static struct resource au1550_psc3_res
[] = {
353 .start
= AU1550_PSC3_PHYS_ADDR
,
354 .end
= AU1550_PSC3_PHYS_ADDR
+ 0xfff,
355 .flags
= IORESOURCE_MEM
,
358 .start
= AU1550_PSC3_INT
,
359 .end
= AU1550_PSC3_INT
,
360 .flags
= IORESOURCE_IRQ
,
363 .start
= AU1550_DSCR_CMD0_PSC3_TX
,
364 .end
= AU1550_DSCR_CMD0_PSC3_TX
,
365 .flags
= IORESOURCE_DMA
,
368 .start
= AU1550_DSCR_CMD0_PSC3_RX
,
369 .end
= AU1550_DSCR_CMD0_PSC3_RX
,
370 .flags
= IORESOURCE_DMA
,
374 static struct platform_device db1550_i2s_dev
= {
375 .name
= "au1xpsc_i2s",
376 .id
= 3, /* PSC ID */
377 .num_resources
= ARRAY_SIZE(au1550_psc3_res
),
378 .resource
= au1550_psc3_res
,
381 /**********************************************************************/
383 static struct platform_device db1550_stac_dev
= {
384 .name
= "ac97-codec",
385 .id
= 1, /* on PSC1 */
388 static struct platform_device db1550_ac97dma_dev
= {
389 .name
= "au1xpsc-pcm",
390 .id
= 1, /* on PSC3 */
393 static struct platform_device db1550_i2sdma_dev
= {
394 .name
= "au1xpsc-pcm",
395 .id
= 3, /* on PSC3 */
398 static struct platform_device db1550_sndac97_dev
= {
399 .name
= "db1550-ac97",
402 static struct platform_device db1550_sndi2s_dev
= {
403 .name
= "db1550-i2s",
406 /**********************************************************************/
408 static int db1550_map_pci_irq(const struct pci_dev
*d
, u8 slot
, u8 pin
)
410 if ((slot
< 11) || (slot
> 13) || pin
== 0)
413 return (pin
== 1) ? AU1550_PCI_INTC
: 0xff;
416 case 1: return AU1550_PCI_INTB
;
417 case 2: return AU1550_PCI_INTC
;
418 case 3: return AU1550_PCI_INTD
;
419 case 4: return AU1550_PCI_INTA
;
424 case 1: return AU1550_PCI_INTA
;
425 case 2: return AU1550_PCI_INTB
;
426 case 3: return AU1550_PCI_INTC
;
427 case 4: return AU1550_PCI_INTD
;
433 static int pb1550_map_pci_irq(const struct pci_dev
*d
, u8 slot
, u8 pin
)
435 if ((slot
< 12) || (slot
> 13) || pin
== 0)
439 case 1: return AU1500_PCI_INTB
;
440 case 2: return AU1500_PCI_INTC
;
441 case 3: return AU1500_PCI_INTD
;
442 case 4: return AU1500_PCI_INTA
;
447 case 1: return AU1500_PCI_INTA
;
448 case 2: return AU1500_PCI_INTB
;
449 case 3: return AU1500_PCI_INTC
;
450 case 4: return AU1500_PCI_INTD
;
456 static struct resource alchemy_pci_host_res
[] = {
458 .start
= AU1500_PCI_PHYS_ADDR
,
459 .end
= AU1500_PCI_PHYS_ADDR
+ 0xfff,
460 .flags
= IORESOURCE_MEM
,
464 static struct alchemy_pci_platdata db1550_pci_pd
= {
465 .board_map_irq
= db1550_map_pci_irq
,
468 static struct platform_device db1550_pci_host_dev
= {
469 .dev
.platform_data
= &db1550_pci_pd
,
470 .name
= "alchemy-pci",
472 .num_resources
= ARRAY_SIZE(alchemy_pci_host_res
),
473 .resource
= alchemy_pci_host_res
,
476 /**********************************************************************/
478 static struct platform_device
*db1550_devs
[] __initdata
= {
490 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
491 int __init
db1550_pci_setup(int id
)
494 db1550_pci_pd
.board_map_irq
= pb1550_map_pci_irq
;
495 return platform_device_register(&db1550_pci_host_dev
);
498 static void __init
db1550_devices(void)
500 alchemy_gpio_direction_output(203, 0); /* red led on */
502 irq_set_irq_type(AU1550_GPIO0_INT
, IRQ_TYPE_EDGE_BOTH
); /* CD0# */
503 irq_set_irq_type(AU1550_GPIO1_INT
, IRQ_TYPE_EDGE_BOTH
); /* CD1# */
504 irq_set_irq_type(AU1550_GPIO3_INT
, IRQ_TYPE_LEVEL_LOW
); /* CARD0# */
505 irq_set_irq_type(AU1550_GPIO5_INT
, IRQ_TYPE_LEVEL_LOW
); /* CARD1# */
506 irq_set_irq_type(AU1550_GPIO21_INT
, IRQ_TYPE_LEVEL_LOW
); /* STSCHG0# */
507 irq_set_irq_type(AU1550_GPIO22_INT
, IRQ_TYPE_LEVEL_LOW
); /* STSCHG1# */
509 db1x_register_pcmcia_socket(
510 AU1000_PCMCIA_ATTR_PHYS_ADDR
,
511 AU1000_PCMCIA_ATTR_PHYS_ADDR
+ 0x000400000 - 1,
512 AU1000_PCMCIA_MEM_PHYS_ADDR
,
513 AU1000_PCMCIA_MEM_PHYS_ADDR
+ 0x000400000 - 1,
514 AU1000_PCMCIA_IO_PHYS_ADDR
,
515 AU1000_PCMCIA_IO_PHYS_ADDR
+ 0x000010000 - 1,
516 AU1550_GPIO3_INT
, AU1550_GPIO0_INT
,
517 /*AU1550_GPIO21_INT*/0, 0, 0);
519 db1x_register_pcmcia_socket(
520 AU1000_PCMCIA_ATTR_PHYS_ADDR
+ 0x004000000,
521 AU1000_PCMCIA_ATTR_PHYS_ADDR
+ 0x004400000 - 1,
522 AU1000_PCMCIA_MEM_PHYS_ADDR
+ 0x004000000,
523 AU1000_PCMCIA_MEM_PHYS_ADDR
+ 0x004400000 - 1,
524 AU1000_PCMCIA_IO_PHYS_ADDR
+ 0x004000000,
525 AU1000_PCMCIA_IO_PHYS_ADDR
+ 0x004010000 - 1,
526 AU1550_GPIO5_INT
, AU1550_GPIO1_INT
,
527 /*AU1550_GPIO22_INT*/0, 0, 1);
529 platform_device_register(&db1550_nand_dev
);
531 alchemy_gpio_direction_output(202, 0); /* green led on */
534 static void __init
pb1550_devices(void)
536 irq_set_irq_type(AU1550_GPIO0_INT
, IRQ_TYPE_LEVEL_LOW
);
537 irq_set_irq_type(AU1550_GPIO1_INT
, IRQ_TYPE_LEVEL_LOW
);
538 irq_set_irq_type(AU1550_GPIO201_205_INT
, IRQ_TYPE_LEVEL_HIGH
);
540 /* enable both PCMCIA card irqs in the shared line */
541 alchemy_gpio2_enable_int(201); /* socket 0 card irq */
542 alchemy_gpio2_enable_int(202); /* socket 1 card irq */
544 /* Pb1550, like all others, also has statuschange irqs; however they're
545 * wired up on one of the Au1550's shared GPIO201_205 line, which also
546 * services the PCMCIA card interrupts. So we ignore statuschange and
547 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
548 * drivers are used to shared irqs and b) statuschange isn't really use-
551 db1x_register_pcmcia_socket(
552 AU1000_PCMCIA_ATTR_PHYS_ADDR
,
553 AU1000_PCMCIA_ATTR_PHYS_ADDR
+ 0x000400000 - 1,
554 AU1000_PCMCIA_MEM_PHYS_ADDR
,
555 AU1000_PCMCIA_MEM_PHYS_ADDR
+ 0x000400000 - 1,
556 AU1000_PCMCIA_IO_PHYS_ADDR
,
557 AU1000_PCMCIA_IO_PHYS_ADDR
+ 0x000010000 - 1,
558 AU1550_GPIO201_205_INT
, AU1550_GPIO0_INT
, 0, 0, 0);
560 db1x_register_pcmcia_socket(
561 AU1000_PCMCIA_ATTR_PHYS_ADDR
+ 0x008000000,
562 AU1000_PCMCIA_ATTR_PHYS_ADDR
+ 0x008400000 - 1,
563 AU1000_PCMCIA_MEM_PHYS_ADDR
+ 0x008000000,
564 AU1000_PCMCIA_MEM_PHYS_ADDR
+ 0x008400000 - 1,
565 AU1000_PCMCIA_IO_PHYS_ADDR
+ 0x008000000,
566 AU1000_PCMCIA_IO_PHYS_ADDR
+ 0x008010000 - 1,
567 AU1550_GPIO201_205_INT
, AU1550_GPIO1_INT
, 0, 0, 1);
572 int __init
db1550_dev_setup(void)
577 id
= (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI
)) != BCSR_WHOAMI_DB1550
);
579 i2c_register_board_info(0, db1550_i2c_devs
,
580 ARRAY_SIZE(db1550_i2c_devs
));
581 spi_register_board_info(db1550_spi_devs
,
582 ARRAY_SIZE(db1550_i2c_devs
));
584 c
= clk_get(NULL
, "psc0_intclk");
586 clk_set_rate(c
, 50000000);
587 clk_prepare_enable(c
);
590 c
= clk_get(NULL
, "psc2_intclk");
592 clk_set_rate(c
, db1550_spi_platdata
.mainclk_hz
);
593 clk_prepare_enable(c
);
597 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
598 __raw_writel(PSC_SEL_CLK_SERCLK
,
599 (void __iomem
*)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR
) + PSC_SEL_OFFSET
);
601 __raw_writel(PSC_SEL_CLK_SERCLK
,
602 (void __iomem
*)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR
) + PSC_SEL_OFFSET
);
604 /* SPI/I2C use internally supplied 50MHz source */
605 __raw_writel(PSC_SEL_CLK_INTCLK
,
606 (void __iomem
*)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR
) + PSC_SEL_OFFSET
);
608 __raw_writel(PSC_SEL_CLK_INTCLK
,
609 (void __iomem
*)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR
) + PSC_SEL_OFFSET
);
612 id
? pb1550_devices() : db1550_devices();
614 swapped
= bcsr_read(BCSR_STATUS
) &
615 (id
? BCSR_STATUS_PB1550_SWAPBOOT
: BCSR_STATUS_DB1000_SWAPBOOT
);
616 db1x_register_norflash(128 << 20, 4, swapped
);
618 return platform_add_devices(db1550_devs
, ARRAY_SIZE(db1550_devs
));