3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
5 * This device tree is pruned and patched by early boot code before
6 * use. Because of this, it contains a super-set of the available
7 * devices and properties.
10 compatible = "cavium,octeon-3860";
13 interrupt-parent = <&ciu>;
16 compatible = "simple-bus";
19 ranges; /* Direct mapping */
21 ciu: interrupt-controller@1070000000000 {
22 compatible = "cavium,octeon-3860-ciu";
24 /* Interrupts are specified by two parts:
25 * 1) Controller register (0 or 1)
26 * 2) Bit within the register (0..63)
28 #interrupt-cells = <2>;
29 reg = <0x10700 0x00000000 0x0 0x7000>;
32 gpio: gpio-controller@1070000000800 {
34 compatible = "cavium,octeon-3860-gpio";
35 reg = <0x10700 0x00000800 0x0 0x100>;
37 /* Interrupts are specified by two parts:
38 * 1) GPIO pin number (0..15)
39 * 2) Triggering (1 - edge rising
41 * 4 - level active high
42 * 8 - level active low)
45 #interrupt-cells = <2>;
46 /* The GPIO pin connect to 16 consecutive CUI bits */
47 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
48 <0 20>, <0 21>, <0 22>, <0 23>,
49 <0 24>, <0 25>, <0 26>, <0 27>,
50 <0 28>, <0 29>, <0 30>, <0 31>;
53 smi0: mdio@1180000001800 {
54 compatible = "cavium,octeon-3860-mdio";
57 reg = <0x11800 0x00001800 0x0 0x40>;
59 phy0: ethernet-phy@0 {
60 compatible = "marvell,88e1118";
62 /* Fix rx and tx clock transition timing */
63 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
64 /* Adjust LED drive. */
65 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
66 /* irq, blink-activity, blink-link */
67 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
71 phy1: ethernet-phy@1 {
72 compatible = "marvell,88e1118";
74 /* Fix rx and tx clock transition timing */
75 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
76 /* Adjust LED drive. */
77 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
78 /* irq, blink-activity, blink-link */
79 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
83 phy2: ethernet-phy@2 {
85 compatible = "marvell,88e1149r";
86 marvell,reg-init = <3 0x10 0 0x5777>,
91 phy3: ethernet-phy@3 {
93 compatible = "marvell,88e1149r";
94 marvell,reg-init = <3 0x10 0 0x5777>,
99 phy4: ethernet-phy@4 {
101 compatible = "marvell,88e1149r";
102 marvell,reg-init = <3 0x10 0 0x5777>,
107 phy5: ethernet-phy@5 {
109 compatible = "marvell,88e1149r";
110 marvell,reg-init = <3 0x10 0 0x5777>,
116 phy6: ethernet-phy@6 {
118 compatible = "marvell,88e1149r";
119 marvell,reg-init = <3 0x10 0 0x5777>,
124 phy7: ethernet-phy@7 {
126 compatible = "marvell,88e1149r";
127 marvell,reg-init = <3 0x10 0 0x5777>,
132 phy8: ethernet-phy@8 {
134 compatible = "marvell,88e1149r";
135 marvell,reg-init = <3 0x10 0 0x5777>,
140 phy9: ethernet-phy@9 {
142 compatible = "marvell,88e1149r";
143 marvell,reg-init = <3 0x10 0 0x5777>,
150 smi1: mdio@1180000001900 {
151 compatible = "cavium,octeon-3860-mdio";
152 #address-cells = <1>;
154 reg = <0x11800 0x00001900 0x0 0x40>;
156 phy100: ethernet-phy@1 {
158 compatible = "marvell,88e1149r";
159 marvell,reg-init = <3 0x10 0 0x5777>,
163 interrupt-parent = <&gpio>;
164 interrupts = <12 8>; /* Pin 12, active low */
166 phy101: ethernet-phy@2 {
168 compatible = "marvell,88e1149r";
169 marvell,reg-init = <3 0x10 0 0x5777>,
173 interrupt-parent = <&gpio>;
174 interrupts = <12 8>; /* Pin 12, active low */
176 phy102: ethernet-phy@3 {
178 compatible = "marvell,88e1149r";
179 marvell,reg-init = <3 0x10 0 0x5777>,
183 interrupt-parent = <&gpio>;
184 interrupts = <12 8>; /* Pin 12, active low */
186 phy103: ethernet-phy@4 {
188 compatible = "marvell,88e1149r";
189 marvell,reg-init = <3 0x10 0 0x5777>,
193 interrupt-parent = <&gpio>;
194 interrupts = <12 8>; /* Pin 12, active low */
198 mix0: ethernet@1070000100000 {
199 compatible = "cavium,octeon-5750-mix";
200 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
201 <0x11800 0xE0000000 0x0 0x300>, /* AGL */
202 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
203 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
205 interrupts = <0 62>, <1 46>;
206 local-mac-address = [ 00 00 00 00 00 00 ];
207 phy-handle = <&phy0>;
210 mix1: ethernet@1070000100800 {
211 compatible = "cavium,octeon-5750-mix";
212 reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
213 <0x11800 0xE0000800 0x0 0x300>, /* AGL */
214 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
215 <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */
217 interrupts = <1 18>, < 1 46>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 phy-handle = <&phy1>;
222 pip: pip@11800a0000000 {
223 compatible = "cavium,octeon-3860-pip";
224 #address-cells = <1>;
226 reg = <0x11800 0xa0000000 0x0 0x2000>;
229 compatible = "cavium,octeon-3860-pip-interface";
230 #address-cells = <1>;
232 reg = <0>; /* interface */
235 compatible = "cavium,octeon-3860-pip-port";
236 reg = <0x0>; /* Port */
237 local-mac-address = [ 00 00 00 00 00 00 ];
238 phy-handle = <&phy2>;
239 cavium,alt-phy-handle = <&phy100>;
242 compatible = "cavium,octeon-3860-pip-port";
243 reg = <0x1>; /* Port */
244 local-mac-address = [ 00 00 00 00 00 00 ];
245 phy-handle = <&phy3>;
246 cavium,alt-phy-handle = <&phy101>;
249 compatible = "cavium,octeon-3860-pip-port";
250 reg = <0x2>; /* Port */
251 local-mac-address = [ 00 00 00 00 00 00 ];
252 phy-handle = <&phy4>;
253 cavium,alt-phy-handle = <&phy102>;
256 compatible = "cavium,octeon-3860-pip-port";
257 reg = <0x3>; /* Port */
258 local-mac-address = [ 00 00 00 00 00 00 ];
259 phy-handle = <&phy5>;
260 cavium,alt-phy-handle = <&phy103>;
263 compatible = "cavium,octeon-3860-pip-port";
264 reg = <0x4>; /* Port */
265 local-mac-address = [ 00 00 00 00 00 00 ];
268 compatible = "cavium,octeon-3860-pip-port";
269 reg = <0x5>; /* Port */
270 local-mac-address = [ 00 00 00 00 00 00 ];
273 compatible = "cavium,octeon-3860-pip-port";
274 reg = <0x6>; /* Port */
275 local-mac-address = [ 00 00 00 00 00 00 ];
278 compatible = "cavium,octeon-3860-pip-port";
279 reg = <0x7>; /* Port */
280 local-mac-address = [ 00 00 00 00 00 00 ];
283 compatible = "cavium,octeon-3860-pip-port";
284 reg = <0x8>; /* Port */
285 local-mac-address = [ 00 00 00 00 00 00 ];
288 compatible = "cavium,octeon-3860-pip-port";
289 reg = <0x9>; /* Port */
290 local-mac-address = [ 00 00 00 00 00 00 ];
293 compatible = "cavium,octeon-3860-pip-port";
294 reg = <0xa>; /* Port */
295 local-mac-address = [ 00 00 00 00 00 00 ];
298 compatible = "cavium,octeon-3860-pip-port";
299 reg = <0xb>; /* Port */
300 local-mac-address = [ 00 00 00 00 00 00 ];
303 compatible = "cavium,octeon-3860-pip-port";
304 reg = <0xc>; /* Port */
305 local-mac-address = [ 00 00 00 00 00 00 ];
308 compatible = "cavium,octeon-3860-pip-port";
309 reg = <0xd>; /* Port */
310 local-mac-address = [ 00 00 00 00 00 00 ];
313 compatible = "cavium,octeon-3860-pip-port";
314 reg = <0xe>; /* Port */
315 local-mac-address = [ 00 00 00 00 00 00 ];
318 compatible = "cavium,octeon-3860-pip-port";
319 reg = <0xf>; /* Port */
320 local-mac-address = [ 00 00 00 00 00 00 ];
325 compatible = "cavium,octeon-3860-pip-interface";
326 #address-cells = <1>;
328 reg = <1>; /* interface */
331 compatible = "cavium,octeon-3860-pip-port";
332 reg = <0x0>; /* Port */
333 local-mac-address = [ 00 00 00 00 00 00 ];
334 phy-handle = <&phy6>;
337 compatible = "cavium,octeon-3860-pip-port";
338 reg = <0x1>; /* Port */
339 local-mac-address = [ 00 00 00 00 00 00 ];
340 phy-handle = <&phy7>;
343 compatible = "cavium,octeon-3860-pip-port";
344 reg = <0x2>; /* Port */
345 local-mac-address = [ 00 00 00 00 00 00 ];
346 phy-handle = <&phy8>;
349 compatible = "cavium,octeon-3860-pip-port";
350 reg = <0x3>; /* Port */
351 local-mac-address = [ 00 00 00 00 00 00 ];
352 phy-handle = <&phy9>;
357 twsi0: i2c@1180000001000 {
358 #address-cells = <1>;
360 compatible = "cavium,octeon-3860-twsi";
361 reg = <0x11800 0x00001000 0x0 0x200>;
363 clock-frequency = <100000>;
366 compatible = "dallas,ds1337";
370 compatible = "ti,tmp421";
375 twsi1: i2c@1180000001200 {
376 #address-cells = <1>;
378 compatible = "cavium,octeon-3860-twsi";
379 reg = <0x11800 0x00001200 0x0 0x200>;
381 clock-frequency = <100000>;
384 uart0: serial@1180000000800 {
385 compatible = "cavium,octeon-3860-uart","ns16550";
386 reg = <0x11800 0x00000800 0x0 0x400>;
387 clock-frequency = <0>;
388 current-speed = <115200>;
393 uart1: serial@1180000000c00 {
394 compatible = "cavium,octeon-3860-uart","ns16550";
395 reg = <0x11800 0x00000c00 0x0 0x400>;
396 clock-frequency = <0>;
397 current-speed = <115200>;
402 uart2: serial@1180000000400 {
403 compatible = "cavium,octeon-3860-uart","ns16550";
404 reg = <0x11800 0x00000400 0x0 0x400>;
405 clock-frequency = <0>;
406 current-speed = <115200>;
411 bootbus: bootbus@1180000000000 {
412 compatible = "cavium,octeon-3860-bootbus";
413 reg = <0x11800 0x00000000 0x0 0x200>;
414 /* The chip select number and offset */
415 #address-cells = <2>;
416 /* The size of the chip select region */
418 ranges = <0 0 0x0 0x1f400000 0xc00000>,
419 <1 0 0x10000 0x30000000 0>,
420 <2 0 0x10000 0x40000000 0>,
421 <3 0 0x10000 0x50000000 0>,
422 <4 0 0x0 0x1d020000 0x10000>,
423 <5 0 0x0 0x1d040000 0x10000>,
424 <6 0 0x0 0x1d050000 0x10000>,
425 <7 0 0x10000 0x90000000 0>;
428 compatible = "cavium,octeon-3860-bootbus-config";
429 cavium,cs-index = <0>;
434 cavium,t-rd-hld = <35>;
435 cavium,t-wr-hld = <45>;
436 cavium,t-pause = <0>;
438 cavium,t-page = <35>;
439 cavium,t-rd-dly = <0>;
442 cavium,bus-width = <8>;
445 compatible = "cavium,octeon-3860-bootbus-config";
446 cavium,cs-index = <4>;
447 cavium,t-adr = <320>;
451 cavium,t-rd-hld = <320>;
452 cavium,t-wr-hld = <320>;
453 cavium,t-pause = <320>;
454 cavium,t-wait = <320>;
455 cavium,t-page = <320>;
456 cavium,t-rd-dly = <0>;
459 cavium,bus-width = <8>;
462 compatible = "cavium,octeon-3860-bootbus-config";
463 cavium,cs-index = <5>;
468 cavium,t-rd-hld = <100>;
469 cavium,t-wr-hld = <30>;
470 cavium,t-pause = <0>;
471 cavium,t-wait = <30>;
472 cavium,t-page = <320>;
473 cavium,t-rd-dly = <0>;
476 cavium,bus-width = <16>;
479 compatible = "cavium,octeon-3860-bootbus-config";
480 cavium,cs-index = <6>;
485 cavium,t-rd-hld = <100>;
486 cavium,t-wr-hld = <70>;
487 cavium,t-pause = <0>;
489 cavium,t-page = <320>;
490 cavium,t-rd-dly = <0>;
494 cavium,bus-width = <16>;
498 compatible = "cfi-flash";
499 reg = <0 0 0x800000>;
500 #address-cells = <1>;
504 led0: led-display@4,0 {
505 compatible = "avago,hdsp-253x";
506 reg = <4 0x20 0x20>, <4 0 0x20>;
509 cf0: compact-flash@5,0 {
510 compatible = "cavium,ebt3000-compact-flash";
511 reg = <5 0 0x10000>, <6 0 0x10000>;
512 cavium,bus-width = <16>;
514 cavium,dma-engine-handle = <&dma0>;
518 dma0: dma-engine@1180000000100 {
519 compatible = "cavium,octeon-5750-bootbus-dma";
520 reg = <0x11800 0x00000100 0x0 0x8>;
523 dma1: dma-engine@1180000000108 {
524 compatible = "cavium,octeon-5750-bootbus-dma";
525 reg = <0x11800 0x00000108 0x0 0x8>;
529 uctl: uctl@118006f000000 {
530 compatible = "cavium,octeon-6335-uctl";
531 reg = <0x11800 0x6f000000 0x0 0x100>;
532 ranges; /* Direct mapping */
533 #address-cells = <2>;
535 /* 12MHz, 24MHz and 48MHz allowed */
536 refclk-frequency = <12000000>;
537 /* Either "crystal" or "external" */
538 refclk-type = "crystal";
541 compatible = "cavium,octeon-6335-ehci","usb-ehci";
542 reg = <0x16f00 0x00000000 0x0 0x100>;
547 compatible = "cavium,octeon-6335-ohci","usb-ohci";
548 reg = <0x16f00 0x00000400 0x0 0x100>;
554 usbn: usbn@1180068000000 {
555 compatible = "cavium,octeon-5750-usbn";
556 reg = <0x11800 0x68000000 0x0 0x1000>;
557 ranges; /* Direct mapping */
558 #address-cells = <2>;
560 /* 12MHz, 24MHz and 48MHz allowed */
561 refclk-frequency = <12000000>;
562 /* Either "crystal" or "external" */
563 refclk-type = "crystal";
566 compatible = "cavium,octeon-5750-usbc";
567 reg = <0x16f00 0x10000000 0x0 0x80000>;
592 compatible = "gpio-leds";
595 gpios = <&gpio 9 1>; /* Active low */
599 gpios = <&gpio 10 1>; /* Active low */