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Linux 4.1.18
[linux/fpc-iii.git] / arch / mips / kvm / mips.c
blob22ee0afc7d5dc3e01bde825c3ef83c97d0b464ca
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/kdebug.h>
15 #include <linux/module.h>
16 #include <linux/vmalloc.h>
17 #include <linux/fs.h>
18 #include <linux/bootmem.h>
19 #include <asm/fpu.h>
20 #include <asm/page.h>
21 #include <asm/cacheflush.h>
22 #include <asm/mmu_context.h>
23 #include <asm/pgtable.h>
24
25 #include <linux/kvm_host.h>
26
27 #include "interrupt.h"
28 #include "commpage.h"
29
30 #define CREATE_TRACE_POINTS
31 #include "trace.h"
32
33 #ifndef VECTORSPACING
34 #define VECTORSPACING 0x100 /* for EI/VI mode */
35 #endif
36
37 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
38 struct kvm_stats_debugfs_item debugfs_entries[] = {
39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
53 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
54 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
55 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
56 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
58 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
59 {NULL}
60 };
61
62 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
63 {
64 int i;
65
66 for_each_possible_cpu(i) {
67 vcpu->arch.guest_kernel_asid[i] = 0;
68 vcpu->arch.guest_user_asid[i] = 0;
69 }
70
71 return 0;
72 }
73
74 /*
75 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
76 * Config7, so we are "runnable" if interrupts are pending
77 */
78 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
79 {
80 return !!(vcpu->arch.pending_exceptions);
81 }
82
83 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
84 {
85 return 1;
86 }
87
88 int kvm_arch_hardware_enable(void)
89 {
90 return 0;
91 }
92
93 int kvm_arch_hardware_setup(void)
94 {
95 return 0;
96 }
97
98 void kvm_arch_check_processor_compat(void *rtn)
99 {
100 *(int *)rtn = 0;
101 }
102
103 static void kvm_mips_init_tlbs(struct kvm *kvm)
104 {
105 unsigned long wired;
106
107 /*
108 * Add a wired entry to the TLB, it is used to map the commpage to
109 * the Guest kernel
110 */
111 wired = read_c0_wired();
112 write_c0_wired(wired + 1);
113 mtc0_tlbw_hazard();
114 kvm->arch.commpage_tlb = wired;
115
116 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
117 kvm->arch.commpage_tlb);
118 }
119
120 static void kvm_mips_init_vm_percpu(void *arg)
121 {
122 struct kvm *kvm = (struct kvm *)arg;
123
124 kvm_mips_init_tlbs(kvm);
125 kvm_mips_callbacks->vm_init(kvm);
126
127 }
128
129 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
130 {
131 if (atomic_inc_return(&kvm_mips_instance) == 1) {
132 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
133 __func__);
134 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
135 }
136
137 return 0;
138 }
139
140 void kvm_mips_free_vcpus(struct kvm *kvm)
141 {
142 unsigned int i;
143 struct kvm_vcpu *vcpu;
144
145 /* Put the pages we reserved for the guest pmap */
146 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
147 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
148 kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]);
149 }
150 kfree(kvm->arch.guest_pmap);
151
152 kvm_for_each_vcpu(i, vcpu, kvm) {
153 kvm_arch_vcpu_free(vcpu);
154 }
155
156 mutex_lock(&kvm->lock);
157
158 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
159 kvm->vcpus[i] = NULL;
160
161 atomic_set(&kvm->online_vcpus, 0);
162
163 mutex_unlock(&kvm->lock);
164 }
165
166 static void kvm_mips_uninit_tlbs(void *arg)
167 {
168 /* Restore wired count */
169 write_c0_wired(0);
170 mtc0_tlbw_hazard();
171 /* Clear out all the TLBs */
172 kvm_local_flush_tlb_all();
173 }
174
175 void kvm_arch_destroy_vm(struct kvm *kvm)
176 {
177 kvm_mips_free_vcpus(kvm);
178
179 /* If this is the last instance, restore wired count */
180 if (atomic_dec_return(&kvm_mips_instance) == 0) {
181 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
182 __func__);
183 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
184 }
185 }
186
187 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
188 unsigned long arg)
189 {
190 return -ENOIOCTLCMD;
191 }
192
193 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
194 unsigned long npages)
195 {
196 return 0;
197 }
198
199 int kvm_arch_prepare_memory_region(struct kvm *kvm,
200 struct kvm_memory_slot *memslot,
201 struct kvm_userspace_memory_region *mem,
202 enum kvm_mr_change change)
203 {
204 return 0;
205 }
206
207 void kvm_arch_commit_memory_region(struct kvm *kvm,
208 struct kvm_userspace_memory_region *mem,
209 const struct kvm_memory_slot *old,
210 enum kvm_mr_change change)
211 {
212 unsigned long npages = 0;
213 int i;
214
215 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
216 __func__, kvm, mem->slot, mem->guest_phys_addr,
217 mem->memory_size, mem->userspace_addr);
218
219 /* Setup Guest PMAP table */
220 if (!kvm->arch.guest_pmap) {
221 if (mem->slot == 0)
222 npages = mem->memory_size >> PAGE_SHIFT;
223
224 if (npages) {
225 kvm->arch.guest_pmap_npages = npages;
226 kvm->arch.guest_pmap =
227 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
228
229 if (!kvm->arch.guest_pmap) {
230 kvm_err("Failed to allocate guest PMAP");
231 return;
232 }
233
234 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
235 npages, kvm->arch.guest_pmap);
236
237 /* Now setup the page table */
238 for (i = 0; i < npages; i++)
239 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
240 }
241 }
242 }
243
244 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
245 {
246 int err, size, offset;
247 void *gebase;
248 int i;
249
250 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
251
252 if (!vcpu) {
253 err = -ENOMEM;
254 goto out;
255 }
256
257 err = kvm_vcpu_init(vcpu, kvm, id);
258
259 if (err)
260 goto out_free_cpu;
261
262 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
263
264 /*
265 * Allocate space for host mode exception handlers that handle
266 * guest mode exits
267 */
268 if (cpu_has_veic || cpu_has_vint)
269 size = 0x200 + VECTORSPACING * 64;
270 else
271 size = 0x4000;
272
273 /* Save Linux EBASE */
274 vcpu->arch.host_ebase = (void *)read_c0_ebase();
275
276 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
277
278 if (!gebase) {
279 err = -ENOMEM;
280 goto out_uninit_cpu;
281 }
282 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
283 ALIGN(size, PAGE_SIZE), gebase);
284
285 /* Save new ebase */
286 vcpu->arch.guest_ebase = gebase;
287
288 /* Copy L1 Guest Exception handler to correct offset */
289
290 /* TLB Refill, EXL = 0 */
291 memcpy(gebase, mips32_exception,
292 mips32_exceptionEnd - mips32_exception);
293
294 /* General Exception Entry point */
295 memcpy(gebase + 0x180, mips32_exception,
296 mips32_exceptionEnd - mips32_exception);
297
298 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
299 for (i = 0; i < 8; i++) {
300 kvm_debug("L1 Vectored handler @ %p\n",
301 gebase + 0x200 + (i * VECTORSPACING));
302 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
303 mips32_exceptionEnd - mips32_exception);
304 }
305
306 /* General handler, relocate to unmapped space for sanity's sake */
307 offset = 0x2000;
308 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
309 gebase + offset,
310 mips32_GuestExceptionEnd - mips32_GuestException);
311
312 memcpy(gebase + offset, mips32_GuestException,
313 mips32_GuestExceptionEnd - mips32_GuestException);
314
315 /* Invalidate the icache for these ranges */
316 local_flush_icache_range((unsigned long)gebase,
317 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
318
319 /*
320 * Allocate comm page for guest kernel, a TLB will be reserved for
321 * mapping GVA @ 0xFFFF8000 to this page
322 */
323 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
324
325 if (!vcpu->arch.kseg0_commpage) {
326 err = -ENOMEM;
327 goto out_free_gebase;
328 }
329
330 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
331 kvm_mips_commpage_init(vcpu);
332
333 /* Init */
334 vcpu->arch.last_sched_cpu = -1;
335
336 /* Start off the timer */
337 kvm_mips_init_count(vcpu);
338
339 return vcpu;
340
341 out_free_gebase:
342 kfree(gebase);
343
344 out_uninit_cpu:
345 kvm_vcpu_uninit(vcpu);
346
347 out_free_cpu:
348 kfree(vcpu);
349
350 out:
351 return ERR_PTR(err);
352 }
353
354 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
355 {
356 hrtimer_cancel(&vcpu->arch.comparecount_timer);
357
358 kvm_vcpu_uninit(vcpu);
359
360 kvm_mips_dump_stats(vcpu);
361
362 kfree(vcpu->arch.guest_ebase);
363 kfree(vcpu->arch.kseg0_commpage);
364 kfree(vcpu);
365 }
366
367 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
368 {
369 kvm_arch_vcpu_free(vcpu);
370 }
371
372 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
373 struct kvm_guest_debug *dbg)
374 {
375 return -ENOIOCTLCMD;
376 }
377
378 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
379 {
380 int r = 0;
381 sigset_t sigsaved;
382
383 if (vcpu->sigset_active)
384 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
385
386 if (vcpu->mmio_needed) {
387 if (!vcpu->mmio_is_write)
388 kvm_mips_complete_mmio_load(vcpu, run);
389 vcpu->mmio_needed = 0;
390 }
391
392 lose_fpu(1);
393
394 local_irq_disable();
395 /* Check if we have any exceptions/interrupts pending */
396 kvm_mips_deliver_interrupts(vcpu,
397 kvm_read_c0_guest_cause(vcpu->arch.cop0));
398
399 kvm_guest_enter();
400
401 /* Disable hardware page table walking while in guest */
402 htw_stop();
403
404 r = __kvm_mips_vcpu_run(run, vcpu);
405
406 /* Re-enable HTW before enabling interrupts */
407 htw_start();
408
409 kvm_guest_exit();
410 local_irq_enable();
411
412 if (vcpu->sigset_active)
413 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
414
415 return r;
416 }
417
418 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
419 struct kvm_mips_interrupt *irq)
420 {
421 int intr = (int)irq->irq;
422 struct kvm_vcpu *dvcpu = NULL;
423
424 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
425 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
426 (int)intr);
427
428 if (irq->cpu == -1)
429 dvcpu = vcpu;
430 else
431 dvcpu = vcpu->kvm->vcpus[irq->cpu];
432
433 if (intr == 2 || intr == 3 || intr == 4) {
434 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
435
436 } else if (intr == -2 || intr == -3 || intr == -4) {
437 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
438 } else {
439 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
440 irq->cpu, irq->irq);
441 return -EINVAL;
442 }
443
444 dvcpu->arch.wait = 0;
445
446 if (waitqueue_active(&dvcpu->wq))
447 wake_up_interruptible(&dvcpu->wq);
448
449 return 0;
450 }
451
452 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
453 struct kvm_mp_state *mp_state)
454 {
455 return -ENOIOCTLCMD;
456 }
457
458 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
459 struct kvm_mp_state *mp_state)
460 {
461 return -ENOIOCTLCMD;
462 }
463
464 static u64 kvm_mips_get_one_regs[] = {
465 KVM_REG_MIPS_R0,
466 KVM_REG_MIPS_R1,
467 KVM_REG_MIPS_R2,
468 KVM_REG_MIPS_R3,
469 KVM_REG_MIPS_R4,
470 KVM_REG_MIPS_R5,
471 KVM_REG_MIPS_R6,
472 KVM_REG_MIPS_R7,
473 KVM_REG_MIPS_R8,
474 KVM_REG_MIPS_R9,
475 KVM_REG_MIPS_R10,
476 KVM_REG_MIPS_R11,
477 KVM_REG_MIPS_R12,
478 KVM_REG_MIPS_R13,
479 KVM_REG_MIPS_R14,
480 KVM_REG_MIPS_R15,
481 KVM_REG_MIPS_R16,
482 KVM_REG_MIPS_R17,
483 KVM_REG_MIPS_R18,
484 KVM_REG_MIPS_R19,
485 KVM_REG_MIPS_R20,
486 KVM_REG_MIPS_R21,
487 KVM_REG_MIPS_R22,
488 KVM_REG_MIPS_R23,
489 KVM_REG_MIPS_R24,
490 KVM_REG_MIPS_R25,
491 KVM_REG_MIPS_R26,
492 KVM_REG_MIPS_R27,
493 KVM_REG_MIPS_R28,
494 KVM_REG_MIPS_R29,
495 KVM_REG_MIPS_R30,
496 KVM_REG_MIPS_R31,
497
498 KVM_REG_MIPS_HI,
499 KVM_REG_MIPS_LO,
500 KVM_REG_MIPS_PC,
501
502 KVM_REG_MIPS_CP0_INDEX,
503 KVM_REG_MIPS_CP0_CONTEXT,
504 KVM_REG_MIPS_CP0_USERLOCAL,
505 KVM_REG_MIPS_CP0_PAGEMASK,
506 KVM_REG_MIPS_CP0_WIRED,
507 KVM_REG_MIPS_CP0_HWRENA,
508 KVM_REG_MIPS_CP0_BADVADDR,
509 KVM_REG_MIPS_CP0_COUNT,
510 KVM_REG_MIPS_CP0_ENTRYHI,
511 KVM_REG_MIPS_CP0_COMPARE,
512 KVM_REG_MIPS_CP0_STATUS,
513 KVM_REG_MIPS_CP0_CAUSE,
514 KVM_REG_MIPS_CP0_EPC,
515 KVM_REG_MIPS_CP0_PRID,
516 KVM_REG_MIPS_CP0_CONFIG,
517 KVM_REG_MIPS_CP0_CONFIG1,
518 KVM_REG_MIPS_CP0_CONFIG2,
519 KVM_REG_MIPS_CP0_CONFIG3,
520 KVM_REG_MIPS_CP0_CONFIG4,
521 KVM_REG_MIPS_CP0_CONFIG5,
522 KVM_REG_MIPS_CP0_CONFIG7,
523 KVM_REG_MIPS_CP0_ERROREPC,
524
525 KVM_REG_MIPS_COUNT_CTL,
526 KVM_REG_MIPS_COUNT_RESUME,
527 KVM_REG_MIPS_COUNT_HZ,
528 };
529
530 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
531 const struct kvm_one_reg *reg)
532 {
533 struct mips_coproc *cop0 = vcpu->arch.cop0;
534 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
535 int ret;
536 s64 v;
537 s64 vs[2];
538 unsigned int idx;
539
540 switch (reg->id) {
541 /* General purpose registers */
542 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
543 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
544 break;
545 case KVM_REG_MIPS_HI:
546 v = (long)vcpu->arch.hi;
547 break;
548 case KVM_REG_MIPS_LO:
549 v = (long)vcpu->arch.lo;
550 break;
551 case KVM_REG_MIPS_PC:
552 v = (long)vcpu->arch.pc;
553 break;
554
555 /* Floating point registers */
556 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
557 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
558 return -EINVAL;
559 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
560 /* Odd singles in top of even double when FR=0 */
561 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
562 v = get_fpr32(&fpu->fpr[idx], 0);
563 else
564 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
565 break;
566 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
567 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
568 return -EINVAL;
569 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
570 /* Can't access odd doubles in FR=0 mode */
571 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
572 return -EINVAL;
573 v = get_fpr64(&fpu->fpr[idx], 0);
574 break;
575 case KVM_REG_MIPS_FCR_IR:
576 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
577 return -EINVAL;
578 v = boot_cpu_data.fpu_id;
579 break;
580 case KVM_REG_MIPS_FCR_CSR:
581 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
582 return -EINVAL;
583 v = fpu->fcr31;
584 break;
585
586 /* MIPS SIMD Architecture (MSA) registers */
587 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
588 if (!kvm_mips_guest_has_msa(&vcpu->arch))
589 return -EINVAL;
590 /* Can't access MSA registers in FR=0 mode */
591 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
592 return -EINVAL;
593 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
594 #ifdef CONFIG_CPU_LITTLE_ENDIAN
595 /* least significant byte first */
596 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
597 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
598 #else
599 /* most significant byte first */
600 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
601 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
602 #endif
603 break;
604 case KVM_REG_MIPS_MSA_IR:
605 if (!kvm_mips_guest_has_msa(&vcpu->arch))
606 return -EINVAL;
607 v = boot_cpu_data.msa_id;
608 break;
609 case KVM_REG_MIPS_MSA_CSR:
610 if (!kvm_mips_guest_has_msa(&vcpu->arch))
611 return -EINVAL;
612 v = fpu->msacsr;
613 break;
614
615 /* Co-processor 0 registers */
616 case KVM_REG_MIPS_CP0_INDEX:
617 v = (long)kvm_read_c0_guest_index(cop0);
618 break;
619 case KVM_REG_MIPS_CP0_CONTEXT:
620 v = (long)kvm_read_c0_guest_context(cop0);
621 break;
622 case KVM_REG_MIPS_CP0_USERLOCAL:
623 v = (long)kvm_read_c0_guest_userlocal(cop0);
624 break;
625 case KVM_REG_MIPS_CP0_PAGEMASK:
626 v = (long)kvm_read_c0_guest_pagemask(cop0);
627 break;
628 case KVM_REG_MIPS_CP0_WIRED:
629 v = (long)kvm_read_c0_guest_wired(cop0);
630 break;
631 case KVM_REG_MIPS_CP0_HWRENA:
632 v = (long)kvm_read_c0_guest_hwrena(cop0);
633 break;
634 case KVM_REG_MIPS_CP0_BADVADDR:
635 v = (long)kvm_read_c0_guest_badvaddr(cop0);
636 break;
637 case KVM_REG_MIPS_CP0_ENTRYHI:
638 v = (long)kvm_read_c0_guest_entryhi(cop0);
639 break;
640 case KVM_REG_MIPS_CP0_COMPARE:
641 v = (long)kvm_read_c0_guest_compare(cop0);
642 break;
643 case KVM_REG_MIPS_CP0_STATUS:
644 v = (long)kvm_read_c0_guest_status(cop0);
645 break;
646 case KVM_REG_MIPS_CP0_CAUSE:
647 v = (long)kvm_read_c0_guest_cause(cop0);
648 break;
649 case KVM_REG_MIPS_CP0_EPC:
650 v = (long)kvm_read_c0_guest_epc(cop0);
651 break;
652 case KVM_REG_MIPS_CP0_PRID:
653 v = (long)kvm_read_c0_guest_prid(cop0);
654 break;
655 case KVM_REG_MIPS_CP0_CONFIG:
656 v = (long)kvm_read_c0_guest_config(cop0);
657 break;
658 case KVM_REG_MIPS_CP0_CONFIG1:
659 v = (long)kvm_read_c0_guest_config1(cop0);
660 break;
661 case KVM_REG_MIPS_CP0_CONFIG2:
662 v = (long)kvm_read_c0_guest_config2(cop0);
663 break;
664 case KVM_REG_MIPS_CP0_CONFIG3:
665 v = (long)kvm_read_c0_guest_config3(cop0);
666 break;
667 case KVM_REG_MIPS_CP0_CONFIG4:
668 v = (long)kvm_read_c0_guest_config4(cop0);
669 break;
670 case KVM_REG_MIPS_CP0_CONFIG5:
671 v = (long)kvm_read_c0_guest_config5(cop0);
672 break;
673 case KVM_REG_MIPS_CP0_CONFIG7:
674 v = (long)kvm_read_c0_guest_config7(cop0);
675 break;
676 case KVM_REG_MIPS_CP0_ERROREPC:
677 v = (long)kvm_read_c0_guest_errorepc(cop0);
678 break;
679 /* registers to be handled specially */
680 case KVM_REG_MIPS_CP0_COUNT:
681 case KVM_REG_MIPS_COUNT_CTL:
682 case KVM_REG_MIPS_COUNT_RESUME:
683 case KVM_REG_MIPS_COUNT_HZ:
684 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
685 if (ret)
686 return ret;
687 break;
688 default:
689 return -EINVAL;
690 }
691 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
692 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
693
694 return put_user(v, uaddr64);
695 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
696 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
697 u32 v32 = (u32)v;
698
699 return put_user(v32, uaddr32);
700 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
701 void __user *uaddr = (void __user *)(long)reg->addr;
702
703 return copy_to_user(uaddr, vs, 16);
704 } else {
705 return -EINVAL;
706 }
707 }
708
709 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
710 const struct kvm_one_reg *reg)
711 {
712 struct mips_coproc *cop0 = vcpu->arch.cop0;
713 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
714 s64 v;
715 s64 vs[2];
716 unsigned int idx;
717
718 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
719 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
720
721 if (get_user(v, uaddr64) != 0)
722 return -EFAULT;
723 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
724 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
725 s32 v32;
726
727 if (get_user(v32, uaddr32) != 0)
728 return -EFAULT;
729 v = (s64)v32;
730 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
731 void __user *uaddr = (void __user *)(long)reg->addr;
732
733 return copy_from_user(vs, uaddr, 16);
734 } else {
735 return -EINVAL;
736 }
737
738 switch (reg->id) {
739 /* General purpose registers */
740 case KVM_REG_MIPS_R0:
741 /* Silently ignore requests to set $0 */
742 break;
743 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
744 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
745 break;
746 case KVM_REG_MIPS_HI:
747 vcpu->arch.hi = v;
748 break;
749 case KVM_REG_MIPS_LO:
750 vcpu->arch.lo = v;
751 break;
752 case KVM_REG_MIPS_PC:
753 vcpu->arch.pc = v;
754 break;
755
756 /* Floating point registers */
757 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
758 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
759 return -EINVAL;
760 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
761 /* Odd singles in top of even double when FR=0 */
762 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
763 set_fpr32(&fpu->fpr[idx], 0, v);
764 else
765 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
766 break;
767 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
768 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
769 return -EINVAL;
770 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
771 /* Can't access odd doubles in FR=0 mode */
772 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
773 return -EINVAL;
774 set_fpr64(&fpu->fpr[idx], 0, v);
775 break;
776 case KVM_REG_MIPS_FCR_IR:
777 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
778 return -EINVAL;
779 /* Read-only */
780 break;
781 case KVM_REG_MIPS_FCR_CSR:
782 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
783 return -EINVAL;
784 fpu->fcr31 = v;
785 break;
786
787 /* MIPS SIMD Architecture (MSA) registers */
788 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
789 if (!kvm_mips_guest_has_msa(&vcpu->arch))
790 return -EINVAL;
791 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
792 #ifdef CONFIG_CPU_LITTLE_ENDIAN
793 /* least significant byte first */
794 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
795 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
796 #else
797 /* most significant byte first */
798 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
799 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
800 #endif
801 break;
802 case KVM_REG_MIPS_MSA_IR:
803 if (!kvm_mips_guest_has_msa(&vcpu->arch))
804 return -EINVAL;
805 /* Read-only */
806 break;
807 case KVM_REG_MIPS_MSA_CSR:
808 if (!kvm_mips_guest_has_msa(&vcpu->arch))
809 return -EINVAL;
810 fpu->msacsr = v;
811 break;
812
813 /* Co-processor 0 registers */
814 case KVM_REG_MIPS_CP0_INDEX:
815 kvm_write_c0_guest_index(cop0, v);
816 break;
817 case KVM_REG_MIPS_CP0_CONTEXT:
818 kvm_write_c0_guest_context(cop0, v);
819 break;
820 case KVM_REG_MIPS_CP0_USERLOCAL:
821 kvm_write_c0_guest_userlocal(cop0, v);
822 break;
823 case KVM_REG_MIPS_CP0_PAGEMASK:
824 kvm_write_c0_guest_pagemask(cop0, v);
825 break;
826 case KVM_REG_MIPS_CP0_WIRED:
827 kvm_write_c0_guest_wired(cop0, v);
828 break;
829 case KVM_REG_MIPS_CP0_HWRENA:
830 kvm_write_c0_guest_hwrena(cop0, v);
831 break;
832 case KVM_REG_MIPS_CP0_BADVADDR:
833 kvm_write_c0_guest_badvaddr(cop0, v);
834 break;
835 case KVM_REG_MIPS_CP0_ENTRYHI:
836 kvm_write_c0_guest_entryhi(cop0, v);
837 break;
838 case KVM_REG_MIPS_CP0_STATUS:
839 kvm_write_c0_guest_status(cop0, v);
840 break;
841 case KVM_REG_MIPS_CP0_EPC:
842 kvm_write_c0_guest_epc(cop0, v);
843 break;
844 case KVM_REG_MIPS_CP0_PRID:
845 kvm_write_c0_guest_prid(cop0, v);
846 break;
847 case KVM_REG_MIPS_CP0_ERROREPC:
848 kvm_write_c0_guest_errorepc(cop0, v);
849 break;
850 /* registers to be handled specially */
851 case KVM_REG_MIPS_CP0_COUNT:
852 case KVM_REG_MIPS_CP0_COMPARE:
853 case KVM_REG_MIPS_CP0_CAUSE:
854 case KVM_REG_MIPS_CP0_CONFIG:
855 case KVM_REG_MIPS_CP0_CONFIG1:
856 case KVM_REG_MIPS_CP0_CONFIG2:
857 case KVM_REG_MIPS_CP0_CONFIG3:
858 case KVM_REG_MIPS_CP0_CONFIG4:
859 case KVM_REG_MIPS_CP0_CONFIG5:
860 case KVM_REG_MIPS_COUNT_CTL:
861 case KVM_REG_MIPS_COUNT_RESUME:
862 case KVM_REG_MIPS_COUNT_HZ:
863 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
864 default:
865 return -EINVAL;
866 }
867 return 0;
868 }
869
870 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
871 struct kvm_enable_cap *cap)
872 {
873 int r = 0;
874
875 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
876 return -EINVAL;
877 if (cap->flags)
878 return -EINVAL;
879 if (cap->args[0])
880 return -EINVAL;
881
882 switch (cap->cap) {
883 case KVM_CAP_MIPS_FPU:
884 vcpu->arch.fpu_enabled = true;
885 break;
886 case KVM_CAP_MIPS_MSA:
887 vcpu->arch.msa_enabled = true;
888 break;
889 default:
890 r = -EINVAL;
891 break;
892 }
893
894 return r;
895 }
896
897 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
898 unsigned long arg)
899 {
900 struct kvm_vcpu *vcpu = filp->private_data;
901 void __user *argp = (void __user *)arg;
902 long r;
903
904 switch (ioctl) {
905 case KVM_SET_ONE_REG:
906 case KVM_GET_ONE_REG: {
907 struct kvm_one_reg reg;
908
909 if (copy_from_user(&reg, argp, sizeof(reg)))
910 return -EFAULT;
911 if (ioctl == KVM_SET_ONE_REG)
912 return kvm_mips_set_reg(vcpu, &reg);
913 else
914 return kvm_mips_get_reg(vcpu, &reg);
915 }
916 case KVM_GET_REG_LIST: {
917 struct kvm_reg_list __user *user_list = argp;
918 u64 __user *reg_dest;
919 struct kvm_reg_list reg_list;
920 unsigned n;
921
922 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
923 return -EFAULT;
924 n = reg_list.n;
925 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
926 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
927 return -EFAULT;
928 if (n < reg_list.n)
929 return -E2BIG;
930 reg_dest = user_list->reg;
931 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
932 sizeof(kvm_mips_get_one_regs)))
933 return -EFAULT;
934 return 0;
935 }
936 case KVM_NMI:
937 /* Treat the NMI as a CPU reset */
938 r = kvm_mips_reset_vcpu(vcpu);
939 break;
940 case KVM_INTERRUPT:
941 {
942 struct kvm_mips_interrupt irq;
943
944 r = -EFAULT;
945 if (copy_from_user(&irq, argp, sizeof(irq)))
946 goto out;
947
948 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
949 irq.irq);
950
951 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
952 break;
953 }
954 case KVM_ENABLE_CAP: {
955 struct kvm_enable_cap cap;
956
957 r = -EFAULT;
958 if (copy_from_user(&cap, argp, sizeof(cap)))
959 goto out;
960 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
961 break;
962 }
963 default:
964 r = -ENOIOCTLCMD;
965 }
966
967 out:
968 return r;
969 }
970
971 /* Get (and clear) the dirty memory log for a memory slot. */
972 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
973 {
974 struct kvm_memory_slot *memslot;
975 unsigned long ga, ga_end;
976 int is_dirty = 0;
977 int r;
978 unsigned long n;
979
980 mutex_lock(&kvm->slots_lock);
981
982 r = kvm_get_dirty_log(kvm, log, &is_dirty);
983 if (r)
984 goto out;
985
986 /* If nothing is dirty, don't bother messing with page tables. */
987 if (is_dirty) {
988 memslot = id_to_memslot(kvm->memslots, log->slot);
989
990 ga = memslot->base_gfn << PAGE_SHIFT;
991 ga_end = ga + (memslot->npages << PAGE_SHIFT);
992
993 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
994 ga_end);
995
996 n = kvm_dirty_bitmap_bytes(memslot);
997 memset(memslot->dirty_bitmap, 0, n);
998 }
999
1000 r = 0;
1001 out:
1002 mutex_unlock(&kvm->slots_lock);
1003 return r;
1004
1005 }
1006
1007 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1008 {
1009 long r;
1010
1011 switch (ioctl) {
1012 default:
1013 r = -ENOIOCTLCMD;
1014 }
1015
1016 return r;
1017 }
1018
1019 int kvm_arch_init(void *opaque)
1020 {
1021 if (kvm_mips_callbacks) {
1022 kvm_err("kvm: module already exists\n");
1023 return -EEXIST;
1024 }
1025
1026 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1027 }
1028
1029 void kvm_arch_exit(void)
1030 {
1031 kvm_mips_callbacks = NULL;
1032 }
1033
1034 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1035 struct kvm_sregs *sregs)
1036 {
1037 return -ENOIOCTLCMD;
1038 }
1039
1040 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1041 struct kvm_sregs *sregs)
1042 {
1043 return -ENOIOCTLCMD;
1044 }
1045
1046 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1047 {
1048 }
1049
1050 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1051 {
1052 return -ENOIOCTLCMD;
1053 }
1054
1055 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1056 {
1057 return -ENOIOCTLCMD;
1058 }
1059
1060 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1061 {
1062 return VM_FAULT_SIGBUS;
1063 }
1064
1065 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1066 {
1067 int r;
1068
1069 switch (ext) {
1070 case KVM_CAP_ONE_REG:
1071 case KVM_CAP_ENABLE_CAP:
1072 r = 1;
1073 break;
1074 case KVM_CAP_COALESCED_MMIO:
1075 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1076 break;
1077 case KVM_CAP_MIPS_FPU:
1078 r = !!cpu_has_fpu;
1079 break;
1080 case KVM_CAP_MIPS_MSA:
1081 /*
1082 * We don't support MSA vector partitioning yet:
1083 * 1) It would require explicit support which can't be tested
1084 * yet due to lack of support in current hardware.
1085 * 2) It extends the state that would need to be saved/restored
1086 * by e.g. QEMU for migration.
1087 *
1088 * When vector partitioning hardware becomes available, support
1089 * could be added by requiring a flag when enabling
1090 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1091 * to save/restore the appropriate extra state.
1092 */
1093 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1094 break;
1095 default:
1096 r = 0;
1097 break;
1098 }
1099 return r;
1100 }
1101
1102 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1103 {
1104 return kvm_mips_pending_timer(vcpu);
1105 }
1106
1107 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1108 {
1109 int i;
1110 struct mips_coproc *cop0;
1111
1112 if (!vcpu)
1113 return -1;
1114
1115 kvm_debug("VCPU Register Dump:\n");
1116 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1117 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1118
1119 for (i = 0; i < 32; i += 4) {
1120 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1121 vcpu->arch.gprs[i],
1122 vcpu->arch.gprs[i + 1],
1123 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1124 }
1125 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1126 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1127
1128 cop0 = vcpu->arch.cop0;
1129 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1130 kvm_read_c0_guest_status(cop0),
1131 kvm_read_c0_guest_cause(cop0));
1132
1133 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1134
1135 return 0;
1136 }
1137
1138 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1139 {
1140 int i;
1141
1142 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1143 vcpu->arch.gprs[i] = regs->gpr[i];
1144 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1145 vcpu->arch.hi = regs->hi;
1146 vcpu->arch.lo = regs->lo;
1147 vcpu->arch.pc = regs->pc;
1148
1149 return 0;
1150 }
1151
1152 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1153 {
1154 int i;
1155
1156 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1157 regs->gpr[i] = vcpu->arch.gprs[i];
1158
1159 regs->hi = vcpu->arch.hi;
1160 regs->lo = vcpu->arch.lo;
1161 regs->pc = vcpu->arch.pc;
1162
1163 return 0;
1164 }
1165
1166 static void kvm_mips_comparecount_func(unsigned long data)
1167 {
1168 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1169
1170 kvm_mips_callbacks->queue_timer_int(vcpu);
1171
1172 vcpu->arch.wait = 0;
1173 if (waitqueue_active(&vcpu->wq))
1174 wake_up_interruptible(&vcpu->wq);
1175 }
1176
1177 /* low level hrtimer wake routine */
1178 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1179 {
1180 struct kvm_vcpu *vcpu;
1181
1182 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1183 kvm_mips_comparecount_func((unsigned long) vcpu);
1184 return kvm_mips_count_timeout(vcpu);
1185 }
1186
1187 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1188 {
1189 kvm_mips_callbacks->vcpu_init(vcpu);
1190 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1191 HRTIMER_MODE_REL);
1192 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1193 return 0;
1194 }
1195
1196 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1197 struct kvm_translation *tr)
1198 {
1199 return 0;
1200 }
1201
1202 /* Initial guest state */
1203 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1204 {
1205 return kvm_mips_callbacks->vcpu_setup(vcpu);
1206 }
1207
1208 static void kvm_mips_set_c0_status(void)
1209 {
1210 uint32_t status = read_c0_status();
1211
1212 if (cpu_has_dsp)
1213 status |= (ST0_MX);
1214
1215 write_c0_status(status);
1216 ehb();
1217 }
1218
1219 /*
1220 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1221 */
1222 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1223 {
1224 uint32_t cause = vcpu->arch.host_cp0_cause;
1225 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1226 uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
1227 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1228 enum emulation_result er = EMULATE_DONE;
1229 int ret = RESUME_GUEST;
1230
1231 /* re-enable HTW before enabling interrupts */
1232 htw_start();
1233
1234 /* Set a default exit reason */
1235 run->exit_reason = KVM_EXIT_UNKNOWN;
1236 run->ready_for_interrupt_injection = 1;
1237
1238 /*
1239 * Set the appropriate status bits based on host CPU features,
1240 * before we hit the scheduler
1241 */
1242 kvm_mips_set_c0_status();
1243
1244 local_irq_enable();
1245
1246 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1247 cause, opc, run, vcpu);
1248
1249 /*
1250 * Do a privilege check, if in UM most of these exit conditions end up
1251 * causing an exception to be delivered to the Guest Kernel
1252 */
1253 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1254 if (er == EMULATE_PRIV_FAIL) {
1255 goto skip_emul;
1256 } else if (er == EMULATE_FAIL) {
1257 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1258 ret = RESUME_HOST;
1259 goto skip_emul;
1260 }
1261
1262 switch (exccode) {
1263 case T_INT:
1264 kvm_debug("[%d]T_INT @ %p\n", vcpu->vcpu_id, opc);
1265
1266 ++vcpu->stat.int_exits;
1267 trace_kvm_exit(vcpu, INT_EXITS);
1268
1269 if (need_resched())
1270 cond_resched();
1271
1272 ret = RESUME_GUEST;
1273 break;
1274
1275 case T_COP_UNUSABLE:
1276 kvm_debug("T_COP_UNUSABLE: @ PC: %p\n", opc);
1277
1278 ++vcpu->stat.cop_unusable_exits;
1279 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
1280 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1281 /* XXXKYMA: Might need to return to user space */
1282 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1283 ret = RESUME_HOST;
1284 break;
1285
1286 case T_TLB_MOD:
1287 ++vcpu->stat.tlbmod_exits;
1288 trace_kvm_exit(vcpu, TLBMOD_EXITS);
1289 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1290 break;
1291
1292 case T_TLB_ST_MISS:
1293 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1294 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1295 badvaddr);
1296
1297 ++vcpu->stat.tlbmiss_st_exits;
1298 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
1299 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1300 break;
1301
1302 case T_TLB_LD_MISS:
1303 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1304 cause, opc, badvaddr);
1305
1306 ++vcpu->stat.tlbmiss_ld_exits;
1307 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
1308 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1309 break;
1310
1311 case T_ADDR_ERR_ST:
1312 ++vcpu->stat.addrerr_st_exits;
1313 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
1314 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1315 break;
1316
1317 case T_ADDR_ERR_LD:
1318 ++vcpu->stat.addrerr_ld_exits;
1319 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
1320 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1321 break;
1322
1323 case T_SYSCALL:
1324 ++vcpu->stat.syscall_exits;
1325 trace_kvm_exit(vcpu, SYSCALL_EXITS);
1326 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1327 break;
1328
1329 case T_RES_INST:
1330 ++vcpu->stat.resvd_inst_exits;
1331 trace_kvm_exit(vcpu, RESVD_INST_EXITS);
1332 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1333 break;
1334
1335 case T_BREAK:
1336 ++vcpu->stat.break_inst_exits;
1337 trace_kvm_exit(vcpu, BREAK_INST_EXITS);
1338 ret = kvm_mips_callbacks->handle_break(vcpu);
1339 break;
1340
1341 case T_TRAP:
1342 ++vcpu->stat.trap_inst_exits;
1343 trace_kvm_exit(vcpu, TRAP_INST_EXITS);
1344 ret = kvm_mips_callbacks->handle_trap(vcpu);
1345 break;
1346
1347 case T_MSAFPE:
1348 ++vcpu->stat.msa_fpe_exits;
1349 trace_kvm_exit(vcpu, MSA_FPE_EXITS);
1350 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1351 break;
1352
1353 case T_FPE:
1354 ++vcpu->stat.fpe_exits;
1355 trace_kvm_exit(vcpu, FPE_EXITS);
1356 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1357 break;
1358
1359 case T_MSADIS:
1360 ++vcpu->stat.msa_disabled_exits;
1361 trace_kvm_exit(vcpu, MSA_DISABLED_EXITS);
1362 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1363 break;
1364
1365 default:
1366 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1367 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1368 kvm_read_c0_guest_status(vcpu->arch.cop0));
1369 kvm_arch_vcpu_dump_regs(vcpu);
1370 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1371 ret = RESUME_HOST;
1372 break;
1373
1374 }
1375
1376 skip_emul:
1377 local_irq_disable();
1378
1379 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1380 kvm_mips_deliver_interrupts(vcpu, cause);
1381
1382 if (!(ret & RESUME_HOST)) {
1383 /* Only check for signals if not already exiting to userspace */
1384 if (signal_pending(current)) {
1385 run->exit_reason = KVM_EXIT_INTR;
1386 ret = (-EINTR << 2) | RESUME_HOST;
1387 ++vcpu->stat.signal_exits;
1388 trace_kvm_exit(vcpu, SIGNAL_EXITS);
1389 }
1390 }
1391
1392 if (ret == RESUME_GUEST) {
1393 /*
1394 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1395 * is live), restore FCR31 / MSACSR.
1396 *
1397 * This should be before returning to the guest exception
1398 * vector, as it may well cause an [MSA] FP exception if there
1399 * are pending exception bits unmasked. (see
1400 * kvm_mips_csr_die_notifier() for how that is handled).
1401 */
1402 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1403 read_c0_status() & ST0_CU1)
1404 __kvm_restore_fcsr(&vcpu->arch);
1405
1406 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1407 read_c0_config5() & MIPS_CONF5_MSAEN)
1408 __kvm_restore_msacsr(&vcpu->arch);
1409 }
1410
1411 /* Disable HTW before returning to guest or host */
1412 htw_stop();
1413
1414 return ret;
1415 }
1416
1417 /* Enable FPU for guest and restore context */
1418 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1419 {
1420 struct mips_coproc *cop0 = vcpu->arch.cop0;
1421 unsigned int sr, cfg5;
1422
1423 preempt_disable();
1424
1425 sr = kvm_read_c0_guest_status(cop0);
1426
1427 /*
1428 * If MSA state is already live, it is undefined how it interacts with
1429 * FR=0 FPU state, and we don't want to hit reserved instruction
1430 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1431 * play it safe and save it first.
1432 *
1433 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1434 * get called when guest CU1 is set, however we can't trust the guest
1435 * not to clobber the status register directly via the commpage.
1436 */
1437 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1438 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1439 kvm_lose_fpu(vcpu);
1440
1441 /*
1442 * Enable FPU for guest
1443 * We set FR and FRE according to guest context
1444 */
1445 change_c0_status(ST0_CU1 | ST0_FR, sr);
1446 if (cpu_has_fre) {
1447 cfg5 = kvm_read_c0_guest_config5(cop0);
1448 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1449 }
1450 enable_fpu_hazard();
1451
1452 /* If guest FPU state not active, restore it now */
1453 if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) {
1454 __kvm_restore_fpu(&vcpu->arch);
1455 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1456 }
1457
1458 preempt_enable();
1459 }
1460
1461 #ifdef CONFIG_CPU_HAS_MSA
1462 /* Enable MSA for guest and restore context */
1463 void kvm_own_msa(struct kvm_vcpu *vcpu)
1464 {
1465 struct mips_coproc *cop0 = vcpu->arch.cop0;
1466 unsigned int sr, cfg5;
1467
1468 preempt_disable();
1469
1470 /*
1471 * Enable FPU if enabled in guest, since we're restoring FPU context
1472 * anyway. We set FR and FRE according to guest context.
1473 */
1474 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1475 sr = kvm_read_c0_guest_status(cop0);
1476
1477 /*
1478 * If FR=0 FPU state is already live, it is undefined how it
1479 * interacts with MSA state, so play it safe and save it first.
1480 */
1481 if (!(sr & ST0_FR) &&
1482 (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU |
1483 KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU)
1484 kvm_lose_fpu(vcpu);
1485
1486 change_c0_status(ST0_CU1 | ST0_FR, sr);
1487 if (sr & ST0_CU1 && cpu_has_fre) {
1488 cfg5 = kvm_read_c0_guest_config5(cop0);
1489 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1490 }
1491 }
1492
1493 /* Enable MSA for guest */
1494 set_c0_config5(MIPS_CONF5_MSAEN);
1495 enable_fpu_hazard();
1496
1497 switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) {
1498 case KVM_MIPS_FPU_FPU:
1499 /*
1500 * Guest FPU state already loaded, only restore upper MSA state
1501 */
1502 __kvm_restore_msa_upper(&vcpu->arch);
1503 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1504 break;
1505 case 0:
1506 /* Neither FPU or MSA already active, restore full MSA state */
1507 __kvm_restore_msa(&vcpu->arch);
1508 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1509 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1510 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1511 break;
1512 default:
1513 break;
1514 }
1515
1516 preempt_enable();
1517 }
1518 #endif
1519
1520 /* Drop FPU & MSA without saving it */
1521 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1522 {
1523 preempt_disable();
1524 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1525 disable_msa();
1526 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA;
1527 }
1528 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1529 clear_c0_status(ST0_CU1 | ST0_FR);
1530 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1531 }
1532 preempt_enable();
1533 }
1534
1535 /* Save and disable FPU & MSA */
1536 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1537 {
1538 /*
1539 * FPU & MSA get disabled in root context (hardware) when it is disabled
1540 * in guest context (software), but the register state in the hardware
1541 * may still be in use. This is why we explicitly re-enable the hardware
1542 * before saving.
1543 */
1544
1545 preempt_disable();
1546 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1547 set_c0_config5(MIPS_CONF5_MSAEN);
1548 enable_fpu_hazard();
1549
1550 __kvm_save_msa(&vcpu->arch);
1551
1552 /* Disable MSA & FPU */
1553 disable_msa();
1554 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1555 clear_c0_status(ST0_CU1 | ST0_FR);
1556 vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA);
1557 } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1558 set_c0_status(ST0_CU1);
1559 enable_fpu_hazard();
1560
1561 __kvm_save_fpu(&vcpu->arch);
1562 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1563
1564 /* Disable FPU */
1565 clear_c0_status(ST0_CU1 | ST0_FR);
1566 }
1567 preempt_enable();
1568 }
1569
1570 /*
1571 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1572 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1573 * exception if cause bits are set in the value being written.
1574 */
1575 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1576 unsigned long cmd, void *ptr)
1577 {
1578 struct die_args *args = (struct die_args *)ptr;
1579 struct pt_regs *regs = args->regs;
1580 unsigned long pc;
1581
1582 /* Only interested in FPE and MSAFPE */
1583 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1584 return NOTIFY_DONE;
1585
1586 /* Return immediately if guest context isn't active */
1587 if (!(current->flags & PF_VCPU))
1588 return NOTIFY_DONE;
1589
1590 /* Should never get here from user mode */
1591 BUG_ON(user_mode(regs));
1592
1593 pc = instruction_pointer(regs);
1594 switch (cmd) {
1595 case DIE_FP:
1596 /* match 2nd instruction in __kvm_restore_fcsr */
1597 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1598 return NOTIFY_DONE;
1599 break;
1600 case DIE_MSAFP:
1601 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1602 if (!cpu_has_msa ||
1603 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1604 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1605 return NOTIFY_DONE;
1606 break;
1607 }
1608
1609 /* Move PC forward a little and continue executing */
1610 instruction_pointer(regs) += 4;
1611
1612 return NOTIFY_STOP;
1613 }
1614
1615 static struct notifier_block kvm_mips_csr_die_notifier = {
1616 .notifier_call = kvm_mips_csr_die_notify,
1617 };
1618
1619 int __init kvm_mips_init(void)
1620 {
1621 int ret;
1622
1623 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1624
1625 if (ret)
1626 return ret;
1627
1628 register_die_notifier(&kvm_mips_csr_die_notifier);
1629
1630 /*
1631 * On MIPS, kernel modules are executed from "mapped space", which
1632 * requires TLBs. The TLB handling code is statically linked with
1633 * the rest of the kernel (tlb.c) to avoid the possibility of
1634 * double faulting. The issue is that the TLB code references
1635 * routines that are part of the the KVM module, which are only
1636 * available once the module is loaded.
1637 */
1638 kvm_mips_gfn_to_pfn = gfn_to_pfn;
1639 kvm_mips_release_pfn_clean = kvm_release_pfn_clean;
1640 kvm_mips_is_error_pfn = is_error_pfn;
1641
1642 return 0;
1643 }
1644
1645 void __exit kvm_mips_exit(void)
1646 {
1647 kvm_exit();
1648
1649 kvm_mips_gfn_to_pfn = NULL;
1650 kvm_mips_release_pfn_clean = NULL;
1651 kvm_mips_is_error_pfn = NULL;
1652
1653 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1654 }
1655
1656 module_init(kvm_mips_init);
1657 module_exit(kvm_mips_exit);
1658
1659 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux with added FPC-III support