arch/mips/math-emu/ieee754sp.c

   1 /* IEEE754 floating point arithmetic
   2  * single precision
   3  */
   4 /*
   5  * MIPS floating point support
   6  * Copyright (C) 1994-2000 Algorithmics Ltd.
   7  *
   8  *  This program is free software; you can distribute it and/or modify it
   9  *  under the terms of the GNU General Public License (Version 2) as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, write to the Free Software Foundation, Inc.,
  19  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  20  */
  21
  22 #include <linux/compiler.h>
  23
  24 #include "ieee754sp.h"
  25
  26 int ieee754sp_class(union ieee754sp x)
  27 {
  28         COMPXSP;
  29         EXPLODEXSP;
  30         return xc;
  31 }
  32
  33 static inline int ieee754sp_isnan(union ieee754sp x)
  34 {
  35         return ieee754_class_nan(ieee754sp_class(x));
  36 }
  37
  38 static inline int ieee754sp_issnan(union ieee754sp x)
  39 {
  40         assert(ieee754sp_isnan(x));
  41         return SPMANT(x) & SP_MBIT(SP_FBITS - 1);
  42 }
  43
  44
  45 /*
  46  * Raise the Invalid Operation IEEE 754 exception
  47  * and convert the signaling NaN supplied to a quiet NaN.
  48  */
  49 union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r)
  50 {
  51         assert(ieee754sp_issnan(r));
  52
  53         ieee754_setcx(IEEE754_INVALID_OPERATION);
  54         return ieee754sp_indef();
  55 }
  56
  57 static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
  58 {
  59         /* inexact must round of 3 bits
  60          */
  61         if (xm & (SP_MBIT(3) - 1)) {
  62                 switch (ieee754_csr.rm) {
  63                 case FPU_CSR_RZ:
  64                         break;
  65                 case FPU_CSR_RN:
  66                         xm += 0x3 + ((xm >> 3) & 1);
  67                         /* xm += (xm&0x8)?0x4:0x3 */
  68                         break;
  69                 case FPU_CSR_RU:        /* toward +Infinity */
  70                         if (!sn)        /* ?? */
  71                                 xm += 0x8;
  72                         break;
  73                 case FPU_CSR_RD:        /* toward -Infinity */
  74                         if (sn) /* ?? */
  75                                 xm += 0x8;
  76                         break;
  77                 }
  78         }
  79         return xm;
  80 }
  81
  82
  83 /* generate a normal/denormal number with over,under handling
  84  * sn is sign
  85  * xe is an unbiased exponent
  86  * xm is 3bit extended precision value.
  87  */
  88 union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
  89 {
  90         assert(xm);             /* we don't gen exact zeros (probably should) */
  91
  92         assert((xm >> (SP_FBITS + 1 + 3)) == 0);        /* no execess */
  93         assert(xm & (SP_HIDDEN_BIT << 3));
  94
  95         if (xe < SP_EMIN) {
  96                 /* strip lower bits */
  97                 int es = SP_EMIN - xe;
  98
  99                 if (ieee754_csr.nod) {
 100                         ieee754_setcx(IEEE754_UNDERFLOW);
 101                         ieee754_setcx(IEEE754_INEXACT);
 102
 103                         switch(ieee754_csr.rm) {
 104                         case FPU_CSR_RN:
 105                         case FPU_CSR_RZ:
 106                                 return ieee754sp_zero(sn);
 107                         case FPU_CSR_RU:      /* toward +Infinity */
 108                                 if (sn == 0)
 109                                         return ieee754sp_min(0);
 110                                 else
 111                                         return ieee754sp_zero(1);
 112                         case FPU_CSR_RD:      /* toward -Infinity */
 113                                 if (sn == 0)
 114                                         return ieee754sp_zero(0);
 115                                 else
 116                                         return ieee754sp_min(1);
 117                         }
 118                 }
 119
 120                 if (xe == SP_EMIN - 1 &&
 121                     ieee754sp_get_rounding(sn, xm) >> (SP_FBITS + 1 + 3))
 122                 {
 123                         /* Not tiny after rounding */
 124                         ieee754_setcx(IEEE754_INEXACT);
 125                         xm = ieee754sp_get_rounding(sn, xm);
 126                         xm >>= 1;
 127                         /* Clear grs bits */
 128                         xm &= ~(SP_MBIT(3) - 1);
 129                         xe++;
 130                 } else {
 131                         /* sticky right shift es bits
 132                          */
 133                         SPXSRSXn(es);
 134                         assert((xm & (SP_HIDDEN_BIT << 3)) == 0);
 135                         assert(xe == SP_EMIN);
 136                 }
 137         }
 138         if (xm & (SP_MBIT(3) - 1)) {
 139                 ieee754_setcx(IEEE754_INEXACT);
 140                 if ((xm & (SP_HIDDEN_BIT << 3)) == 0) {
 141                         ieee754_setcx(IEEE754_UNDERFLOW);
 142                 }
 143
 144                 /* inexact must round of 3 bits
 145                  */
 146                 xm = ieee754sp_get_rounding(sn, xm);
 147                 /* adjust exponent for rounding add overflowing
 148                  */
 149                 if (xm >> (SP_FBITS + 1 + 3)) {
 150                         /* add causes mantissa overflow */
 151                         xm >>= 1;
 152                         xe++;
 153                 }
 154         }
 155         /* strip grs bits */
 156         xm >>= 3;
 157
 158         assert((xm >> (SP_FBITS + 1)) == 0);    /* no execess */
 159         assert(xe >= SP_EMIN);
 160
 161         if (xe > SP_EMAX) {
 162                 ieee754_setcx(IEEE754_OVERFLOW);
 163                 ieee754_setcx(IEEE754_INEXACT);
 164                 /* -O can be table indexed by (rm,sn) */
 165                 switch (ieee754_csr.rm) {
 166                 case FPU_CSR_RN:
 167                         return ieee754sp_inf(sn);
 168                 case FPU_CSR_RZ:
 169                         return ieee754sp_max(sn);
 170                 case FPU_CSR_RU:        /* toward +Infinity */
 171                         if (sn == 0)
 172                                 return ieee754sp_inf(0);
 173                         else
 174                                 return ieee754sp_max(1);
 175                 case FPU_CSR_RD:        /* toward -Infinity */
 176                         if (sn == 0)
 177                                 return ieee754sp_max(0);
 178                         else
 179                                 return ieee754sp_inf(1);
 180                 }
 181         }
 182         /* gen norm/denorm/zero */
 183
 184         if ((xm & SP_HIDDEN_BIT) == 0) {
 185                 /* we underflow (tiny/zero) */
 186                 assert(xe == SP_EMIN);
 187                 if (ieee754_csr.mx & IEEE754_UNDERFLOW)
 188                         ieee754_setcx(IEEE754_UNDERFLOW);
 189                 return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm);
 190         } else {
 191                 assert((xm >> (SP_FBITS + 1)) == 0);    /* no execess */
 192                 assert(xm & SP_HIDDEN_BIT);
 193
 194                 return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT);
 195         }
 196 }