arch/mips/mm/uasm-mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * A small micro-assembler. It is intentionally kept simple, does only
   7  * support a subset of instructions, and does not try to hide pipeline
   8  * effects like branch delay slots.
   9  *
  10  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  11  * Copyright (C) 2005, 2007  Maciej W. Rozycki
  12  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  13  * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18
  19 #include <asm/inst.h>
  20 #include <asm/elf.h>
  21 #include <asm/bugs.h>
  22 #define UASM_ISA        _UASM_ISA_CLASSIC
  23 #include <asm/uasm.h>
  24
  25 #define RS_MASK         0x1f
  26 #define RS_SH           21
  27 #define RT_MASK         0x1f
  28 #define RT_SH           16
  29 #define SCIMM_MASK      0xfffff
  30 #define SCIMM_SH        6
  31
  32 /* This macro sets the non-variable bits of an instruction. */
  33 #define M(a, b, c, d, e, f)                                     \
  34         ((a) << OP_SH                                           \
  35          | (b) << RS_SH                                         \
  36          | (c) << RT_SH                                         \
  37          | (d) << RD_SH                                         \
  38          | (e) << RE_SH                                         \
  39          | (f) << FUNC_SH)
  40
  41 /* This macro sets the non-variable bits of an R6 instruction. */
  42 #define M6(a, b, c, d, e)                                       \
  43         ((a) << OP_SH                                           \
  44          | (b) << RS_SH                                         \
  45          | (c) << RT_SH                                         \
  46          | (d) << SIMM9_SH                                      \
  47          | (e) << FUNC_SH)
  48
  49 #include "uasm.c"
  50
  51 static struct insn insn_table[] = {
  52         { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
  53         { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
  54         { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
  55         { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
  56         { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  57         { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  58         { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  59         { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  60         { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
  61         { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
  62         { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
  63         { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
  64         { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  65 #ifndef CONFIG_CPU_MIPSR6
  66         { insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
  67 #else
  68         { insn_cache,  M6(cache_op, 0, 0, 0, cache6_op),  RS | RT | SIMM9 },
  69 #endif
  70         { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
  71         { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
  72         { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
  73         { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
  74         { insn_divu, M(spec_op, 0, 0, 0, 0, divu_op), RS | RT },
  75         { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
  76         { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
  77         { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
  78         { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
  79         { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
  80         { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
  81         { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
  82         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
  83         { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
  84         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
  85         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
  86         { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
  87         { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
  88         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
  89         { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
  90         { insn_jalr,  M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD },
  91         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
  92 #ifndef CONFIG_CPU_MIPSR6
  93         { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
  94 #else
  95         { insn_jr,  M(spec_op, 0, 0, 0, 0, jalr_op),  RS },
  96 #endif
  97         { insn_lb, M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
  98         { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
  99         { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
 100         { insn_lh,  M(lh_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 101 #ifndef CONFIG_CPU_MIPSR6
 102         { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 103         { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 104 #else
 105         { insn_lld,  M6(spec3_op, 0, 0, 0, lld6_op),  RS | RT | SIMM9 },
 106         { insn_ll,  M6(spec3_op, 0, 0, 0, ll6_op),  RS | RT | SIMM9 },
 107 #endif
 108         { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
 109         { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 110         { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
 111         { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
 112         { insn_mfhc0,  M(cop0_op, mfhc0_op, 0, 0, 0, 0),  RT | RD | SET},
 113         { insn_mfhi,  M(spec_op, 0, 0, 0, 0, mfhi_op), RD },
 114         { insn_mflo,  M(spec_op, 0, 0, 0, 0, mflo_op), RD },
 115         { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
 116         { insn_mthc0,  M(cop0_op, mthc0_op, 0, 0, 0, 0),  RT | RD | SET},
 117         { insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
 118         { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
 119         { insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },
 120 #ifndef CONFIG_CPU_MIPSR6
 121         { insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 122 #else
 123         { insn_pref,  M6(spec3_op, 0, 0, 0, pref6_op),  RS | RT | SIMM9 },
 124 #endif
 125         { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
 126         { insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
 127 #ifndef CONFIG_CPU_MIPSR6
 128         { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 129         { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 130 #else
 131         { insn_scd,  M6(spec3_op, 0, 0, 0, scd6_op),  RS | RT | SIMM9 },
 132         { insn_sc,  M6(spec3_op, 0, 0, 0, sc6_op),  RS | RT | SIMM9 },
 133 #endif
 134         { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 135         { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
 136         { insn_sllv,  M(spec_op, 0, 0, 0, 0, sllv_op),  RS | RT | RD },
 137         { insn_slt,  M(spec_op, 0, 0, 0, 0, slt_op),  RS | RT | RD },
 138         { insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
 139         { insn_sltu, M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD },
 140         { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
 141         { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
 142         { insn_srlv,  M(spec_op, 0, 0, 0, 0, srlv_op),  RS | RT | RD },
 143         { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
 144         { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 145         { insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE },
 146         { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
 147         { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
 148         { insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },
 149         { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
 150         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
 151         { insn_wait, M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM },
 152         { insn_wsbh, M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD },
 153         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
 154         { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
 155         { insn_yield, M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD },
 156         { insn_invalid, 0, 0 }
 157 };
 158
 159 #undef M
 160
 161 static inline u32 build_bimm(s32 arg)
 162 {
 163         WARN(arg > 0x1ffff || arg < -0x20000,
 164              KERN_WARNING "Micro-assembler field overflow\n");
 165
 166         WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
 167
 168         return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
 169 }
 170
 171 static inline u32 build_jimm(u32 arg)
 172 {
 173         WARN(arg & ~(JIMM_MASK << 2),
 174              KERN_WARNING "Micro-assembler field overflow\n");
 175
 176         return (arg >> 2) & JIMM_MASK;
 177 }
 178
 179 /*
 180  * The order of opcode arguments is implicitly left to right,
 181  * starting with RS and ending with FUNC or IMM.
 182  */
 183 static void build_insn(u32 **buf, enum opcode opc, ...)
 184 {
 185         struct insn *ip = NULL;
 186         unsigned int i;
 187         va_list ap;
 188         u32 op;
 189
 190         for (i = 0; insn_table[i].opcode != insn_invalid; i++)
 191                 if (insn_table[i].opcode == opc) {
 192                         ip = &insn_table[i];
 193                         break;
 194                 }
 195
 196         if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
 197                 panic("Unsupported Micro-assembler instruction %d", opc);
 198
 199         op = ip->match;
 200         va_start(ap, opc);
 201         if (ip->fields & RS)
 202                 op |= build_rs(va_arg(ap, u32));
 203         if (ip->fields & RT)
 204                 op |= build_rt(va_arg(ap, u32));
 205         if (ip->fields & RD)
 206                 op |= build_rd(va_arg(ap, u32));
 207         if (ip->fields & RE)
 208                 op |= build_re(va_arg(ap, u32));
 209         if (ip->fields & SIMM)
 210                 op |= build_simm(va_arg(ap, s32));
 211         if (ip->fields & UIMM)
 212                 op |= build_uimm(va_arg(ap, u32));
 213         if (ip->fields & BIMM)
 214                 op |= build_bimm(va_arg(ap, s32));
 215         if (ip->fields & JIMM)
 216                 op |= build_jimm(va_arg(ap, u32));
 217         if (ip->fields & FUNC)
 218                 op |= build_func(va_arg(ap, u32));
 219         if (ip->fields & SET)
 220                 op |= build_set(va_arg(ap, u32));
 221         if (ip->fields & SCIMM)
 222                 op |= build_scimm(va_arg(ap, u32));
 223         if (ip->fields & SIMM9)
 224                 op |= build_scimm9(va_arg(ap, u32));
 225         va_end(ap);
 226
 227         **buf = op;
 228         (*buf)++;
 229 }
 230
 231 static inline void
 232 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 233 {
 234         long laddr = (long)lab->addr;
 235         long raddr = (long)rel->addr;
 236
 237         switch (rel->type) {
 238         case R_MIPS_PC16:
 239                 *rel->addr |= build_bimm(laddr - (raddr + 4));
 240                 break;
 241
 242         default:
 243                 panic("Unsupported Micro-assembler relocation %d",
 244                       rel->type);
 245         }
 246 }