arch/mips/ralink/rt288x.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify it
   3  * under the terms of the GNU General Public License version 2 as published
   4  * by the Free Software Foundation.
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   9  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10  * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16
  17 #include <asm/mipsregs.h>
  18 #include <asm/mach-ralink/ralink_regs.h>
  19 #include <asm/mach-ralink/rt288x.h>
  20 #include <asm/mach-ralink/pinmux.h>
  21
  22 #include "common.h"
  23
  24 static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
  25 static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
  26 static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
  27 static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
  28 static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
  29 static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
  30 static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
  31
  32 static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
  33         GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
  34         GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
  35         GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
  36         GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
  37         GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
  38         GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
  39         GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
  40         { 0 }
  41 };
  42
  43 static void rt288x_wdt_reset(void)
  44 {
  45         u32 t;
  46
  47         /* enable WDT reset output on pin SRAM_CS_N */
  48         t = rt_sysc_r32(SYSC_REG_CLKCFG);
  49         t |= CLKCFG_SRAM_CS_N_WDT;
  50         rt_sysc_w32(t, SYSC_REG_CLKCFG);
  51 }
  52
  53 void __init ralink_clk_init(void)
  54 {
  55         unsigned long cpu_rate, wmac_rate = 40000000;
  56         u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  57         t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
  58
  59         switch (t) {
  60         case SYSTEM_CONFIG_CPUCLK_250:
  61                 cpu_rate = 250000000;
  62                 break;
  63         case SYSTEM_CONFIG_CPUCLK_266:
  64                 cpu_rate = 266666667;
  65                 break;
  66         case SYSTEM_CONFIG_CPUCLK_280:
  67                 cpu_rate = 280000000;
  68                 break;
  69         case SYSTEM_CONFIG_CPUCLK_300:
  70                 cpu_rate = 300000000;
  71                 break;
  72         }
  73
  74         ralink_clk_add("cpu", cpu_rate);
  75         ralink_clk_add("300100.timer", cpu_rate / 2);
  76         ralink_clk_add("300120.watchdog", cpu_rate / 2);
  77         ralink_clk_add("300500.uart", cpu_rate / 2);
  78         ralink_clk_add("300c00.uartlite", cpu_rate / 2);
  79         ralink_clk_add("400000.ethernet", cpu_rate / 2);
  80         ralink_clk_add("480000.wmac", wmac_rate);
  81 }
  82
  83 void __init ralink_of_remap(void)
  84 {
  85         rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
  86         rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
  87
  88         if (!rt_sysc_membase || !rt_memc_membase)
  89                 panic("Failed to remap core resources");
  90 }
  91
  92 void prom_soc_init(struct ralink_soc_info *soc_info)
  93 {
  94         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
  95         const char *name;
  96         u32 n0;
  97         u32 n1;
  98         u32 id;
  99
 100         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 101         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 102         id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
 103
 104         if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
 105                 soc_info->compatible = "ralink,r2880-soc";
 106                 name = "RT2880";
 107         } else {
 108                 panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
 109         }
 110
 111         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 112                 "Ralink %s id:%u rev:%u",
 113                 name,
 114                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 115                 (id & CHIP_ID_REV_MASK));
 116
 117         soc_info->mem_base = RT2880_SDRAM_BASE;
 118         soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
 119         soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
 120
 121         rt2880_pinmux_data = rt2880_pinmux_data_act;
 122 }