2 * MPC8323E EMDS Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
14 * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
15 * 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
16 * next to the serial ports.
17 * 3) Solder a wire from U61-22 to P19K-22.
19 * Note that there's a typo in the schematic. The board labels the last column
20 * of pins "P19K", but in the schematic, that column is called "P19J". So if
21 * you're going by the schematic, the pin is called "P19J-K22".
27 model = "MPC8323EMDS";
28 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
47 d-cache-line-size = <32>; // 32 bytes
48 i-cache-line-size = <32>; // 32 bytes
49 d-cache-size = <16384>; // L1, 16K
50 i-cache-size = <16384>; // L1, 16K
51 timebase-frequency = <0>;
53 clock-frequency = <0>;
58 device_type = "memory";
59 reg = <0x00000000 0x08000000>;
63 compatible = "fsl,mpc8323mds-bcsr";
64 reg = <0xf8000000 0x8000>;
71 compatible = "simple-bus";
72 ranges = <0x0 0xe0000000 0x00100000>;
73 reg = <0xe0000000 0x00000200>;
74 bus-frequency = <132000000>;
77 device_type = "watchdog";
78 compatible = "mpc83xx_wdt";
83 compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
84 reg = <0xb00 0x100 0xa00 0x100>;
85 interrupts = <80 0x8>;
86 interrupt-parent = <&ipic>;
93 compatible = "fsl-i2c";
95 interrupts = <14 0x8>;
96 interrupt-parent = <&ipic>;
100 compatible = "dallas,ds1374";
105 serial0: serial@4500 {
107 device_type = "serial";
108 compatible = "fsl,ns16550", "ns16550";
109 reg = <0x4500 0x100>;
110 clock-frequency = <0>;
111 interrupts = <9 0x8>;
112 interrupt-parent = <&ipic>;
115 serial1: serial@4600 {
117 device_type = "serial";
118 compatible = "fsl,ns16550", "ns16550";
119 reg = <0x4600 0x100>;
120 clock-frequency = <0>;
121 interrupts = <10 0x8>;
122 interrupt-parent = <&ipic>;
126 #address-cells = <1>;
128 compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
130 ranges = <0 0x8100 0x1a8>;
131 interrupt-parent = <&ipic>;
135 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
138 interrupt-parent = <&ipic>;
142 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
145 interrupt-parent = <&ipic>;
149 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
152 interrupt-parent = <&ipic>;
156 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
159 interrupt-parent = <&ipic>;
165 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
166 reg = <0x30000 0x10000>;
167 interrupts = <11 0x8>;
168 interrupt-parent = <&ipic>;
169 fsl,num-channels = <1>;
170 fsl,channel-fifo-len = <24>;
171 fsl,exec-units-mask = <0x4c>;
172 fsl,descriptor-types-mask = <0x0122003f>;
173 sleep = <&pmc 0x03000000>;
177 interrupt-controller;
178 #address-cells = <0>;
179 #interrupt-cells = <2>;
181 device_type = "ipic";
185 reg = <0x1400 0x100>;
186 device_type = "par_io";
191 /* port pin dir open_drain assignment has_irq */
192 3 4 3 0 2 0 /* MDIO */
193 3 5 1 0 2 0 /* MDC */
194 0 13 2 0 1 0 /* RX_CLK (CLK9) */
195 3 24 2 0 1 0 /* TX_CLK (CLK10) */
196 1 0 1 0 1 0 /* TxD0 */
197 1 1 1 0 1 0 /* TxD1 */
198 1 2 1 0 1 0 /* TxD2 */
199 1 3 1 0 1 0 /* TxD3 */
200 1 4 2 0 1 0 /* RxD0 */
201 1 5 2 0 1 0 /* RxD1 */
202 1 6 2 0 1 0 /* RxD2 */
203 1 7 2 0 1 0 /* RxD3 */
204 1 8 2 0 1 0 /* RX_ER */
205 1 9 1 0 1 0 /* TX_ER */
206 1 10 2 0 1 0 /* RX_DV */
207 1 11 2 0 1 0 /* COL */
208 1 12 1 0 1 0 /* TX_EN */
209 1 13 2 0 1 0>; /* CRS */
213 /* port pin dir open_drain assignment has_irq */
214 3 31 2 0 1 0 /* RX_CLK (CLK7) */
215 3 6 2 0 1 0 /* TX_CLK (CLK8) */
216 1 18 1 0 1 0 /* TxD0 */
217 1 19 1 0 1 0 /* TxD1 */
218 1 20 1 0 1 0 /* TxD2 */
219 1 21 1 0 1 0 /* TxD3 */
220 1 22 2 0 1 0 /* RxD0 */
221 1 23 2 0 1 0 /* RxD1 */
222 1 24 2 0 1 0 /* RxD2 */
223 1 25 2 0 1 0 /* RxD3 */
224 1 26 2 0 1 0 /* RX_ER */
225 1 27 1 0 1 0 /* TX_ER */
226 1 28 2 0 1 0 /* RX_DV */
227 1 29 2 0 1 0 /* COL */
228 1 30 1 0 1 0 /* TX_EN */
229 1 31 2 0 1 0>; /* CRS */
235 * port pin dir drain sel irq
237 2 0 1 0 2 0 /* TxD5 */
238 2 8 2 0 2 0 /* RxD5 */
240 2 29 2 0 0 0 /* CTS5 */
241 2 31 1 0 2 0 /* RTS5 */
243 2 24 2 0 0 0 /* CD */
252 #address-cells = <1>;
255 compatible = "fsl,qe";
256 ranges = <0x0 0xe0100000 0x00100000>;
257 reg = <0xe0100000 0x480>;
259 bus-frequency = <198000000>;
260 fsl,qe-num-riscs = <1>;
261 fsl,qe-num-snums = <28>;
264 #address-cells = <1>;
266 compatible = "fsl,qe-muram", "fsl,cpm-muram";
267 ranges = <0x0 0x00010000 0x00004000>;
270 compatible = "fsl,qe-muram-data",
271 "fsl,cpm-muram-data";
278 compatible = "fsl,spi";
281 interrupt-parent = <&qeic>;
287 compatible = "fsl,spi";
290 interrupt-parent = <&qeic>;
295 compatible = "qe_udc";
296 reg = <0x6c0 0x40 0x8b00 0x100>;
298 interrupt-parent = <&qeic>;
303 device_type = "network";
304 compatible = "ucc_geth";
306 reg = <0x2200 0x200>;
308 interrupt-parent = <&qeic>;
309 local-mac-address = [ 00 00 00 00 00 00 ];
310 rx-clock-name = "clk9";
311 tx-clock-name = "clk10";
312 phy-handle = <&phy3>;
313 pio-handle = <&pio3>;
317 device_type = "network";
318 compatible = "ucc_geth";
320 reg = <0x3200 0x200>;
322 interrupt-parent = <&qeic>;
323 local-mac-address = [ 00 00 00 00 00 00 ];
324 rx-clock-name = "clk7";
325 tx-clock-name = "clk8";
326 phy-handle = <&phy4>;
327 pio-handle = <&pio4>;
331 device_type = "serial";
332 compatible = "ucc_uart";
333 cell-index = <5>; /* The UCC number, 1-7*/
334 port-number = <0>; /* Which ttyQEx device */
335 soft-uart; /* We need Soft-UART */
336 reg = <0x2400 0x200>;
337 interrupts = <40>; /* From Table 18-12 */
338 interrupt-parent = < &qeic >;
340 * For Soft-UART, we need to set TX to 1X, which
341 * means specifying separate clock sources.
343 rx-clock-name = "brg5";
344 tx-clock-name = "brg6";
345 pio-handle = < &pio5 >;
350 #address-cells = <1>;
353 compatible = "fsl,ucc-mdio";
355 phy3: ethernet-phy@03 {
356 interrupt-parent = <&ipic>;
357 interrupts = <17 0x8>;
360 phy4: ethernet-phy@04 {
361 interrupt-parent = <&ipic>;
362 interrupts = <18 0x8>;
367 qeic: interrupt-controller@80 {
368 interrupt-controller;
369 compatible = "fsl,qe-ic";
370 #address-cells = <0>;
371 #interrupt-cells = <1>;
374 interrupts = <32 0x8 33 0x8>; //high:32 low:33
375 interrupt-parent = <&ipic>;
380 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
382 /* IDSEL 0x11 AD17 */
383 0x8800 0x0 0x0 0x1 &ipic 20 0x8
384 0x8800 0x0 0x0 0x2 &ipic 21 0x8
385 0x8800 0x0 0x0 0x3 &ipic 22 0x8
386 0x8800 0x0 0x0 0x4 &ipic 23 0x8
388 /* IDSEL 0x12 AD18 */
389 0x9000 0x0 0x0 0x1 &ipic 22 0x8
390 0x9000 0x0 0x0 0x2 &ipic 23 0x8
391 0x9000 0x0 0x0 0x3 &ipic 20 0x8
392 0x9000 0x0 0x0 0x4 &ipic 21 0x8
394 /* IDSEL 0x13 AD19 */
395 0x9800 0x0 0x0 0x1 &ipic 23 0x8
396 0x9800 0x0 0x0 0x2 &ipic 20 0x8
397 0x9800 0x0 0x0 0x3 &ipic 21 0x8
398 0x9800 0x0 0x0 0x4 &ipic 22 0x8
401 0xa800 0x0 0x0 0x1 &ipic 20 0x8
402 0xa800 0x0 0x0 0x2 &ipic 21 0x8
403 0xa800 0x0 0x0 0x3 &ipic 22 0x8
404 0xa800 0x0 0x0 0x4 &ipic 23 0x8
407 0xb000 0x0 0x0 0x1 &ipic 23 0x8
408 0xb000 0x0 0x0 0x2 &ipic 20 0x8
409 0xb000 0x0 0x0 0x3 &ipic 21 0x8
410 0xb000 0x0 0x0 0x4 &ipic 22 0x8
413 0xb800 0x0 0x0 0x1 &ipic 22 0x8
414 0xb800 0x0 0x0 0x2 &ipic 23 0x8
415 0xb800 0x0 0x0 0x3 &ipic 20 0x8
416 0xb800 0x0 0x0 0x4 &ipic 21 0x8
419 0xc000 0x0 0x0 0x1 &ipic 21 0x8
420 0xc000 0x0 0x0 0x2 &ipic 22 0x8
421 0xc000 0x0 0x0 0x3 &ipic 23 0x8
422 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
423 interrupt-parent = <&ipic>;
424 interrupts = <66 0x8>;
425 bus-range = <0x0 0x0>;
426 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
427 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
428 0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
429 clock-frequency = <0>;
430 #interrupt-cells = <1>;
432 #address-cells = <3>;
433 reg = <0xe0008500 0x100 /* internal registers */
434 0xe0008300 0x8>; /* config space access registers */
435 compatible = "fsl,mpc8349-pci";
437 sleep = <&pmc 0x00010000>;