| blob | 1c03060dd0b8559d09c2c7b7d9caad6bd7d70f7f |
1 /*
2 * MPC8641 HPCN Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 };
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
35 PowerPC,8641@0 {
36 device_type = "cpu";
37 reg = <0>;
38 d-cache-line-size = <32>;
39 i-cache-line-size = <32>;
40 d-cache-size = <32768>; // L1
41 i-cache-size = <32768>; // L1
42 timebase-frequency = <0>; // From uboot
43 bus-frequency = <0>; // From uboot
44 clock-frequency = <0>; // From uboot
45 };
46 PowerPC,8641@1 {
47 device_type = "cpu";
48 reg = <1>;
49 d-cache-line-size = <32>;
50 i-cache-line-size = <32>;
51 d-cache-size = <32768>;
52 i-cache-size = <32768>;
53 timebase-frequency = <0>; // From uboot
54 bus-frequency = <0>; // From uboot
55 clock-frequency = <0>; // From uboot
56 };
57 };
59 memory {
60 device_type = "memory";
61 reg = <0x00000000 0x40000000>; // 1G at 0x0
62 };
64 localbus@ffe05000 {
65 #address-cells = <2>;
66 #size-cells = <1>;
67 compatible = "fsl,mpc8641-localbus", "simple-bus";
68 reg = <0xffe05000 0x1000>;
69 interrupts = <19 2>;
70 interrupt-parent = <&mpic>;
72 ranges = <0 0 0xef800000 0x00800000
73 2 0 0xffdf8000 0x00008000
74 3 0 0xffdf0000 0x00008000>;
76 flash@0,0 {
77 compatible = "cfi-flash";
78 reg = <0 0 0x00800000>;
79 bank-width = <2>;
80 device-width = <2>;
81 #address-cells = <1>;
82 #size-cells = <1>;
83 partition@0 {
84 label = "kernel";
85 reg = <0x00000000 0x00300000>;
86 };
87 partition@300000 {
88 label = "firmware b";
89 reg = <0x00300000 0x00100000>;
90 read-only;
91 };
92 partition@400000 {
93 label = "fs";
94 reg = <0x00400000 0x00300000>;
95 };
96 partition@700000 {
97 label = "firmware a";
98 reg = <0x00700000 0x00100000>;
99 read-only;
100 };
101 };
102 };
104 soc8641@ffe00000 {
105 #address-cells = <1>;
106 #size-cells = <1>;
107 device_type = "soc";
108 compatible = "simple-bus";
109 ranges = <0x00000000 0xffe00000 0x00100000>;
110 bus-frequency = <0>;
112 mcm-law@0 {
113 compatible = "fsl,mcm-law";
114 reg = <0x0 0x1000>;
115 fsl,num-laws = <10>;
116 };
118 mcm@1000 {
119 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
120 reg = <0x1000 0x1000>;
121 interrupts = <17 2>;
122 interrupt-parent = <&mpic>;
123 };
125 i2c@3000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 cell-index = <0>;
129 compatible = "fsl-i2c";
130 reg = <0x3000 0x100>;
131 interrupts = <43 2>;
132 interrupt-parent = <&mpic>;
133 dfsrr;
134 };
136 i2c@3100 {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 cell-index = <1>;
140 compatible = "fsl-i2c";
141 reg = <0x3100 0x100>;
142 interrupts = <43 2>;
143 interrupt-parent = <&mpic>;
144 dfsrr;
145 };
147 dma@21300 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
151 reg = <0x21300 0x4>;
152 ranges = <0x0 0x21100 0x200>;
153 cell-index = <0>;
154 dma-channel@0 {
155 compatible = "fsl,mpc8641-dma-channel",
156 "fsl,eloplus-dma-channel";
157 reg = <0x0 0x80>;
158 cell-index = <0>;
159 interrupt-parent = <&mpic>;
160 interrupts = <20 2>;
161 };
162 dma-channel@80 {
163 compatible = "fsl,mpc8641-dma-channel",
164 "fsl,eloplus-dma-channel";
165 reg = <0x80 0x80>;
166 cell-index = <1>;
167 interrupt-parent = <&mpic>;
168 interrupts = <21 2>;
169 };
170 dma-channel@100 {
171 compatible = "fsl,mpc8641-dma-channel",
172 "fsl,eloplus-dma-channel";
173 reg = <0x100 0x80>;
174 cell-index = <2>;
175 interrupt-parent = <&mpic>;
176 interrupts = <22 2>;
177 };
178 dma-channel@180 {
179 compatible = "fsl,mpc8641-dma-channel",
180 "fsl,eloplus-dma-channel";
181 reg = <0x180 0x80>;
182 cell-index = <3>;
183 interrupt-parent = <&mpic>;
184 interrupts = <23 2>;
185 };
186 };
188 enet0: ethernet@24000 {
189 #address-cells = <1>;
190 #size-cells = <1>;
191 cell-index = <0>;
192 device_type = "network";
193 model = "TSEC";
194 compatible = "gianfar";
195 reg = <0x24000 0x1000>;
196 ranges = <0x0 0x24000 0x1000>;
197 local-mac-address = [ 00 00 00 00 00 00 ];
198 interrupts = <29 2 30 2 34 2>;
199 interrupt-parent = <&mpic>;
200 tbi-handle = <&tbi0>;
201 phy-handle = <&phy0>;
202 phy-connection-type = "rgmii-id";
204 mdio@520 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,gianfar-mdio";
208 reg = <0x520 0x20>;
210 phy0: ethernet-phy@0 {
211 interrupt-parent = <&mpic>;
212 interrupts = <10 1>;
213 reg = <0>;
214 };
215 phy1: ethernet-phy@1 {
216 interrupt-parent = <&mpic>;
217 interrupts = <10 1>;
218 reg = <1>;
219 };
220 phy2: ethernet-phy@2 {
221 interrupt-parent = <&mpic>;
222 interrupts = <10 1>;
223 reg = <2>;
224 };
225 phy3: ethernet-phy@3 {
226 interrupt-parent = <&mpic>;
227 interrupts = <10 1>;
228 reg = <3>;
229 };
230 tbi0: tbi-phy@11 {
231 reg = <0x11>;
232 device_type = "tbi-phy";
233 };
234 };
235 };
237 enet1: ethernet@25000 {
238 #address-cells = <1>;
239 #size-cells = <1>;
240 cell-index = <1>;
241 device_type = "network";
242 model = "TSEC";
243 compatible = "gianfar";
244 reg = <0x25000 0x1000>;
245 ranges = <0x0 0x25000 0x1000>;
246 local-mac-address = [ 00 00 00 00 00 00 ];
247 interrupts = <35 2 36 2 40 2>;
248 interrupt-parent = <&mpic>;
249 tbi-handle = <&tbi1>;
250 phy-handle = <&phy1>;
251 phy-connection-type = "rgmii-id";
253 mdio@520 {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 compatible = "fsl,gianfar-tbi";
257 reg = <0x520 0x20>;
259 tbi1: tbi-phy@11 {
260 reg = <0x11>;
261 device_type = "tbi-phy";
262 };
263 };
264 };
266 enet2: ethernet@26000 {
267 #address-cells = <1>;
268 #size-cells = <1>;
269 cell-index = <2>;
270 device_type = "network";
271 model = "TSEC";
272 compatible = "gianfar";
273 reg = <0x26000 0x1000>;
274 ranges = <0x0 0x26000 0x1000>;
275 local-mac-address = [ 00 00 00 00 00 00 ];
276 interrupts = <31 2 32 2 33 2>;
277 interrupt-parent = <&mpic>;
278 tbi-handle = <&tbi2>;
279 phy-handle = <&phy2>;
280 phy-connection-type = "rgmii-id";
282 mdio@520 {
283 #address-cells = <1>;
284 #size-cells = <0>;
285 compatible = "fsl,gianfar-tbi";
286 reg = <0x520 0x20>;
288 tbi2: tbi-phy@11 {
289 reg = <0x11>;
290 device_type = "tbi-phy";
291 };
292 };
293 };
295 enet3: ethernet@27000 {
296 #address-cells = <1>;
297 #size-cells = <1>;
298 cell-index = <3>;
299 device_type = "network";
300 model = "TSEC";
301 compatible = "gianfar";
302 reg = <0x27000 0x1000>;
303 ranges = <0x0 0x27000 0x1000>;
304 local-mac-address = [ 00 00 00 00 00 00 ];
305 interrupts = <37 2 38 2 39 2>;
306 interrupt-parent = <&mpic>;
307 tbi-handle = <&tbi3>;
308 phy-handle = <&phy3>;
309 phy-connection-type = "rgmii-id";
311 mdio@520 {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "fsl,gianfar-tbi";
315 reg = <0x520 0x20>;
317 tbi3: tbi-phy@11 {
318 reg = <0x11>;
319 device_type = "tbi-phy";
320 };
321 };
322 };
324 serial0: serial@4500 {
325 cell-index = <0>;
326 device_type = "serial";
327 compatible = "fsl,ns16550", "ns16550";
328 reg = <0x4500 0x100>;
329 clock-frequency = <0>;
330 interrupts = <42 2>;
331 interrupt-parent = <&mpic>;
332 };
334 serial1: serial@4600 {
335 cell-index = <1>;
336 device_type = "serial";
337 compatible = "fsl,ns16550", "ns16550";
338 reg = <0x4600 0x100>;
339 clock-frequency = <0>;
340 interrupts = <28 2>;
341 interrupt-parent = <&mpic>;
342 };
344 mpic: pic@40000 {
345 interrupt-controller;
346 #address-cells = <0>;
347 #interrupt-cells = <2>;
348 reg = <0x40000 0x40000>;
349 compatible = "chrp,open-pic";
350 device_type = "open-pic";
351 };
353 rmu: rmu@d3000 {
354 #address-cells = <1>;
355 #size-cells = <1>;
356 compatible = "fsl,srio-rmu";
357 reg = <0xd3000 0x500>;
358 ranges = <0x0 0xd3000 0x500>;
360 message-unit@0 {
361 compatible = "fsl,srio-msg-unit";
362 reg = <0x0 0x100>;
363 interrupts = <
364 53 2 /* msg1_tx_irq */
365 54 2>;/* msg1_rx_irq */
366 };
367 message-unit@100 {
368 compatible = "fsl,srio-msg-unit";
369 reg = <0x100 0x100>;
370 interrupts = <
371 55 2 /* msg2_tx_irq */
372 56 2>;/* msg2_rx_irq */
373 };
374 doorbell-unit@400 {
375 compatible = "fsl,srio-dbell-unit";
376 reg = <0x400 0x80>;
377 interrupts = <
378 49 2 /* bell_outb_irq */
379 50 2>;/* bell_inb_irq */
380 };
381 port-write-unit@4e0 {
382 compatible = "fsl,srio-port-write-unit";
383 reg = <0x4e0 0x20>;
384 interrupts = <48 2>;
385 };
386 };
388 global-utilities@e0000 {
389 compatible = "fsl,mpc8641-guts";
390 reg = <0xe0000 0x1000>;
391 fsl,has-rstcr;
392 };
393 };
395 pci0: pcie@ffe08000 {
396 compatible = "fsl,mpc8641-pcie";
397 device_type = "pci";
398 #interrupt-cells = <1>;
399 #size-cells = <2>;
400 #address-cells = <3>;
401 reg = <0xffe08000 0x1000>;
402 bus-range = <0x0 0xff>;
403 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
404 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
405 clock-frequency = <33333333>;
406 interrupt-parent = <&mpic>;
407 interrupts = <24 2>;
408 interrupt-map-mask = <0xff00 0 0 7>;
409 interrupt-map = <
410 /* IDSEL 0x11 func 0 - PCI slot 1 */
411 0x8800 0 0 1 &mpic 2 1
412 0x8800 0 0 2 &mpic 3 1
413 0x8800 0 0 3 &mpic 4 1
414 0x8800 0 0 4 &mpic 1 1
416 /* IDSEL 0x11 func 1 - PCI slot 1 */
417 0x8900 0 0 1 &mpic 2 1
418 0x8900 0 0 2 &mpic 3 1
419 0x8900 0 0 3 &mpic 4 1
420 0x8900 0 0 4 &mpic 1 1
422 /* IDSEL 0x11 func 2 - PCI slot 1 */
423 0x8a00 0 0 1 &mpic 2 1
424 0x8a00 0 0 2 &mpic 3 1
425 0x8a00 0 0 3 &mpic 4 1
426 0x8a00 0 0 4 &mpic 1 1
428 /* IDSEL 0x11 func 3 - PCI slot 1 */
429 0x8b00 0 0 1 &mpic 2 1
430 0x8b00 0 0 2 &mpic 3 1
431 0x8b00 0 0 3 &mpic 4 1
432 0x8b00 0 0 4 &mpic 1 1
434 /* IDSEL 0x11 func 4 - PCI slot 1 */
435 0x8c00 0 0 1 &mpic 2 1
436 0x8c00 0 0 2 &mpic 3 1
437 0x8c00 0 0 3 &mpic 4 1
438 0x8c00 0 0 4 &mpic 1 1
440 /* IDSEL 0x11 func 5 - PCI slot 1 */
441 0x8d00 0 0 1 &mpic 2 1
442 0x8d00 0 0 2 &mpic 3 1
443 0x8d00 0 0 3 &mpic 4 1
444 0x8d00 0 0 4 &mpic 1 1
446 /* IDSEL 0x11 func 6 - PCI slot 1 */
447 0x8e00 0 0 1 &mpic 2 1
448 0x8e00 0 0 2 &mpic 3 1
449 0x8e00 0 0 3 &mpic 4 1
450 0x8e00 0 0 4 &mpic 1 1
452 /* IDSEL 0x11 func 7 - PCI slot 1 */
453 0x8f00 0 0 1 &mpic 2 1
454 0x8f00 0 0 2 &mpic 3 1
455 0x8f00 0 0 3 &mpic 4 1
456 0x8f00 0 0 4 &mpic 1 1
458 /* IDSEL 0x12 func 0 - PCI slot 2 */
459 0x9000 0 0 1 &mpic 3 1
460 0x9000 0 0 2 &mpic 4 1
461 0x9000 0 0 3 &mpic 1 1
462 0x9000 0 0 4 &mpic 2 1
464 /* IDSEL 0x12 func 1 - PCI slot 2 */
465 0x9100 0 0 1 &mpic 3 1
466 0x9100 0 0 2 &mpic 4 1
467 0x9100 0 0 3 &mpic 1 1
468 0x9100 0 0 4 &mpic 2 1
470 /* IDSEL 0x12 func 2 - PCI slot 2 */
471 0x9200 0 0 1 &mpic 3 1
472 0x9200 0 0 2 &mpic 4 1
473 0x9200 0 0 3 &mpic 1 1
474 0x9200 0 0 4 &mpic 2 1
476 /* IDSEL 0x12 func 3 - PCI slot 2 */
477 0x9300 0 0 1 &mpic 3 1
478 0x9300 0 0 2 &mpic 4 1
479 0x9300 0 0 3 &mpic 1 1
480 0x9300 0 0 4 &mpic 2 1
482 /* IDSEL 0x12 func 4 - PCI slot 2 */
483 0x9400 0 0 1 &mpic 3 1
484 0x9400 0 0 2 &mpic 4 1
485 0x9400 0 0 3 &mpic 1 1
486 0x9400 0 0 4 &mpic 2 1
488 /* IDSEL 0x12 func 5 - PCI slot 2 */
489 0x9500 0 0 1 &mpic 3 1
490 0x9500 0 0 2 &mpic 4 1
491 0x9500 0 0 3 &mpic 1 1
492 0x9500 0 0 4 &mpic 2 1
494 /* IDSEL 0x12 func 6 - PCI slot 2 */
495 0x9600 0 0 1 &mpic 3 1
496 0x9600 0 0 2 &mpic 4 1
497 0x9600 0 0 3 &mpic 1 1
498 0x9600 0 0 4 &mpic 2 1
500 /* IDSEL 0x12 func 7 - PCI slot 2 */
501 0x9700 0 0 1 &mpic 3 1
502 0x9700 0 0 2 &mpic 4 1
503 0x9700 0 0 3 &mpic 1 1
504 0x9700 0 0 4 &mpic 2 1
506 // IDSEL 0x1c USB
507 0xe000 0 0 1 &i8259 12 2
508 0xe100 0 0 2 &i8259 9 2
509 0xe200 0 0 3 &i8259 10 2
510 0xe300 0 0 4 &i8259 11 2
512 // IDSEL 0x1d Audio
513 0xe800 0 0 1 &i8259 6 2
515 // IDSEL 0x1e Legacy
516 0xf000 0 0 1 &i8259 7 2
517 0xf100 0 0 1 &i8259 7 2
519 // IDSEL 0x1f IDE/SATA
520 0xf800 0 0 1 &i8259 14 2
521 0xf900 0 0 1 &i8259 5 2
522 >;
524 pcie@0 {
525 reg = <0 0 0 0 0>;
526 #size-cells = <2>;
527 #address-cells = <3>;
528 device_type = "pci";
529 ranges = <0x02000000 0x0 0x80000000
530 0x02000000 0x0 0x80000000
531 0x0 0x20000000
533 0x01000000 0x0 0x00000000
534 0x01000000 0x0 0x00000000
535 0x0 0x00010000>;
536 uli1575@0 {
537 reg = <0 0 0 0 0>;
538 #size-cells = <2>;
539 #address-cells = <3>;
540 ranges = <0x02000000 0x0 0x80000000
541 0x02000000 0x0 0x80000000
542 0x0 0x20000000
543 0x01000000 0x0 0x00000000
544 0x01000000 0x0 0x00000000
545 0x0 0x00010000>;
546 isa@1e {
547 device_type = "isa";
548 #interrupt-cells = <2>;
549 #size-cells = <1>;
550 #address-cells = <2>;
551 reg = <0xf000 0 0 0 0>;
552 ranges = <1 0 0x01000000 0 0
553 0x00001000>;
554 interrupt-parent = <&i8259>;
556 i8259: interrupt-controller@20 {
557 reg = <1 0x20 2
558 1 0xa0 2
559 1 0x4d0 2>;
560 interrupt-controller;
561 device_type = "interrupt-controller";
562 #address-cells = <0>;
563 #interrupt-cells = <2>;
564 compatible = "chrp,iic";
565 interrupts = <9 2>;
566 interrupt-parent = <&mpic>;
567 };
569 i8042@60 {
570 #size-cells = <0>;
571 #address-cells = <1>;
572 reg = <1 0x60 1 1 0x64 1>;
573 interrupts = <1 3 12 3>;
574 interrupt-parent =
575 <&i8259>;
577 keyboard@0 {
578 reg = <0>;
579 compatible = "pnpPNP,303";
580 };
582 mouse@1 {
583 reg = <1>;
584 compatible = "pnpPNP,f03";
585 };
586 };
588 rtc@70 {
589 compatible =
590 "pnpPNP,b00";
591 reg = <1 0x70 2>;
592 };
594 gpio@400 {
595 reg = <1 0x400 0x80>;
596 };
597 };
598 };
599 };
601 };
603 pci1: pcie@ffe09000 {
604 compatible = "fsl,mpc8641-pcie";
605 device_type = "pci";
606 #interrupt-cells = <1>;
607 #size-cells = <2>;
608 #address-cells = <3>;
609 reg = <0xffe09000 0x1000>;
610 bus-range = <0 0xff>;
611 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
612 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
613 clock-frequency = <33333333>;
614 interrupt-parent = <&mpic>;
615 interrupts = <25 2>;
616 interrupt-map-mask = <0xf800 0 0 7>;
617 interrupt-map = <
618 /* IDSEL 0x0 */
619 0x0000 0 0 1 &mpic 4 1
620 0x0000 0 0 2 &mpic 5 1
621 0x0000 0 0 3 &mpic 6 1
622 0x0000 0 0 4 &mpic 7 1
623 >;
624 pcie@0 {
625 reg = <0 0 0 0 0>;
626 #size-cells = <2>;
627 #address-cells = <3>;
628 device_type = "pci";
629 ranges = <0x02000000 0x0 0xa0000000
630 0x02000000 0x0 0xa0000000
631 0x0 0x20000000
633 0x01000000 0x0 0x00000000
634 0x01000000 0x0 0x00000000
635 0x0 0x00010000>;
636 };
637 };
638 /*
639 * Only one of Rapid IO or PCI can be present due to HW limitations and
640 * due to the fact that the 2 now share address space in the new memory
641 * map. The most likely case is that we have PCI, so comment out the
642 * rapidio node. Leave it here for reference.
644 rapidio@ffec0000 {
645 reg = <0xffec0000 0x11000>;
646 compatible = "fsl,srio";
647 interrupt-parent = <&mpic>;
648 interrupts = <48 2>;
649 #address-cells = <2>;
650 #size-cells = <2>;
651 fsl,srio-rmu-handle = <&rmu>;
652 ranges;
654 port1 {
655 #address-cells = <2>;
656 #size-cells = <2>;
657 cell-index = <1>;
658 ranges = <0 0 0x80000000 0 0x20000000>;
659 };
660 };
661 */
663 };