arch/powerpc/boot/dts/t208xrdb.dtsi

   1 /*
   2  * T2080PCIe-RDB Board Device Tree Source
   3  *
   4  * Copyright 2014 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 / {
  36         model = "fsl,T2080RDB";
  37         compatible = "fsl,T2080RDB";
  38         #address-cells = <2>;
  39         #size-cells = <2>;
  40         interrupt-parent = <&mpic>;
  41
  42         reserved-memory {
  43                 #address-cells = <2>;
  44                 #size-cells = <2>;
  45                 ranges;
  46
  47                 bman_fbpr: bman-fbpr {
  48                         size = <0 0x1000000>;
  49                         alignment = <0 0x1000000>;
  50                 };
  51         };
  52
  53         ifc: localbus@ffe124000 {
  54                 reg = <0xf 0xfe124000 0 0x2000>;
  55                 ranges = <0 0 0xf 0xe8000000 0x08000000
  56                           2 0 0xf 0xff800000 0x00010000
  57                           3 0 0xf 0xffdf0000 0x00008000>;
  58
  59                 nor@0,0 {
  60                         #address-cells = <1>;
  61                         #size-cells = <1>;
  62                         compatible = "cfi-flash";
  63                         reg = <0x0 0x0 0x8000000>;
  64
  65                         bank-width = <2>;
  66                         device-width = <1>;
  67                 };
  68
  69                 nand@1,0 {
  70                         #address-cells = <1>;
  71                         #size-cells = <1>;
  72                         compatible = "fsl,ifc-nand";
  73                         reg = <0x2 0x0 0x10000>;
  74                 };
  75
  76                 boardctrl: board-control@2,0 {
  77                         #address-cells = <1>;
  78                         #size-cells = <1>;
  79                         compatible = "fsl,t2080-cpld";
  80                         reg = <3 0 0x300>;
  81                         ranges = <0 3 0 0x300>;
  82                 };
  83         };
  84
  85         memory {
  86                 device_type = "memory";
  87         };
  88
  89         dcsr: dcsr@f00000000 {
  90                 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
  91         };
  92
  93         bportals: bman-portals@ff4000000 {
  94                 ranges = <0x0 0xf 0xf4000000 0x2000000>;
  95         };
  96
  97         soc: soc@ffe000000 {
  98                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  99                 reg = <0xf 0xfe000000 0 0x00001000>;
 100                 spi@110000 {
 101                         flash@0 {
 102                                 #address-cells = <1>;
 103                                 #size-cells = <1>;
 104                                 compatible = "micron,n25q512a";
 105                                 reg = <0>;
 106                                 spi-max-frequency = <10000000>; /* input clock */
 107                         };
 108                 };
 109
 110                 i2c@118000 {
 111                         adt7481@4c {
 112                                 compatible = "adi,adt7481";
 113                                 reg = <0x4c>;
 114                         };
 115
 116                         rtc@68 {
 117                                 compatible = "dallas,ds1339";
 118                                 reg = <0x68>;
 119                                 interrupts = <0x1 0x1 0 0>;
 120                         };
 121
 122                         eeprom@50 {
 123                                 compatible = "atmel,24c256";
 124                                 reg = <0x50>;
 125                         };
 126                 };
 127
 128                 i2c@118100 {
 129                         pca9546@77 {
 130                                 compatible = "nxp,pca9546";
 131                                 reg = <0x77>;
 132                         };
 133                 };
 134
 135                 sdhc@114000 {
 136                         voltage-ranges = <1800 1800 3300 3300>;
 137                 };
 138         };
 139
 140         pci0: pcie@ffe240000 {
 141                 reg = <0xf 0xfe240000 0 0x10000>;
 142                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 143                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 144                 pcie@0 {
 145                         ranges = <0x02000000 0 0xe0000000
 146                                   0x02000000 0 0xe0000000
 147                                   0 0x20000000
 148
 149                                   0x01000000 0 0x00000000
 150                                   0x01000000 0 0x00000000
 151                                   0 0x00010000>;
 152                 };
 153         };
 154
 155         pci1: pcie@ffe250000 {
 156                 reg = <0xf 0xfe250000 0 0x10000>;
 157                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
 158                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 159                 pcie@0 {
 160                         ranges = <0x02000000 0 0xe0000000
 161                                   0x02000000 0 0xe0000000
 162                                   0 0x20000000
 163
 164                                   0x01000000 0 0x00000000
 165                                   0x01000000 0 0x00000000
 166                                   0 0x00010000>;
 167                 };
 168         };
 169
 170         pci2: pcie@ffe260000 {
 171                 reg = <0xf 0xfe260000 0 0x1000>;
 172                 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
 173                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 174                 pcie@0 {
 175                         ranges = <0x02000000 0 0xe0000000
 176                                   0x02000000 0 0xe0000000
 177                                   0 0x20000000
 178
 179                                   0x01000000 0 0x00000000
 180                                   0x01000000 0 0x00000000
 181                                   0 0x00010000>;
 182                 };
 183         };
 184
 185         pci3: pcie@ffe270000 {
 186                 reg = <0xf 0xfe270000 0 0x10000>;
 187                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
 188                           0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
 189                 pcie@0 {
 190                         ranges = <0x02000000 0 0xe0000000
 191                                   0x02000000 0 0xe0000000
 192                                   0 0x20000000
 193
 194                                   0x01000000 0 0x00000000
 195                                   0x01000000 0 0x00000000
 196                                   0 0x00010000>;
 197                 };
 198         };
 199 };