2 * Copyright (C) 2013 DENX Software Engineering
4 * Gerhard Sittig, <gsi@denx.de>
6 * common clock driver support for the MPC512x platform
8 * This is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/bitops.h>
15 #include <linux/clk-provider.h>
16 #include <linux/clkdev.h>
17 #include <linux/device.h>
18 #include <linux/errno.h>
21 #include <linux/of_address.h>
23 #include <asm/mpc5121.h>
24 #include <dt-bindings/clock/mpc512x-clock.h>
26 #include "mpc512x.h" /* our public mpc5121_clk_init() API */
28 /* helpers to keep the MCLK intermediates "somewhere" in our table */
40 #define NR_MCLKS (NR_PSCS + NR_MSCANS + NR_SPDIFS + NR_OUTCLK)
42 /* extend the public set of clocks by adding internal slots for management */
44 /* arrange for adjacent numbers after the public set */
45 MPC512x_CLK_START_PRIVATE
= MPC512x_CLK_LAST_PUBLIC
,
46 /* clocks which aren't announced to the public */
50 /* intermediates in div+gate combos or fractional dividers */
57 MPC512x_CLK_MBX_BUS_UG
,
59 MPC512x_CLK_MBX_3D_UG
,
63 MPC512x_CLK_SPDIF_TX_IN
,
64 /* intermediates for the mux+gate+div+mux MCLK generation */
65 MPC512x_CLK_MCLKS_FIRST
,
66 MPC512x_CLK_MCLKS_LAST
= MPC512x_CLK_MCLKS_FIRST
67 + NR_MCLKS
* MCLK_MAX_IDX
,
68 /* internal, symbolic spec for the number of slots */
69 MPC512x_CLK_LAST_PRIVATE
,
72 /* data required for the OF clock provider registration */
73 static struct clk
*clks
[MPC512x_CLK_LAST_PRIVATE
];
74 static struct clk_onecell_data clk_data
;
76 /* CCM register access */
77 static struct mpc512x_ccm __iomem
*clkregs
;
78 static DEFINE_SPINLOCK(clklock
);
80 /* SoC variants {{{ */
83 * tell SoC variants apart as they are rather similar yet not identical,
84 * cache the result in an enum to not repeatedly run the expensive OF test
86 * MPC5123 is an MPC5121 without the MBX graphics accelerator
88 * MPC5125 has many more differences: no MBX, no AXE, no VIU, no SPDIF,
89 * no PATA, no SATA, no PCI, two FECs (of different compatibility name),
90 * only 10 PSCs (of different compatibility name), two SDHCs, different
91 * NFC IP block, output clocks, system PLL status query, different CPMF
92 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
93 * those differences can get folded into this clock provider support
94 * code and don't warrant a separate highly redundant implementation
97 static enum soc_type
{
103 static void mpc512x_clk_determine_soc(void)
105 if (of_machine_is_compatible("fsl,mpc5121")) {
106 soc
= MPC512x_SOC_MPC5121
;
109 if (of_machine_is_compatible("fsl,mpc5123")) {
110 soc
= MPC512x_SOC_MPC5123
;
113 if (of_machine_is_compatible("fsl,mpc5125")) {
114 soc
= MPC512x_SOC_MPC5125
;
119 static bool soc_has_mbx(void)
121 if (soc
== MPC512x_SOC_MPC5121
)
126 static bool soc_has_axe(void)
128 if (soc
== MPC512x_SOC_MPC5125
)
133 static bool soc_has_viu(void)
135 if (soc
== MPC512x_SOC_MPC5125
)
140 static bool soc_has_spdif(void)
142 if (soc
== MPC512x_SOC_MPC5125
)
147 static bool soc_has_pata(void)
149 if (soc
== MPC512x_SOC_MPC5125
)
154 static bool soc_has_sata(void)
156 if (soc
== MPC512x_SOC_MPC5125
)
161 static bool soc_has_pci(void)
163 if (soc
== MPC512x_SOC_MPC5125
)
168 static bool soc_has_fec2(void)
170 if (soc
== MPC512x_SOC_MPC5125
)
175 static int soc_max_pscnum(void)
177 if (soc
== MPC512x_SOC_MPC5125
)
182 static bool soc_has_sdhc2(void)
184 if (soc
== MPC512x_SOC_MPC5125
)
189 static bool soc_has_nfc_5125(void)
191 if (soc
== MPC512x_SOC_MPC5125
)
196 static bool soc_has_outclk(void)
198 if (soc
== MPC512x_SOC_MPC5125
)
203 static bool soc_has_cpmf_0_bypass(void)
205 if (soc
== MPC512x_SOC_MPC5125
)
210 static bool soc_has_mclk_mux0_canin(void)
212 if (soc
== MPC512x_SOC_MPC5125
)
217 /* }}} SoC variants */
218 /* common clk API wrappers {{{ */
220 /* convenience wrappers around the common clk API */
221 static inline struct clk
*mpc512x_clk_fixed(const char *name
, int rate
)
223 return clk_register_fixed_rate(NULL
, name
, NULL
, CLK_IS_ROOT
, rate
);
226 static inline struct clk
*mpc512x_clk_factor(
227 const char *name
, const char *parent_name
,
232 clkflags
= CLK_SET_RATE_PARENT
;
233 return clk_register_fixed_factor(NULL
, name
, parent_name
, clkflags
,
237 static inline struct clk
*mpc512x_clk_divider(
238 const char *name
, const char *parent_name
, u8 clkflags
,
239 u32 __iomem
*reg
, u8 pos
, u8 len
, int divflags
)
241 return clk_register_divider(NULL
, name
, parent_name
, clkflags
,
242 reg
, pos
, len
, divflags
, &clklock
);
245 static inline struct clk
*mpc512x_clk_divtable(
246 const char *name
, const char *parent_name
,
247 u32 __iomem
*reg
, u8 pos
, u8 len
,
248 const struct clk_div_table
*divtab
)
253 return clk_register_divider_table(NULL
, name
, parent_name
, 0,
254 reg
, pos
, len
, divflags
,
258 static inline struct clk
*mpc512x_clk_gated(
259 const char *name
, const char *parent_name
,
260 u32 __iomem
*reg
, u8 pos
)
264 clkflags
= CLK_SET_RATE_PARENT
;
265 return clk_register_gate(NULL
, name
, parent_name
, clkflags
,
266 reg
, pos
, 0, &clklock
);
269 static inline struct clk
*mpc512x_clk_muxed(const char *name
,
270 const char **parent_names
, int parent_count
,
271 u32 __iomem
*reg
, u8 pos
, u8 len
)
276 clkflags
= CLK_SET_RATE_PARENT
;
278 return clk_register_mux(NULL
, name
,
279 parent_names
, parent_count
, clkflags
,
280 reg
, pos
, len
, muxflags
, &clklock
);
283 /* }}} common clk API wrappers */
285 /* helper to isolate a bit field from a register */
286 static inline int get_bit_field(uint32_t __iomem
*reg
, uint8_t pos
, uint8_t len
)
292 val
&= (1 << len
) - 1;
296 /* get the SPMF and translate it into the "sys pll" multiplier */
297 static int get_spmf_mult(void)
299 static int spmf_to_mult
[] = {
300 68, 1, 12, 16, 20, 24, 28, 32,
301 36, 40, 44, 48, 52, 56, 60, 64,
305 spmf
= get_bit_field(&clkregs
->spmr
, 24, 4);
306 return spmf_to_mult
[spmf
];
310 * get the SYS_DIV value and translate it into a divide factor
312 * values returned from here are a multiple of the real factor since the
313 * divide ratio is fractional
315 static int get_sys_div_x2(void)
317 static int sysdiv_code_to_x2
[] = {
318 4, 5, 6, 7, 8, 9, 10, 14,
319 12, 16, 18, 22, 20, 24, 26, 30,
320 28, 32, 34, 38, 36, 40, 42, 46,
321 44, 48, 50, 54, 52, 56, 58, 62,
326 divcode
= get_bit_field(&clkregs
->scfr2
, 26, 6);
327 return sysdiv_code_to_x2
[divcode
];
331 * get the CPMF value and translate it into a multiplier factor
333 * values returned from here are a multiple of the real factor since the
334 * multiplier ratio is fractional
336 static int get_cpmf_mult_x2(void)
338 static int cpmf_to_mult_x36
[] = {
339 /* 0b000 is "times 36" */
340 72, 2, 2, 3, 4, 5, 6, 7,
342 static int cpmf_to_mult_0by
[] = {
343 /* 0b000 is "bypass" */
344 2, 2, 2, 3, 4, 5, 6, 7,
350 cpmf
= get_bit_field(&clkregs
->spmr
, 16, 4);
351 if (soc_has_cpmf_0_bypass())
352 cpmf_to_mult
= cpmf_to_mult_0by
;
354 cpmf_to_mult
= cpmf_to_mult_x36
;
355 return cpmf_to_mult
[cpmf
];
359 * some of the clock dividers do scale in a linear way, yet not all of
360 * their bit combinations are legal; use a divider table to get a
361 * resulting set of applicable divider values
364 /* applies to the IPS_DIV, and PCI_DIV values */
365 static struct clk_div_table divtab_2346
[] = {
366 { .val
= 2, .div
= 2, },
367 { .val
= 3, .div
= 3, },
368 { .val
= 4, .div
= 4, },
369 { .val
= 6, .div
= 6, },
373 /* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */
374 static struct clk_div_table divtab_1234
[] = {
375 { .val
= 1, .div
= 1, },
376 { .val
= 2, .div
= 2, },
377 { .val
= 3, .div
= 3, },
378 { .val
= 4, .div
= 4, },
382 static int get_freq_from_dt(char *propname
)
384 struct device_node
*np
;
385 const unsigned int *prop
;
389 np
= of_find_compatible_node(NULL
, NULL
, "fsl,mpc5121-immr");
391 prop
= of_get_property(np
, propname
, NULL
);
399 static void mpc512x_clk_preset_data(void)
403 for (i
= 0; i
< ARRAY_SIZE(clks
); i
++)
404 clks
[i
] = ERR_PTR(-ENODEV
);
408 * - receives the "bus frequency" from the caller (that's the IPS clock
409 * rate, the historical source of clock information)
410 * - fetches the system PLL multiplier and divider values as well as the
411 * IPS divider value from hardware
412 * - determines the REF clock rate either from the XTAL/OSC spec (if
413 * there is a device tree node describing the oscillator) or from the
414 * IPS bus clock (supported for backwards compatibility, such that
415 * setups without XTAL/OSC specs keep working)
416 * - creates the "ref" clock item in the clock tree, such that
417 * subsequent code can create the remainder of the hierarchy (REF ->
418 * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
421 static void mpc512x_clk_setup_ref_clock(struct device_node
*np
, int bus_freq
,
422 int *sys_mul
, int *sys_div
,
428 /* fetch mul/div factors from the hardware */
429 *sys_mul
= get_spmf_mult();
430 *sys_mul
*= 2; /* compensate for the fractional divider */
431 *sys_div
= get_sys_div_x2();
432 *ips_div
= get_bit_field(&clkregs
->scfr1
, 23, 3);
434 /* lookup the oscillator clock for its rate */
435 osc_clk
= of_clk_get_by_name(np
, "osc");
438 * either descend from OSC to REF (and in bypassing verify the
439 * IPS rate), or backtrack from IPS and multiplier values that
440 * were fetched from hardware to REF and thus to the OSC value
442 * in either case the REF clock gets created here and the
443 * remainder of the clock tree can get spanned from there
445 if (!IS_ERR(osc_clk
)) {
446 clks
[MPC512x_CLK_REF
] = mpc512x_clk_factor("ref", "osc", 1, 1);
447 calc_freq
= clk_get_rate(clks
[MPC512x_CLK_REF
]);
448 calc_freq
*= *sys_mul
;
449 calc_freq
/= *sys_div
;
451 calc_freq
/= *ips_div
;
452 if (bus_freq
&& calc_freq
!= bus_freq
)
453 pr_warn("calc rate %d != OF spec %d\n",
454 calc_freq
, bus_freq
);
456 calc_freq
= bus_freq
; /* start with IPS */
457 calc_freq
*= *ips_div
; /* IPS -> CSB */
458 calc_freq
*= 2; /* CSB -> SYS */
459 calc_freq
*= *sys_div
; /* SYS -> PLL out */
460 calc_freq
/= *sys_mul
; /* PLL out -> REF == OSC */
461 clks
[MPC512x_CLK_REF
] = mpc512x_clk_fixed("ref", calc_freq
);
465 /* MCLK helpers {{{ */
468 * helper code for the MCLK subtree setup
470 * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4
471 * suggests that all instances of the "PSC clock generation" are equal,
472 * and that one might re-use the PSC setup for MSCAN clock generation
473 * (section 5.2.5) as well, at least the logic if not the data for
476 * the details (starting at page 5-20) show differences in the specific
477 * inputs of the first mux stage ("can clk in", "spdif tx"), and the
478 * factual non-availability of the second mux stage (it's present yet
479 * only one input is valid)
481 * the MSCAN clock related registers (starting at page 5-35) all
482 * reference "spdif clk" at the first mux stage and don't mention any
483 * "can clk" at all, which somehow is unexpected
485 * TODO re-check the document, and clarify whether the RM is correct in
486 * the overview or in the details, and whether the difference is a
487 * clipboard induced error or results from chip revisions
489 * it turns out that the RM rev4 as of 2012-06 talks about "can" for the
490 * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that
491 * first a doc update is required which better reflects reality in the
492 * SoC before the implementation should follow while no questions remain
496 * note that this declaration raises a checkpatch warning, but
497 * it's the very data type dictated by <linux/clk-provider.h>,
498 * "fixing" this warning will break compilation
500 static const char *parent_names_mux0_spdif
[] = {
501 "sys", "ref", "psc-mclk-in", "spdif-tx",
504 static const char *parent_names_mux0_canin
[] = {
505 "sys", "ref", "psc-mclk-in", "can-clk-in",
515 struct mclk_setup_data
{
518 const char *name_mux0
;
519 const char *name_en0
;
520 const char *name_div0
;
521 const char *parent_names_mux1
[2];
522 const char *name_mclk
;
525 #define MCLK_SETUP_DATA_PSC(id) { \
529 "psc" #id "_mclk_div", \
530 { "psc" #id "_mclk_div", "dummy", }, \
534 #define MCLK_SETUP_DATA_MSCAN(id) { \
535 MCLK_TYPE_MSCAN, 0, \
536 "mscan" #id "-mux0", \
537 "mscan" #id "-en0", \
538 "mscan" #id "_mclk_div", \
539 { "mscan" #id "_mclk_div", "dummy", }, \
540 "mscan" #id "_mclk", \
543 #define MCLK_SETUP_DATA_SPDIF { \
544 MCLK_TYPE_SPDIF, 1, \
548 { "spdif_mclk_div", "spdif-rx", }, \
552 #define MCLK_SETUP_DATA_OUTCLK(id) { \
553 MCLK_TYPE_OUTCLK, 0, \
556 "out" #id "_mclk_div", \
557 { "out" #id "_mclk_div", "dummy", }, \
561 static struct mclk_setup_data mclk_psc_data
[] = {
562 MCLK_SETUP_DATA_PSC(0),
563 MCLK_SETUP_DATA_PSC(1),
564 MCLK_SETUP_DATA_PSC(2),
565 MCLK_SETUP_DATA_PSC(3),
566 MCLK_SETUP_DATA_PSC(4),
567 MCLK_SETUP_DATA_PSC(5),
568 MCLK_SETUP_DATA_PSC(6),
569 MCLK_SETUP_DATA_PSC(7),
570 MCLK_SETUP_DATA_PSC(8),
571 MCLK_SETUP_DATA_PSC(9),
572 MCLK_SETUP_DATA_PSC(10),
573 MCLK_SETUP_DATA_PSC(11),
576 static struct mclk_setup_data mclk_mscan_data
[] = {
577 MCLK_SETUP_DATA_MSCAN(0),
578 MCLK_SETUP_DATA_MSCAN(1),
579 MCLK_SETUP_DATA_MSCAN(2),
580 MCLK_SETUP_DATA_MSCAN(3),
583 static struct mclk_setup_data mclk_spdif_data
[] = {
584 MCLK_SETUP_DATA_SPDIF
,
587 static struct mclk_setup_data mclk_outclk_data
[] = {
588 MCLK_SETUP_DATA_OUTCLK(0),
589 MCLK_SETUP_DATA_OUTCLK(1),
590 MCLK_SETUP_DATA_OUTCLK(2),
591 MCLK_SETUP_DATA_OUTCLK(3),
594 /* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
595 static void mpc512x_clk_setup_mclk(struct mclk_setup_data
*entry
, size_t idx
)
597 size_t clks_idx_pub
, clks_idx_int
;
598 u32 __iomem
*mccr_reg
; /* MCLK control register (mux, en, div) */
601 /* derive a few parameters from the component type and index */
602 switch (entry
->type
) {
604 clks_idx_pub
= MPC512x_CLK_PSC0_MCLK
+ idx
;
605 clks_idx_int
= MPC512x_CLK_MCLKS_FIRST
606 + (idx
) * MCLK_MAX_IDX
;
607 mccr_reg
= &clkregs
->psc_ccr
[idx
];
609 case MCLK_TYPE_MSCAN
:
610 clks_idx_pub
= MPC512x_CLK_MSCAN0_MCLK
+ idx
;
611 clks_idx_int
= MPC512x_CLK_MCLKS_FIRST
612 + (NR_PSCS
+ idx
) * MCLK_MAX_IDX
;
613 mccr_reg
= &clkregs
->mscan_ccr
[idx
];
615 case MCLK_TYPE_SPDIF
:
616 clks_idx_pub
= MPC512x_CLK_SPDIF_MCLK
;
617 clks_idx_int
= MPC512x_CLK_MCLKS_FIRST
618 + (NR_PSCS
+ NR_MSCANS
) * MCLK_MAX_IDX
;
619 mccr_reg
= &clkregs
->spccr
;
621 case MCLK_TYPE_OUTCLK
:
622 clks_idx_pub
= MPC512x_CLK_OUT0_CLK
+ idx
;
623 clks_idx_int
= MPC512x_CLK_MCLKS_FIRST
624 + (NR_PSCS
+ NR_MSCANS
+ NR_SPDIFS
+ idx
)
626 mccr_reg
= &clkregs
->out_ccr
[idx
];
633 * this was grabbed from the PPC_CLOCK implementation, which
634 * enforced a specific MCLK divider while the clock was gated
635 * during setup (that's a documented hardware requirement)
637 * the PPC_CLOCK implementation might even have violated the
638 * "MCLK <= IPS" constraint, the fixed divider value of 1
639 * results in a divider of 2 and thus MCLK = SYS/2 which equals
640 * CSB which is greater than IPS; the serial port setup may have
641 * adjusted the divider which the clock setup might have left in
642 * an undesirable state
646 * - MCLK DIV such to not exceed the IPS clock
648 * - MCLK 1 from MCLK DIV
650 div
= clk_get_rate(clks
[MPC512x_CLK_SYS
]);
651 div
/= clk_get_rate(clks
[MPC512x_CLK_IPS
]);
652 out_be32(mccr_reg
, (0 << 16));
653 out_be32(mccr_reg
, (0 << 16) | ((div
- 1) << 17));
654 out_be32(mccr_reg
, (1 << 16) | ((div
- 1) << 17));
657 * create the 'struct clk' items of the MCLK's clock subtree
659 * note that by design we always create all nodes and won't take
660 * shortcuts here, because
661 * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
662 * selectable inputs to the CFM while those who "actually use"
663 * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
665 * - in the absence of "aliases" for clocks we need to create
666 * individial 'struct clk' items for whatever might get
667 * referenced or looked up, even if several of those items are
668 * identical from the logical POV (their rate value)
669 * - for easier future maintenance and for better reflection of
670 * the SoC's documentation, it appears appropriate to generate
671 * clock items even for those muxers which actually are NOPs
672 * (those with two inputs of which one is reserved)
674 clks
[clks_idx_int
+ MCLK_IDX_MUX0
] = mpc512x_clk_muxed(
676 soc_has_mclk_mux0_canin()
677 ? &parent_names_mux0_canin
[0]
678 : &parent_names_mux0_spdif
[0],
679 ARRAY_SIZE(parent_names_mux0_spdif
),
681 clks
[clks_idx_int
+ MCLK_IDX_EN0
] = mpc512x_clk_gated(
682 entry
->name_en0
, entry
->name_mux0
,
684 clks
[clks_idx_int
+ MCLK_IDX_DIV0
] = mpc512x_clk_divider(
686 entry
->name_en0
, CLK_SET_RATE_GATE
,
687 mccr_reg
, 17, 15, 0);
688 if (entry
->has_mclk1
) {
689 clks
[clks_idx_pub
] = mpc512x_clk_muxed(
691 &entry
->parent_names_mux1
[0],
692 ARRAY_SIZE(entry
->parent_names_mux1
),
695 clks
[clks_idx_pub
] = mpc512x_clk_factor(
697 entry
->parent_names_mux1
[0],
702 /* }}} MCLK helpers */
704 static void mpc512x_clk_setup_clock_tree(struct device_node
*np
, int busfreq
)
706 int sys_mul
, sys_div
, ips_div
;
713 * - consider whether to handle clocks which have both gates and
714 * dividers via intermediates or by means of composites
715 * - fractional dividers appear to not map well to composites
716 * since they can be seen as a fixed multiplier and an
717 * adjustable divider, while composites can only combine at
718 * most one of a mux, div, and gate each into one 'struct clk'
720 * - PSC/MSCAN/SPDIF clock generation OTOH already is very
721 * specific and cannot get mapped to componsites (at least not
722 * a single one, maybe two of them, but then some of these
723 * intermediate clock signals get referenced elsewhere (e.g.
724 * in the clock frequency measurement, CFM) and thus need
725 * publicly available names
726 * - the current source layout appropriately reflects the
727 * hardware setup, and it works, so it's questionable whether
728 * further changes will result in big enough a benefit
731 /* regardless of whether XTAL/OSC exists, have REF created */
732 mpc512x_clk_setup_ref_clock(np
, busfreq
, &sys_mul
, &sys_div
, &ips_div
);
734 /* now setup the REF -> SYS -> CSB -> IPS hierarchy */
735 clks
[MPC512x_CLK_SYS
] = mpc512x_clk_factor("sys", "ref",
737 clks
[MPC512x_CLK_CSB
] = mpc512x_clk_factor("csb", "sys", 1, 2);
738 clks
[MPC512x_CLK_IPS
] = mpc512x_clk_divtable("ips", "csb",
739 &clkregs
->scfr1
, 23, 3,
741 /* now setup anything below SYS and CSB and IPS */
743 clks
[MPC512x_CLK_DDR_UG
] = mpc512x_clk_factor("ddr-ug", "sys", 1, 2);
746 * the Reference Manual discusses that for SDHC only even divide
747 * ratios are supported because clock domain synchronization
748 * between 'per' and 'ipg' is broken;
749 * keep the divider's bit 0 cleared (per reset value), and only
750 * allow to setup the divider's bits 7:1, which results in that
751 * only even divide ratios can get configured upon rate changes;
752 * keep the "x4" name because this bit shift hack is an internal
753 * implementation detail, the "fractional divider with quarters"
756 clks
[MPC512x_CLK_SDHC_x4
] = mpc512x_clk_factor("sdhc-x4", "csb", 2, 1);
757 clks
[MPC512x_CLK_SDHC_UG
] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0,
758 &clkregs
->scfr2
, 1, 7,
759 CLK_DIVIDER_ONE_BASED
);
760 if (soc_has_sdhc2()) {
761 clks
[MPC512x_CLK_SDHC2_UG
] = mpc512x_clk_divider(
762 "sdhc2-ug", "sdhc-x4", 0, &clkregs
->scfr2
,
763 9, 7, CLK_DIVIDER_ONE_BASED
);
766 clks
[MPC512x_CLK_DIU_x4
] = mpc512x_clk_factor("diu-x4", "csb", 4, 1);
767 clks
[MPC512x_CLK_DIU_UG
] = mpc512x_clk_divider("diu-ug", "diu-x4", 0,
768 &clkregs
->scfr1
, 0, 8,
769 CLK_DIVIDER_ONE_BASED
);
772 * the "power architecture PLL" was setup from data which was
773 * sampled from the reset config word, at this point in time the
774 * configuration can be considered fixed and read only (i.e. no
775 * longer adjustable, or no longer in need of adjustment), which
776 * is why we don't register a PLL here but assume fixed factors
778 mul
= get_cpmf_mult_x2();
779 div
= 2; /* compensate for the fractional factor */
780 clks
[MPC512x_CLK_E300
] = mpc512x_clk_factor("e300", "csb", mul
, div
);
783 clks
[MPC512x_CLK_MBX_BUS_UG
] = mpc512x_clk_factor(
784 "mbx-bus-ug", "csb", 1, 2);
785 clks
[MPC512x_CLK_MBX_UG
] = mpc512x_clk_divtable(
786 "mbx-ug", "mbx-bus-ug", &clkregs
->scfr1
,
788 clks
[MPC512x_CLK_MBX_3D_UG
] = mpc512x_clk_factor(
789 "mbx-3d-ug", "mbx-ug", 1, 1);
792 clks
[MPC512x_CLK_PCI_UG
] = mpc512x_clk_divtable(
793 "pci-ug", "csb", &clkregs
->scfr1
,
796 if (soc_has_nfc_5125()) {
798 * XXX TODO implement 5125 NFC clock setup logic,
799 * with high/low period counters in clkregs->scfr3,
800 * currently there are no users so it's ENOIMPL
802 clks
[MPC512x_CLK_NFC_UG
] = ERR_PTR(-ENOTSUPP
);
804 clks
[MPC512x_CLK_NFC_UG
] = mpc512x_clk_divtable(
805 "nfc-ug", "ips", &clkregs
->scfr1
,
808 clks
[MPC512x_CLK_LPC_UG
] = mpc512x_clk_divtable("lpc-ug", "ips",
809 &clkregs
->scfr1
, 11, 3,
812 clks
[MPC512x_CLK_LPC
] = mpc512x_clk_gated("lpc", "lpc-ug",
813 &clkregs
->sccr1
, 30);
814 clks
[MPC512x_CLK_NFC
] = mpc512x_clk_gated("nfc", "nfc-ug",
815 &clkregs
->sccr1
, 29);
816 if (soc_has_pata()) {
817 clks
[MPC512x_CLK_PATA
] = mpc512x_clk_gated(
818 "pata", "ips", &clkregs
->sccr1
, 28);
820 /* for PSCs there is a "registers" gate and a bitrate MCLK subtree */
821 for (mclk_idx
= 0; mclk_idx
< soc_max_pscnum(); mclk_idx
++) {
823 snprintf(name
, sizeof(name
), "psc%d", mclk_idx
);
824 clks
[MPC512x_CLK_PSC0
+ mclk_idx
] = mpc512x_clk_gated(
825 name
, "ips", &clkregs
->sccr1
, 27 - mclk_idx
);
826 mpc512x_clk_setup_mclk(&mclk_psc_data
[mclk_idx
], mclk_idx
);
828 clks
[MPC512x_CLK_PSC_FIFO
] = mpc512x_clk_gated("psc-fifo", "ips",
829 &clkregs
->sccr1
, 15);
830 if (soc_has_sata()) {
831 clks
[MPC512x_CLK_SATA
] = mpc512x_clk_gated(
832 "sata", "ips", &clkregs
->sccr1
, 14);
834 clks
[MPC512x_CLK_FEC
] = mpc512x_clk_gated("fec", "ips",
835 &clkregs
->sccr1
, 13);
837 clks
[MPC512x_CLK_PCI
] = mpc512x_clk_gated(
838 "pci", "pci-ug", &clkregs
->sccr1
, 11);
840 clks
[MPC512x_CLK_DDR
] = mpc512x_clk_gated("ddr", "ddr-ug",
841 &clkregs
->sccr1
, 10);
842 if (soc_has_fec2()) {
843 clks
[MPC512x_CLK_FEC2
] = mpc512x_clk_gated(
844 "fec2", "ips", &clkregs
->sccr1
, 9);
847 clks
[MPC512x_CLK_DIU
] = mpc512x_clk_gated("diu", "diu-ug",
848 &clkregs
->sccr2
, 31);
850 clks
[MPC512x_CLK_AXE
] = mpc512x_clk_gated(
851 "axe", "csb", &clkregs
->sccr2
, 30);
853 clks
[MPC512x_CLK_MEM
] = mpc512x_clk_gated("mem", "ips",
854 &clkregs
->sccr2
, 29);
855 clks
[MPC512x_CLK_USB1
] = mpc512x_clk_gated("usb1", "csb",
856 &clkregs
->sccr2
, 28);
857 clks
[MPC512x_CLK_USB2
] = mpc512x_clk_gated("usb2", "csb",
858 &clkregs
->sccr2
, 27);
859 clks
[MPC512x_CLK_I2C
] = mpc512x_clk_gated("i2c", "ips",
860 &clkregs
->sccr2
, 26);
861 /* MSCAN differs from PSC with just one gate for multiple components */
862 clks
[MPC512x_CLK_BDLC
] = mpc512x_clk_gated("bdlc", "ips",
863 &clkregs
->sccr2
, 25);
864 for (mclk_idx
= 0; mclk_idx
< ARRAY_SIZE(mclk_mscan_data
); mclk_idx
++)
865 mpc512x_clk_setup_mclk(&mclk_mscan_data
[mclk_idx
], mclk_idx
);
866 clks
[MPC512x_CLK_SDHC
] = mpc512x_clk_gated("sdhc", "sdhc-ug",
867 &clkregs
->sccr2
, 24);
868 /* there is only one SPDIF component, which shares MCLK support code */
869 if (soc_has_spdif()) {
870 clks
[MPC512x_CLK_SPDIF
] = mpc512x_clk_gated(
871 "spdif", "ips", &clkregs
->sccr2
, 23);
872 mpc512x_clk_setup_mclk(&mclk_spdif_data
[0], 0);
875 clks
[MPC512x_CLK_MBX_BUS
] = mpc512x_clk_gated(
876 "mbx-bus", "mbx-bus-ug", &clkregs
->sccr2
, 22);
877 clks
[MPC512x_CLK_MBX
] = mpc512x_clk_gated(
878 "mbx", "mbx-ug", &clkregs
->sccr2
, 21);
879 clks
[MPC512x_CLK_MBX_3D
] = mpc512x_clk_gated(
880 "mbx-3d", "mbx-3d-ug", &clkregs
->sccr2
, 20);
882 clks
[MPC512x_CLK_IIM
] = mpc512x_clk_gated("iim", "csb",
883 &clkregs
->sccr2
, 19);
885 clks
[MPC512x_CLK_VIU
] = mpc512x_clk_gated(
886 "viu", "csb", &clkregs
->sccr2
, 18);
888 if (soc_has_sdhc2()) {
889 clks
[MPC512x_CLK_SDHC2
] = mpc512x_clk_gated(
890 "sdhc-2", "sdhc2-ug", &clkregs
->sccr2
, 17);
893 if (soc_has_outclk()) {
894 size_t idx
; /* used as mclk_idx, just to trim line length */
895 for (idx
= 0; idx
< ARRAY_SIZE(mclk_outclk_data
); idx
++)
896 mpc512x_clk_setup_mclk(&mclk_outclk_data
[idx
], idx
);
900 * externally provided clocks (when implemented in hardware,
901 * device tree may specify values which otherwise were unknown)
903 freq
= get_freq_from_dt("psc_mclk_in");
906 clks
[MPC512x_CLK_PSC_MCLK_IN
] = mpc512x_clk_fixed("psc_mclk_in", freq
);
907 if (soc_has_mclk_mux0_canin()) {
908 freq
= get_freq_from_dt("can_clk_in");
909 clks
[MPC512x_CLK_CAN_CLK_IN
] = mpc512x_clk_fixed(
912 freq
= get_freq_from_dt("spdif_tx_in");
913 clks
[MPC512x_CLK_SPDIF_TX_IN
] = mpc512x_clk_fixed(
914 "spdif_tx_in", freq
);
915 freq
= get_freq_from_dt("spdif_rx_in");
916 clks
[MPC512x_CLK_SPDIF_TX_IN
] = mpc512x_clk_fixed(
917 "spdif_rx_in", freq
);
920 /* fixed frequency for AC97, always 24.567MHz */
921 clks
[MPC512x_CLK_AC97
] = mpc512x_clk_fixed("ac97", 24567000);
924 * pre-enable those "internal" clock items which never get
925 * claimed by any peripheral driver, to not have the clock
926 * subsystem disable them late at startup
928 clk_prepare_enable(clks
[MPC512x_CLK_DUMMY
]);
929 clk_prepare_enable(clks
[MPC512x_CLK_E300
]); /* PowerPC CPU */
930 clk_prepare_enable(clks
[MPC512x_CLK_DDR
]); /* DRAM */
931 clk_prepare_enable(clks
[MPC512x_CLK_MEM
]); /* SRAM */
932 clk_prepare_enable(clks
[MPC512x_CLK_IPS
]); /* SoC periph */
933 clk_prepare_enable(clks
[MPC512x_CLK_LPC
]); /* boot media */
937 * registers the set of public clocks (those listed in the dt-bindings/
938 * header file) for OF lookups, keeps the intermediates private to us
940 static void mpc5121_clk_register_of_provider(struct device_node
*np
)
942 clk_data
.clks
= clks
;
943 clk_data
.clk_num
= MPC512x_CLK_LAST_PUBLIC
+ 1; /* _not_ ARRAY_SIZE() */
944 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
);
948 * temporary support for the period of time between introduction of CCF
949 * support and the adjustment of peripheral drivers to OF based lookups
951 static void mpc5121_clk_provide_migration_support(void)
955 * pre-enable those clock items which are not yet appropriately
956 * acquired by their peripheral driver
958 * the PCI clock cannot get acquired by its peripheral driver,
959 * because for this platform the driver won't probe(), instead
960 * initialization is done from within the .setup_arch() routine
961 * at a point in time where the clock provider has not been
962 * setup yet and thus isn't available yet
964 * so we "pre-enable" the clock here, to not have the clock
965 * subsystem automatically disable this item in a late init call
967 * this PCI clock pre-enable workaround only applies when there
968 * are device tree nodes for PCI and thus the peripheral driver
969 * has attached to bridges, otherwise the PCI clock remains
970 * unused and so it gets disabled
972 clk_prepare_enable(clks
[MPC512x_CLK_PSC3_MCLK
]);/* serial console */
973 if (of_find_compatible_node(NULL
, "pci", "fsl,mpc5121-pci"))
974 clk_prepare_enable(clks
[MPC512x_CLK_PCI
]);
978 * those macros are not exactly pretty, but they encapsulate a lot
979 * of copy'n'paste heavy code which is even more ugly, and reduce
980 * the potential for inconsistencies in those many code copies
982 #define FOR_NODES(compatname) \
983 for_each_compatible_node(np, NULL, compatname)
985 #define NODE_PREP do { \
986 of_address_to_resource(np, 0, &res); \
987 snprintf(devname, sizeof(devname), "%08x.%s", res.start, np->name); \
990 #define NODE_CHK(clkname, clkitem, regnode, regflag) do { \
992 clk = of_clk_get_by_name(np, clkname); \
995 clk_register_clkdev(clk, clkname, devname); \
997 clk_register_clkdev(clk, clkname, np->name); \
998 did_register |= DID_REG_ ## regflag; \
999 pr_debug("clock alias name '%s' for dev '%s' pointer %p\n", \
1000 clkname, devname, clk); \
1007 * register source code provided fallback results for clock lookups,
1008 * these get consulted when OF based clock lookup fails (that is in the
1009 * case of not yet adjusted device tree data, where clock related specs
1012 static void mpc5121_clk_provide_backwards_compat(void)
1014 enum did_reg_flags
{
1015 DID_REG_PSC
= BIT(0),
1016 DID_REG_PSCFIFO
= BIT(1),
1017 DID_REG_NFC
= BIT(2),
1018 DID_REG_CAN
= BIT(3),
1019 DID_REG_I2C
= BIT(4),
1020 DID_REG_DIU
= BIT(5),
1021 DID_REG_VIU
= BIT(6),
1022 DID_REG_FEC
= BIT(7),
1023 DID_REG_USB
= BIT(8),
1024 DID_REG_PATA
= BIT(9),
1028 struct device_node
*np
;
1029 struct resource res
;
1035 FOR_NODES(mpc512x_select_psc_compat()) {
1037 idx
= (res
.start
>> 8) & 0xf;
1038 NODE_CHK("ipg", clks
[MPC512x_CLK_PSC0
+ idx
], 0, PSC
);
1039 NODE_CHK("mclk", clks
[MPC512x_CLK_PSC0_MCLK
+ idx
], 0, PSC
);
1042 FOR_NODES("fsl,mpc5121-psc-fifo") {
1044 NODE_CHK("ipg", clks
[MPC512x_CLK_PSC_FIFO
], 1, PSCFIFO
);
1047 FOR_NODES("fsl,mpc5121-nfc") {
1049 NODE_CHK("ipg", clks
[MPC512x_CLK_NFC
], 0, NFC
);
1052 FOR_NODES("fsl,mpc5121-mscan") {
1055 idx
+= (res
.start
& 0x2000) ? 2 : 0;
1056 idx
+= (res
.start
& 0x0080) ? 1 : 0;
1057 NODE_CHK("ipg", clks
[MPC512x_CLK_BDLC
], 0, CAN
);
1058 NODE_CHK("mclk", clks
[MPC512x_CLK_MSCAN0_MCLK
+ idx
], 0, CAN
);
1062 * do register the 'ips', 'sys', and 'ref' names globally
1063 * instead of inside each individual CAN node, as there is no
1064 * potential for a name conflict (in contrast to 'ipg' and 'mclk')
1066 if (did_register
& DID_REG_CAN
) {
1067 clk_register_clkdev(clks
[MPC512x_CLK_IPS
], "ips", NULL
);
1068 clk_register_clkdev(clks
[MPC512x_CLK_SYS
], "sys", NULL
);
1069 clk_register_clkdev(clks
[MPC512x_CLK_REF
], "ref", NULL
);
1072 FOR_NODES("fsl,mpc5121-i2c") {
1074 NODE_CHK("ipg", clks
[MPC512x_CLK_I2C
], 0, I2C
);
1078 * workaround for the fact that the I2C driver does an "anonymous"
1079 * lookup (NULL name spec, which yields the first clock spec) for
1080 * which we cannot register an alias -- a _global_ 'ipg' alias that
1081 * is not bound to any device name and returns the I2C clock item
1082 * is not a good idea
1084 * so we have the lookup in the peripheral driver fail, which is
1085 * silent and non-fatal, and pre-enable the clock item here such
1086 * that register access is possible
1088 * see commit b3bfce2b "i2c: mpc: cleanup clock API use" for
1089 * details, adjusting s/NULL/"ipg"/ in i2c-mpc.c would make this
1090 * workaround obsolete
1092 if (did_register
& DID_REG_I2C
)
1093 clk_prepare_enable(clks
[MPC512x_CLK_I2C
]);
1095 FOR_NODES("fsl,mpc5121-diu") {
1097 NODE_CHK("ipg", clks
[MPC512x_CLK_DIU
], 1, DIU
);
1100 FOR_NODES("fsl,mpc5121-viu") {
1102 NODE_CHK("ipg", clks
[MPC512x_CLK_VIU
], 0, VIU
);
1106 * note that 2771399a "fs_enet: cleanup clock API use" did use the
1107 * "per" string for the clock lookup in contrast to the "ipg" name
1108 * which most other nodes are using -- this is not a fatal thing
1109 * but just something to keep in mind when doing compatibility
1110 * registration, it's a non-issue with up-to-date device tree data
1112 FOR_NODES("fsl,mpc5121-fec") {
1114 NODE_CHK("per", clks
[MPC512x_CLK_FEC
], 0, FEC
);
1116 FOR_NODES("fsl,mpc5121-fec-mdio") {
1118 NODE_CHK("per", clks
[MPC512x_CLK_FEC
], 0, FEC
);
1121 * MPC5125 has two FECs: FEC1 at 0x2800, FEC2 at 0x4800;
1122 * the clock items don't "form an array" since FEC2 was
1123 * added only later and was not allowed to shift all other
1124 * clock item indices, so the numbers aren't adjacent
1126 FOR_NODES("fsl,mpc5125-fec") {
1128 if (res
.start
& 0x4000)
1129 idx
= MPC512x_CLK_FEC2
;
1131 idx
= MPC512x_CLK_FEC
;
1132 NODE_CHK("per", clks
[idx
], 0, FEC
);
1135 FOR_NODES("fsl,mpc5121-usb2-dr") {
1137 idx
= (res
.start
& 0x4000) ? 1 : 0;
1138 NODE_CHK("ipg", clks
[MPC512x_CLK_USB1
+ idx
], 0, USB
);
1141 FOR_NODES("fsl,mpc5121-pata") {
1143 NODE_CHK("ipg", clks
[MPC512x_CLK_PATA
], 0, PATA
);
1147 * try to collapse diagnostics into a single line of output yet
1148 * provide a full list of what is missing, to avoid noise in the
1149 * absence of up-to-date device tree data -- backwards
1150 * compatibility to old DTBs is a requirement, updates may be
1151 * desirable or preferrable but are not at all mandatory
1154 pr_notice("device tree lacks clock specs, adding fallbacks (0x%x,%s%s%s%s%s%s%s%s%s%s)\n",
1156 (did_register
& DID_REG_PSC
) ? " PSC" : "",
1157 (did_register
& DID_REG_PSCFIFO
) ? " PSCFIFO" : "",
1158 (did_register
& DID_REG_NFC
) ? " NFC" : "",
1159 (did_register
& DID_REG_CAN
) ? " CAN" : "",
1160 (did_register
& DID_REG_I2C
) ? " I2C" : "",
1161 (did_register
& DID_REG_DIU
) ? " DIU" : "",
1162 (did_register
& DID_REG_VIU
) ? " VIU" : "",
1163 (did_register
& DID_REG_FEC
) ? " FEC" : "",
1164 (did_register
& DID_REG_USB
) ? " USB" : "",
1165 (did_register
& DID_REG_PATA
) ? " PATA" : "");
1167 pr_debug("device tree has clock specs, no fallbacks added\n");
1172 * The "fixed-clock" nodes (which includes the oscillator node if the board's
1173 * DT provides one) has already been scanned by the of_clk_init() in
1176 int __init
mpc5121_clk_init(void)
1178 struct device_node
*clk_np
;
1181 /* map the clock control registers */
1182 clk_np
= of_find_compatible_node(NULL
, NULL
, "fsl,mpc5121-clock");
1185 clkregs
= of_iomap(clk_np
, 0);
1188 /* determine the SoC variant we run on */
1189 mpc512x_clk_determine_soc();
1191 /* invalidate all not yet registered clock slots */
1192 mpc512x_clk_preset_data();
1195 * add a dummy clock for those situations where a clock spec is
1196 * required yet no real clock is involved
1198 clks
[MPC512x_CLK_DUMMY
] = mpc512x_clk_fixed("dummy", 0);
1201 * have all the real nodes in the clock tree populated from REF
1202 * down to all leaves, either starting from the OSC node or from
1203 * a REF root that was created from the IPS bus clock input
1205 busfreq
= get_freq_from_dt("bus-frequency");
1206 mpc512x_clk_setup_clock_tree(clk_np
, busfreq
);
1208 /* register as an OF clock provider */
1209 mpc5121_clk_register_of_provider(clk_np
);
1212 * unbreak not yet adjusted peripheral drivers during migration
1213 * towards fully operational common clock support, and allow
1214 * operation in the absence of clock related device tree specs
1216 mpc5121_clk_provide_migration_support();
1217 mpc5121_clk_provide_backwards_compat();