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Linux 4.1.18
[linux/fpc-iii.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
blobc8d92950bc041bcebcb6a2361ebeac0ce3065279
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
9 */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26 #include <linux/delay.h>
27 #include <linux/crash_dump.h>
28 #include <linux/reboot.h>
29
30 #include <asm/uv/uv_mmrs.h>
31 #include <asm/uv/uv_hub.h>
32 #include <asm/current.h>
33 #include <asm/pgtable.h>
34 #include <asm/uv/bios.h>
35 #include <asm/uv/uv.h>
36 #include <asm/apic.h>
37 #include <asm/ipi.h>
38 #include <asm/smp.h>
39 #include <asm/x86_init.h>
40 #include <asm/nmi.h>
41
42 DEFINE_PER_CPU(int, x2apic_extra_bits);
43
44 #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
45
46 static enum uv_system_type uv_system_type;
47 static u64 gru_start_paddr, gru_end_paddr;
48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
49 static u64 gru_dist_lmask, gru_dist_umask;
50 static union uvh_apicid uvh_apicid;
51 int uv_min_hub_revision_id;
52 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
53 unsigned int uv_apicid_hibits;
54 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
55
56 static struct apic apic_x2apic_uv_x;
57
58 static unsigned long __init uv_early_read_mmr(unsigned long addr)
59 {
60 unsigned long val, *mmr;
61
62 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
63 val = *mmr;
64 early_iounmap(mmr, sizeof(*mmr));
65 return val;
66 }
67
68 static inline bool is_GRU_range(u64 start, u64 end)
69 {
70 if (gru_dist_base) {
71 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
72 u64 sl = start & gru_dist_lmask; /* base offset bits */
73 u64 eu = end & gru_dist_umask;
74 u64 el = end & gru_dist_lmask;
75
76 /* Must reside completely within a single GRU range */
77 return (sl == gru_dist_base && el == gru_dist_base &&
78 su >= gru_first_node_paddr &&
79 su <= gru_last_node_paddr &&
80 eu == su);
81 } else {
82 return start >= gru_start_paddr && end <= gru_end_paddr;
83 }
84 }
85
86 static bool uv_is_untracked_pat_range(u64 start, u64 end)
87 {
88 return is_ISA_range(start, end) || is_GRU_range(start, end);
89 }
90
91 static int __init early_get_pnodeid(void)
92 {
93 union uvh_node_id_u node_id;
94 union uvh_rh_gam_config_mmr_u m_n_config;
95 int pnode;
96
97 /* Currently, all blades have same revision number */
98 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
99 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
100 uv_min_hub_revision_id = node_id.s.revision;
101
102 switch (node_id.s.part_number) {
103 case UV2_HUB_PART_NUMBER:
104 case UV2_HUB_PART_NUMBER_X:
105 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
106 break;
107 case UV3_HUB_PART_NUMBER:
108 case UV3_HUB_PART_NUMBER_X:
109 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
110 break;
111 }
112
113 uv_hub_info->hub_revision = uv_min_hub_revision_id;
114 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
115 return pnode;
116 }
117
118 static void __init early_get_apic_pnode_shift(void)
119 {
120 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
121 if (!uvh_apicid.v)
122 /*
123 * Old bios, use default value
124 */
125 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
126 }
127
128 /*
129 * Add an extra bit as dictated by bios to the destination apicid of
130 * interrupts potentially passing through the UV HUB. This prevents
131 * a deadlock between interrupts and IO port operations.
132 */
133 static void __init uv_set_apicid_hibit(void)
134 {
135 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
136
137 if (is_uv1_hub()) {
138 apicid_mask.v =
139 uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
140 uv_apicid_hibits =
141 apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
142 }
143 }
144
145 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
146 {
147 int pnodeid;
148 int uv_apic;
149
150 if (strncmp(oem_id, "SGI", 3) != 0)
151 return 0;
152
153 /*
154 * Determine UV arch type.
155 * SGI: UV100/1000
156 * SGI2: UV2000/3000
157 * SGI3: UV300 (truncated to 4 chars because of different varieties)
158 */
159 uv_hub_info->hub_revision =
160 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
161 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
162 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
163
164 if (uv_hub_info->hub_revision == 0)
165 goto badbios;
166
167 pnodeid = early_get_pnodeid();
168 early_get_apic_pnode_shift();
169 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
170 x86_platform.nmi_init = uv_nmi_init;
171
172 if (!strcmp(oem_table_id, "UVX")) { /* most common */
173 uv_system_type = UV_X2APIC;
174 uv_apic = 0;
175
176 } else if (!strcmp(oem_table_id, "UVH")) { /* only UV1 systems */
177 uv_system_type = UV_NON_UNIQUE_APIC;
178 __this_cpu_write(x2apic_extra_bits,
179 pnodeid << uvh_apicid.s.pnode_shift);
180 uv_set_apicid_hibit();
181 uv_apic = 1;
182
183 } else if (!strcmp(oem_table_id, "UVL")) { /* only used for */
184 uv_system_type = UV_LEGACY_APIC; /* very small systems */
185 uv_apic = 0;
186
187 } else {
188 goto badbios;
189 }
190
191 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
192 oem_id, oem_table_id, uv_system_type,
193 uv_min_hub_revision_id, uv_apic);
194
195 return uv_apic;
196
197 badbios:
198 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
199 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
200 BUG();
201 }
202
203 enum uv_system_type get_uv_system_type(void)
204 {
205 return uv_system_type;
206 }
207
208 int is_uv_system(void)
209 {
210 return uv_system_type != UV_NONE;
211 }
212 EXPORT_SYMBOL_GPL(is_uv_system);
213
214 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
215 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
216
217 struct uv_blade_info *uv_blade_info;
218 EXPORT_SYMBOL_GPL(uv_blade_info);
219
220 short *uv_node_to_blade;
221 EXPORT_SYMBOL_GPL(uv_node_to_blade);
222
223 short *uv_cpu_to_blade;
224 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
225
226 short uv_possible_blades;
227 EXPORT_SYMBOL_GPL(uv_possible_blades);
228
229 unsigned long sn_rtc_cycles_per_second;
230 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
231
232 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
233 {
234 unsigned long val;
235 int pnode;
236
237 pnode = uv_apicid_to_pnode(phys_apicid);
238 phys_apicid |= uv_apicid_hibits;
239 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
240 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
241 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
242 APIC_DM_INIT;
243 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
244
245 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
246 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
247 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
248 APIC_DM_STARTUP;
249 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
250
251 atomic_set(&init_deasserted, 1);
252 return 0;
253 }
254
255 static void uv_send_IPI_one(int cpu, int vector)
256 {
257 unsigned long apicid;
258 int pnode;
259
260 apicid = per_cpu(x86_cpu_to_apicid, cpu);
261 pnode = uv_apicid_to_pnode(apicid);
262 uv_hub_send_ipi(pnode, apicid, vector);
263 }
264
265 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
266 {
267 unsigned int cpu;
268
269 for_each_cpu(cpu, mask)
270 uv_send_IPI_one(cpu, vector);
271 }
272
273 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
274 {
275 unsigned int this_cpu = smp_processor_id();
276 unsigned int cpu;
277
278 for_each_cpu(cpu, mask) {
279 if (cpu != this_cpu)
280 uv_send_IPI_one(cpu, vector);
281 }
282 }
283
284 static void uv_send_IPI_allbutself(int vector)
285 {
286 unsigned int this_cpu = smp_processor_id();
287 unsigned int cpu;
288
289 for_each_online_cpu(cpu) {
290 if (cpu != this_cpu)
291 uv_send_IPI_one(cpu, vector);
292 }
293 }
294
295 static void uv_send_IPI_all(int vector)
296 {
297 uv_send_IPI_mask(cpu_online_mask, vector);
298 }
299
300 static int uv_apic_id_valid(int apicid)
301 {
302 return 1;
303 }
304
305 static int uv_apic_id_registered(void)
306 {
307 return 1;
308 }
309
310 static void uv_init_apic_ldr(void)
311 {
312 }
313
314 static int
315 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
316 const struct cpumask *andmask,
317 unsigned int *apicid)
318 {
319 int unsigned cpu;
320
321 /*
322 * We're using fixed IRQ delivery, can only return one phys APIC ID.
323 * May as well be the first.
324 */
325 for_each_cpu_and(cpu, cpumask, andmask) {
326 if (cpumask_test_cpu(cpu, cpu_online_mask))
327 break;
328 }
329
330 if (likely(cpu < nr_cpu_ids)) {
331 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
332 return 0;
333 }
334
335 return -EINVAL;
336 }
337
338 static unsigned int x2apic_get_apic_id(unsigned long x)
339 {
340 unsigned int id;
341
342 WARN_ON(preemptible() && num_online_cpus() > 1);
343 id = x | __this_cpu_read(x2apic_extra_bits);
344
345 return id;
346 }
347
348 static unsigned long set_apic_id(unsigned int id)
349 {
350 unsigned long x;
351
352 /* maskout x2apic_extra_bits ? */
353 x = id;
354 return x;
355 }
356
357 static unsigned int uv_read_apic_id(void)
358 {
359
360 return x2apic_get_apic_id(apic_read(APIC_ID));
361 }
362
363 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
364 {
365 return uv_read_apic_id() >> index_msb;
366 }
367
368 static void uv_send_IPI_self(int vector)
369 {
370 apic_write(APIC_SELF_IPI, vector);
371 }
372
373 static int uv_probe(void)
374 {
375 return apic == &apic_x2apic_uv_x;
376 }
377
378 static struct apic __refdata apic_x2apic_uv_x = {
379
380 .name = "UV large system",
381 .probe = uv_probe,
382 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
383 .apic_id_valid = uv_apic_id_valid,
384 .apic_id_registered = uv_apic_id_registered,
385
386 .irq_delivery_mode = dest_Fixed,
387 .irq_dest_mode = 0, /* physical */
388
389 .target_cpus = online_target_cpus,
390 .disable_esr = 0,
391 .dest_logical = APIC_DEST_LOGICAL,
392 .check_apicid_used = NULL,
393
394 .vector_allocation_domain = default_vector_allocation_domain,
395 .init_apic_ldr = uv_init_apic_ldr,
396
397 .ioapic_phys_id_map = NULL,
398 .setup_apic_routing = NULL,
399 .cpu_present_to_apicid = default_cpu_present_to_apicid,
400 .apicid_to_cpu_present = NULL,
401 .check_phys_apicid_present = default_check_phys_apicid_present,
402 .phys_pkg_id = uv_phys_pkg_id,
403
404 .get_apic_id = x2apic_get_apic_id,
405 .set_apic_id = set_apic_id,
406 .apic_id_mask = 0xFFFFFFFFu,
407
408 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
409
410 .send_IPI_mask = uv_send_IPI_mask,
411 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
412 .send_IPI_allbutself = uv_send_IPI_allbutself,
413 .send_IPI_all = uv_send_IPI_all,
414 .send_IPI_self = uv_send_IPI_self,
415
416 .wakeup_secondary_cpu = uv_wakeup_secondary,
417 .wait_for_init_deassert = false,
418 .inquire_remote_apic = NULL,
419
420 .read = native_apic_msr_read,
421 .write = native_apic_msr_write,
422 .eoi_write = native_apic_msr_eoi_write,
423 .icr_read = native_x2apic_icr_read,
424 .icr_write = native_x2apic_icr_write,
425 .wait_icr_idle = native_x2apic_wait_icr_idle,
426 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
427 };
428
429 static void set_x2apic_extra_bits(int pnode)
430 {
431 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
432 }
433
434 /*
435 * Called on boot cpu.
436 */
437 static __init int boot_pnode_to_blade(int pnode)
438 {
439 int blade;
440
441 for (blade = 0; blade < uv_num_possible_blades(); blade++)
442 if (pnode == uv_blade_info[blade].pnode)
443 return blade;
444 BUG();
445 }
446
447 struct redir_addr {
448 unsigned long redirect;
449 unsigned long alias;
450 };
451
452 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
453
454 static __initdata struct redir_addr redir_addrs[] = {
455 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
456 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
457 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
458 };
459
460 static unsigned char get_n_lshift(int m_val)
461 {
462 union uv3h_gr0_gam_gr_config_u m_gr_config;
463
464 if (is_uv1_hub())
465 return m_val;
466
467 if (is_uv2_hub())
468 return m_val == 40 ? 40 : 39;
469
470 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
471 return m_gr_config.s3.m_skt;
472 }
473
474 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
475 {
476 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
477 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
478 int i;
479
480 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
481 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
482 if (alias.s.enable && alias.s.base == 0) {
483 *size = (1UL << alias.s.m_alias);
484 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
485 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
486 return;
487 }
488 }
489 *base = *size = 0;
490 }
491
492 enum map_type {map_wb, map_uc};
493
494 static __init void map_high(char *id, unsigned long base, int pshift,
495 int bshift, int max_pnode, enum map_type map_type)
496 {
497 unsigned long bytes, paddr;
498
499 paddr = base << pshift;
500 bytes = (1UL << bshift) * (max_pnode + 1);
501 if (!paddr) {
502 pr_info("UV: Map %s_HI base address NULL\n", id);
503 return;
504 }
505 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
506 if (map_type == map_uc)
507 init_extra_mapping_uc(paddr, bytes);
508 else
509 init_extra_mapping_wb(paddr, bytes);
510 }
511
512 static __init void map_gru_distributed(unsigned long c)
513 {
514 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
515 u64 paddr;
516 unsigned long bytes;
517 int nid;
518
519 gru.v = c;
520 /* only base bits 42:28 relevant in dist mode */
521 gru_dist_base = gru.v & 0x000007fff0000000UL;
522 if (!gru_dist_base) {
523 pr_info("UV: Map GRU_DIST base address NULL\n");
524 return;
525 }
526 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
527 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
528 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
529 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
530 for_each_online_node(nid) {
531 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
532 gru_dist_base;
533 init_extra_mapping_wb(paddr, bytes);
534 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
535 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
536 }
537 /* Save upper (63:M) bits of address only for is_GRU_range */
538 gru_first_node_paddr &= gru_dist_umask;
539 gru_last_node_paddr &= gru_dist_umask;
540 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n",
541 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
542 }
543
544 static __init void map_gru_high(int max_pnode)
545 {
546 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
547 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
548
549 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
550 if (!gru.s.enable) {
551 pr_info("UV: GRU disabled\n");
552 return;
553 }
554
555 if (is_uv3_hub() && gru.s3.mode) {
556 map_gru_distributed(gru.v);
557 return;
558 }
559 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
560 gru_start_paddr = ((u64)gru.s.base << shift);
561 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
562 }
563
564 static __init void map_mmr_high(int max_pnode)
565 {
566 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
567 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
568
569 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
570 if (mmr.s.enable)
571 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
572 else
573 pr_info("UV: MMR disabled\n");
574 }
575
576 /*
577 * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
578 * and REDIRECT MMR regs are exactly the same on UV3.
579 */
580 struct mmioh_config {
581 unsigned long overlay;
582 unsigned long redirect;
583 char *id;
584 };
585
586 static __initdata struct mmioh_config mmiohs[] = {
587 {
588 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
589 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
590 "MMIOH0"
591 },
592 {
593 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
594 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
595 "MMIOH1"
596 },
597 };
598
599 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
600 {
601 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
602 unsigned long mmr;
603 unsigned long base;
604 int i, n, shift, m_io, max_io;
605 int nasid, lnasid, fi, li;
606 char *id;
607
608 id = mmiohs[index].id;
609 overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
610 pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
611 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
612 if (!overlay.s3.enable) {
613 pr_info("UV: %s disabled\n", id);
614 return;
615 }
616
617 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
618 base = (unsigned long)overlay.s3.base;
619 m_io = overlay.s3.m_io;
620 mmr = mmiohs[index].redirect;
621 n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
622 min_pnode *= 2; /* convert to NASID */
623 max_pnode *= 2;
624 max_io = lnasid = fi = li = -1;
625
626 for (i = 0; i < n; i++) {
627 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
628
629 redirect.v = uv_read_local_mmr(mmr + i * 8);
630 nasid = redirect.s3.nasid;
631 if (nasid < min_pnode || max_pnode < nasid)
632 nasid = -1; /* invalid NASID */
633
634 if (nasid == lnasid) {
635 li = i;
636 if (i != n-1) /* last entry check */
637 continue;
638 }
639
640 /* check if we have a cached (or last) redirect to print */
641 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
642 unsigned long addr1, addr2;
643 int f, l;
644
645 if (lnasid == -1) {
646 f = l = i;
647 lnasid = nasid;
648 } else {
649 f = fi;
650 l = li;
651 }
652 addr1 = (base << shift) +
653 f * (unsigned long)(1 << m_io);
654 addr2 = (base << shift) +
655 (l + 1) * (unsigned long)(1 << m_io);
656 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
657 id, fi, li, lnasid, addr1, addr2);
658 if (max_io < l)
659 max_io = l;
660 }
661 fi = li = i;
662 lnasid = nasid;
663 }
664
665 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
666 id, base, shift, m_io, max_io);
667
668 if (max_io >= 0)
669 map_high(id, base, shift, m_io, max_io, map_uc);
670 }
671
672 static __init void map_mmioh_high(int min_pnode, int max_pnode)
673 {
674 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
675 unsigned long mmr, base;
676 int shift, enable, m_io, n_io;
677
678 if (is_uv3_hub()) {
679 /* Map both MMIOH Regions */
680 map_mmioh_high_uv3(0, min_pnode, max_pnode);
681 map_mmioh_high_uv3(1, min_pnode, max_pnode);
682 return;
683 }
684
685 if (is_uv1_hub()) {
686 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
687 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
688 mmioh.v = uv_read_local_mmr(mmr);
689 enable = !!mmioh.s1.enable;
690 base = mmioh.s1.base;
691 m_io = mmioh.s1.m_io;
692 n_io = mmioh.s1.n_io;
693 } else if (is_uv2_hub()) {
694 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
695 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
696 mmioh.v = uv_read_local_mmr(mmr);
697 enable = !!mmioh.s2.enable;
698 base = mmioh.s2.base;
699 m_io = mmioh.s2.m_io;
700 n_io = mmioh.s2.n_io;
701 } else
702 return;
703
704 if (enable) {
705 max_pnode &= (1 << n_io) - 1;
706 pr_info(
707 "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
708 base, shift, m_io, n_io, max_pnode);
709 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
710 } else {
711 pr_info("UV: MMIOH disabled\n");
712 }
713 }
714
715 static __init void map_low_mmrs(void)
716 {
717 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
718 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
719 }
720
721 static __init void uv_rtc_init(void)
722 {
723 long status;
724 u64 ticks_per_sec;
725
726 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
727 &ticks_per_sec);
728 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
729 printk(KERN_WARNING
730 "unable to determine platform RTC clock frequency, "
731 "guessing.\n");
732 /* BIOS gives wrong value for clock freq. so guess */
733 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
734 } else
735 sn_rtc_cycles_per_second = ticks_per_sec;
736 }
737
738 /*
739 * percpu heartbeat timer
740 */
741 static void uv_heartbeat(unsigned long ignored)
742 {
743 struct timer_list *timer = &uv_hub_info->scir.timer;
744 unsigned char bits = uv_hub_info->scir.state;
745
746 /* flip heartbeat bit */
747 bits ^= SCIR_CPU_HEARTBEAT;
748
749 /* is this cpu idle? */
750 if (idle_cpu(raw_smp_processor_id()))
751 bits &= ~SCIR_CPU_ACTIVITY;
752 else
753 bits |= SCIR_CPU_ACTIVITY;
754
755 /* update system controller interface reg */
756 uv_set_scir_bits(bits);
757
758 /* enable next timer period */
759 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
760 }
761
762 static void uv_heartbeat_enable(int cpu)
763 {
764 while (!uv_cpu_hub_info(cpu)->scir.enabled) {
765 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
766
767 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
768 setup_timer(timer, uv_heartbeat, cpu);
769 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
770 add_timer_on(timer, cpu);
771 uv_cpu_hub_info(cpu)->scir.enabled = 1;
772
773 /* also ensure that boot cpu is enabled */
774 cpu = 0;
775 }
776 }
777
778 #ifdef CONFIG_HOTPLUG_CPU
779 static void uv_heartbeat_disable(int cpu)
780 {
781 if (uv_cpu_hub_info(cpu)->scir.enabled) {
782 uv_cpu_hub_info(cpu)->scir.enabled = 0;
783 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
784 }
785 uv_set_cpu_scir_bits(cpu, 0xff);
786 }
787
788 /*
789 * cpu hotplug notifier
790 */
791 static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
792 void *hcpu)
793 {
794 long cpu = (long)hcpu;
795
796 switch (action) {
797 case CPU_ONLINE:
798 uv_heartbeat_enable(cpu);
799 break;
800 case CPU_DOWN_PREPARE:
801 uv_heartbeat_disable(cpu);
802 break;
803 default:
804 break;
805 }
806 return NOTIFY_OK;
807 }
808
809 static __init void uv_scir_register_cpu_notifier(void)
810 {
811 hotcpu_notifier(uv_scir_cpu_notify, 0);
812 }
813
814 #else /* !CONFIG_HOTPLUG_CPU */
815
816 static __init void uv_scir_register_cpu_notifier(void)
817 {
818 }
819
820 static __init int uv_init_heartbeat(void)
821 {
822 int cpu;
823
824 if (is_uv_system())
825 for_each_online_cpu(cpu)
826 uv_heartbeat_enable(cpu);
827 return 0;
828 }
829
830 late_initcall(uv_init_heartbeat);
831
832 #endif /* !CONFIG_HOTPLUG_CPU */
833
834 /* Direct Legacy VGA I/O traffic to designated IOH */
835 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
836 unsigned int command_bits, u32 flags)
837 {
838 int domain, bus, rc;
839
840 PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
841 pdev->devfn, decode, command_bits, flags);
842
843 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
844 return 0;
845
846 if ((command_bits & PCI_COMMAND_IO) == 0)
847 return 0;
848
849 domain = pci_domain_nr(pdev->bus);
850 bus = pdev->bus->number;
851
852 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
853 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
854
855 return rc;
856 }
857
858 /*
859 * Called on each cpu to initialize the per_cpu UV data area.
860 * FIXME: hotplug not supported yet
861 */
862 void uv_cpu_init(void)
863 {
864 /* CPU 0 initilization will be done via uv_system_init. */
865 if (!uv_blade_info)
866 return;
867
868 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
869
870 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
871 set_x2apic_extra_bits(uv_hub_info->pnode);
872 }
873
874 void __init uv_system_init(void)
875 {
876 union uvh_rh_gam_config_mmr_u m_n_config;
877 union uvh_node_id_u node_id;
878 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
879 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
880 int gnode_extra, min_pnode = 999999, max_pnode = -1;
881 unsigned long mmr_base, present, paddr;
882 unsigned short pnode_mask;
883 unsigned char n_lshift;
884 char *hub = (is_uv1_hub() ? "UV100/1000" :
885 (is_uv2_hub() ? "UV2000/3000" :
886 (is_uv3_hub() ? "UV300" : NULL)));
887
888 if (!hub) {
889 pr_err("UV: Unknown/unsupported UV hub\n");
890 return;
891 }
892 pr_info("UV: Found %s hub\n", hub);
893 map_low_mmrs();
894
895 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
896 m_val = m_n_config.s.m_skt;
897 n_val = m_n_config.s.n_skt;
898 pnode_mask = (1 << n_val) - 1;
899 n_lshift = get_n_lshift(m_val);
900 mmr_base =
901 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
902 ~UV_MMR_ENABLE;
903
904 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
905 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
906 gnode_upper = ((unsigned long)gnode_extra << m_val);
907 pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n",
908 n_val, m_val, pnode_mask, gnode_upper, gnode_extra,
909 n_lshift);
910
911 pr_info("UV: global MMR base 0x%lx\n", mmr_base);
912
913 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
914 uv_possible_blades +=
915 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
916
917 /* uv_num_possible_blades() is really the hub count */
918 pr_info("UV: Found %d blades, %d hubs\n",
919 is_uv1_hub() ? uv_num_possible_blades() :
920 (uv_num_possible_blades() + 1) / 2,
921 uv_num_possible_blades());
922
923 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
924 uv_blade_info = kzalloc(bytes, GFP_KERNEL);
925 BUG_ON(!uv_blade_info);
926
927 for (blade = 0; blade < uv_num_possible_blades(); blade++)
928 uv_blade_info[blade].memory_nid = -1;
929
930 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
931
932 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
933 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
934 BUG_ON(!uv_node_to_blade);
935 memset(uv_node_to_blade, 255, bytes);
936
937 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
938 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
939 BUG_ON(!uv_cpu_to_blade);
940 memset(uv_cpu_to_blade, 255, bytes);
941
942 blade = 0;
943 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
944 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
945 for (j = 0; j < 64; j++) {
946 if (!test_bit(j, &present))
947 continue;
948 pnode = (i * 64 + j) & pnode_mask;
949 uv_blade_info[blade].pnode = pnode;
950 uv_blade_info[blade].nr_possible_cpus = 0;
951 uv_blade_info[blade].nr_online_cpus = 0;
952 spin_lock_init(&uv_blade_info[blade].nmi_lock);
953 min_pnode = min(pnode, min_pnode);
954 max_pnode = max(pnode, max_pnode);
955 blade++;
956 }
957 }
958
959 uv_bios_init();
960 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
961 &sn_region_size, &system_serial_number);
962 uv_rtc_init();
963
964 for_each_present_cpu(cpu) {
965 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
966
967 nid = cpu_to_node(cpu);
968 /*
969 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
970 */
971 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
972 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
973 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
974
975 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
976 uv_cpu_hub_info(cpu)->n_lshift = n_lshift;
977
978 pnode = uv_apicid_to_pnode(apicid);
979 blade = boot_pnode_to_blade(pnode);
980 lcpu = uv_blade_info[blade].nr_possible_cpus;
981 uv_blade_info[blade].nr_possible_cpus++;
982
983 /* Any node on the blade, else will contain -1. */
984 uv_blade_info[blade].memory_nid = nid;
985
986 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
987 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
988 uv_cpu_hub_info(cpu)->m_val = m_val;
989 uv_cpu_hub_info(cpu)->n_val = n_val;
990 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
991 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
992 uv_cpu_hub_info(cpu)->pnode = pnode;
993 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
994 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
995 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
996 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
997 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
998 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
999 uv_node_to_blade[nid] = blade;
1000 uv_cpu_to_blade[cpu] = blade;
1001 }
1002
1003 /* Add blade/pnode info for nodes without cpus */
1004 for_each_online_node(nid) {
1005 if (uv_node_to_blade[nid] >= 0)
1006 continue;
1007 paddr = node_start_pfn(nid) << PAGE_SHIFT;
1008 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1009 blade = boot_pnode_to_blade(pnode);
1010 uv_node_to_blade[nid] = blade;
1011 }
1012
1013 map_gru_high(max_pnode);
1014 map_mmr_high(max_pnode);
1015 map_mmioh_high(min_pnode, max_pnode);
1016
1017 uv_nmi_setup();
1018 uv_cpu_init();
1019 uv_scir_register_cpu_notifier();
1020 proc_mkdir("sgi_uv", NULL);
1021
1022 /* register Legacy VGA I/O redirection handler */
1023 pci_register_set_vga_state(uv_set_vga_state);
1024
1025 /*
1026 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1027 * EFI is not enabled in the kdump kernel.
1028 */
1029 if (is_kdump_kernel())
1030 reboot_type = BOOT_ACPI;
1031 }
1032
1033 apic_driver(apic_x2apic_uv_x);
Linux with added FPC-III support