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Linux 4.1.18
[linux/fpc-iii.git] / arch / x86 / kvm / lapic.c
blob7dd9a8d3911ae22fe12b105fe279fd6844b11f70
1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
23 #include <linux/mm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
32 #include <asm/msr.h>
33 #include <asm/page.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
40 #include "irq.h"
41 #include "trace.h"
42 #include "x86.h"
43 #include "cpuid.h"
44
45 #ifndef CONFIG_X86_64
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #else
48 #define mod_64(x, y) ((x) % (y))
49 #endif
50
51 #define PRId64 "d"
52 #define PRIx64 "llx"
53 #define PRIu64 "u"
54 #define PRIo64 "o"
55
56 #define APIC_BUS_CYCLE_NS 1
57
58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59 #define apic_debug(fmt, arg...)
60
61 #define APIC_LVT_NUM 6
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
71
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
74
75 #define VEC_POS(v) ((v) & (32 - 1))
76 #define REG_POS(v) (((v) >> 5) << 4)
77
78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79 {
80 *((u32 *) (apic->regs + reg_off)) = val;
81 }
82
83 static inline int apic_test_vector(int vec, void *bitmap)
84 {
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86 }
87
88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89 {
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94 }
95
96 static inline void apic_set_vector(int vec, void *bitmap)
97 {
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99 }
100
101 static inline void apic_clear_vector(int vec, void *bitmap)
102 {
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104 }
105
106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107 {
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109 }
110
111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112 {
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114 }
115
116 struct static_key_deferred apic_hw_disabled __read_mostly;
117 struct static_key_deferred apic_sw_disabled __read_mostly;
118
119 static inline int apic_enabled(struct kvm_lapic *apic)
120 {
121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
122 }
123
124 #define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127 #define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131 static inline int kvm_apic_id(struct kvm_lapic *apic)
132 {
133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
134 }
135
136 /* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
138 */
139 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
140 {
141 return !(map->mode & (map->mode - 1));
142 }
143
144 static inline void
145 apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
146 {
147 unsigned lid_bits;
148
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
153
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
156 }
157
158 static void recalculate_apic_map(struct kvm *kvm)
159 {
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
162 int i;
163
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
165
166 mutex_lock(&kvm->arch.apic_map_lock);
167
168 if (!new)
169 goto out;
170
171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
173 u16 cid, lid;
174 u32 ldr, aid;
175
176 if (!kvm_apic_present(vcpu))
177 continue;
178
179 aid = kvm_apic_id(apic);
180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
181
182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
184
185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
187 } else if (ldr) {
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
191 else
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
193 }
194
195 if (!kvm_apic_logical_map_valid(new))
196 continue;
197
198 apic_logical_id(new, ldr, &cid, &lid);
199
200 if (lid && cid < ARRAY_SIZE(new->logical_map))
201 new->logical_map[cid][ffs(lid) - 1] = apic;
202 }
203 out:
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
208
209 if (old)
210 kfree_rcu(old, rcu);
211
212 kvm_vcpu_request_scan_ioapic(kvm);
213 }
214
215 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
216 {
217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
218
219 apic_set_reg(apic, APIC_SPIV, val);
220
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
223 if (enabled) {
224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
226 } else
227 static_key_slow_inc(&apic_sw_disabled.key);
228 }
229 }
230
231 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
232 {
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
235 }
236
237 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
238 {
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
241 }
242
243 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
244 {
245 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
246 }
247
248 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
249 {
250 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
251 }
252
253 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
254 {
255 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
256 }
257
258 static inline int apic_lvtt_period(struct kvm_lapic *apic)
259 {
260 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
261 }
262
263 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
264 {
265 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
266 }
267
268 static inline int apic_lvt_nmi_mode(u32 lvt_val)
269 {
270 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
271 }
272
273 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
274 {
275 struct kvm_lapic *apic = vcpu->arch.apic;
276 struct kvm_cpuid_entry2 *feat;
277 u32 v = APIC_VERSION;
278
279 if (!kvm_vcpu_has_lapic(vcpu))
280 return;
281
282 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
283 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
284 v |= APIC_LVR_DIRECTED_EOI;
285 apic_set_reg(apic, APIC_LVR, v);
286 }
287
288 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
289 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
290 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
291 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
292 LINT_MASK, LINT_MASK, /* LVT0-1 */
293 LVT_MASK /* LVTERR */
294 };
295
296 static int find_highest_vector(void *bitmap)
297 {
298 int vec;
299 u32 *reg;
300
301 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
302 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
303 reg = bitmap + REG_POS(vec);
304 if (*reg)
305 return fls(*reg) - 1 + vec;
306 }
307
308 return -1;
309 }
310
311 static u8 count_vectors(void *bitmap)
312 {
313 int vec;
314 u32 *reg;
315 u8 count = 0;
316
317 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
318 reg = bitmap + REG_POS(vec);
319 count += hweight32(*reg);
320 }
321
322 return count;
323 }
324
325 void __kvm_apic_update_irr(u32 *pir, void *regs)
326 {
327 u32 i, pir_val;
328
329 for (i = 0; i <= 7; i++) {
330 pir_val = xchg(&pir[i], 0);
331 if (pir_val)
332 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
333 }
334 }
335 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
336
337 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
338 {
339 struct kvm_lapic *apic = vcpu->arch.apic;
340
341 __kvm_apic_update_irr(pir, apic->regs);
342
343 kvm_make_request(KVM_REQ_EVENT, vcpu);
344 }
345 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
346
347 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
348 {
349 apic_set_vector(vec, apic->regs + APIC_IRR);
350 /*
351 * irr_pending must be true if any interrupt is pending; set it after
352 * APIC_IRR to avoid race with apic_clear_irr
353 */
354 apic->irr_pending = true;
355 }
356
357 static inline int apic_search_irr(struct kvm_lapic *apic)
358 {
359 return find_highest_vector(apic->regs + APIC_IRR);
360 }
361
362 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
363 {
364 int result;
365
366 /*
367 * Note that irr_pending is just a hint. It will be always
368 * true with virtual interrupt delivery enabled.
369 */
370 if (!apic->irr_pending)
371 return -1;
372
373 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
374 result = apic_search_irr(apic);
375 ASSERT(result == -1 || result >= 16);
376
377 return result;
378 }
379
380 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
381 {
382 struct kvm_vcpu *vcpu;
383
384 vcpu = apic->vcpu;
385
386 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
387 /* try to update RVI */
388 apic_clear_vector(vec, apic->regs + APIC_IRR);
389 kvm_make_request(KVM_REQ_EVENT, vcpu);
390 } else {
391 apic->irr_pending = false;
392 apic_clear_vector(vec, apic->regs + APIC_IRR);
393 if (apic_search_irr(apic) != -1)
394 apic->irr_pending = true;
395 }
396 }
397
398 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
399 {
400 struct kvm_vcpu *vcpu;
401
402 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
403 return;
404
405 vcpu = apic->vcpu;
406
407 /*
408 * With APIC virtualization enabled, all caching is disabled
409 * because the processor can modify ISR under the hood. Instead
410 * just set SVI.
411 */
412 if (unlikely(kvm_x86_ops->hwapic_isr_update))
413 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
414 else {
415 ++apic->isr_count;
416 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
417 /*
418 * ISR (in service register) bit is set when injecting an interrupt.
419 * The highest vector is injected. Thus the latest bit set matches
420 * the highest bit in ISR.
421 */
422 apic->highest_isr_cache = vec;
423 }
424 }
425
426 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
427 {
428 int result;
429
430 /*
431 * Note that isr_count is always 1, and highest_isr_cache
432 * is always -1, with APIC virtualization enabled.
433 */
434 if (!apic->isr_count)
435 return -1;
436 if (likely(apic->highest_isr_cache != -1))
437 return apic->highest_isr_cache;
438
439 result = find_highest_vector(apic->regs + APIC_ISR);
440 ASSERT(result == -1 || result >= 16);
441
442 return result;
443 }
444
445 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
446 {
447 struct kvm_vcpu *vcpu;
448 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
449 return;
450
451 vcpu = apic->vcpu;
452
453 /*
454 * We do get here for APIC virtualization enabled if the guest
455 * uses the Hyper-V APIC enlightenment. In this case we may need
456 * to trigger a new interrupt delivery by writing the SVI field;
457 * on the other hand isr_count and highest_isr_cache are unused
458 * and must be left alone.
459 */
460 if (unlikely(kvm_x86_ops->hwapic_isr_update))
461 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
462 apic_find_highest_isr(apic));
463 else {
464 --apic->isr_count;
465 BUG_ON(apic->isr_count < 0);
466 apic->highest_isr_cache = -1;
467 }
468 }
469
470 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
471 {
472 int highest_irr;
473
474 /* This may race with setting of irr in __apic_accept_irq() and
475 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
476 * will cause vmexit immediately and the value will be recalculated
477 * on the next vmentry.
478 */
479 if (!kvm_vcpu_has_lapic(vcpu))
480 return 0;
481 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
482
483 return highest_irr;
484 }
485
486 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
487 int vector, int level, int trig_mode,
488 unsigned long *dest_map);
489
490 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
491 unsigned long *dest_map)
492 {
493 struct kvm_lapic *apic = vcpu->arch.apic;
494
495 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
496 irq->level, irq->trig_mode, dest_map);
497 }
498
499 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
500 {
501
502 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
503 sizeof(val));
504 }
505
506 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
507 {
508
509 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
510 sizeof(*val));
511 }
512
513 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
514 {
515 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
516 }
517
518 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
519 {
520 u8 val;
521 if (pv_eoi_get_user(vcpu, &val) < 0)
522 apic_debug("Can't read EOI MSR value: 0x%llx\n",
523 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
524 return val & 0x1;
525 }
526
527 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
528 {
529 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
530 apic_debug("Can't set EOI MSR value: 0x%llx\n",
531 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
532 return;
533 }
534 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
535 }
536
537 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
538 {
539 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
540 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
541 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
542 return;
543 }
544 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
545 }
546
547 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
548 {
549 struct kvm_lapic *apic = vcpu->arch.apic;
550 int i;
551
552 for (i = 0; i < 8; i++)
553 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
554 }
555
556 static void apic_update_ppr(struct kvm_lapic *apic)
557 {
558 u32 tpr, isrv, ppr, old_ppr;
559 int isr;
560
561 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
562 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
563 isr = apic_find_highest_isr(apic);
564 isrv = (isr != -1) ? isr : 0;
565
566 if ((tpr & 0xf0) >= (isrv & 0xf0))
567 ppr = tpr & 0xff;
568 else
569 ppr = isrv & 0xf0;
570
571 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
572 apic, ppr, isr, isrv);
573
574 if (old_ppr != ppr) {
575 apic_set_reg(apic, APIC_PROCPRI, ppr);
576 if (ppr < old_ppr)
577 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
578 }
579 }
580
581 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
582 {
583 apic_set_reg(apic, APIC_TASKPRI, tpr);
584 apic_update_ppr(apic);
585 }
586
587 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
588 {
589 if (apic_x2apic_mode(apic))
590 return mda == X2APIC_BROADCAST;
591
592 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
593 }
594
595 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
596 {
597 if (kvm_apic_broadcast(apic, mda))
598 return true;
599
600 if (apic_x2apic_mode(apic))
601 return mda == kvm_apic_id(apic);
602
603 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
604 }
605
606 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
607 {
608 u32 logical_id;
609
610 if (kvm_apic_broadcast(apic, mda))
611 return true;
612
613 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
614
615 if (apic_x2apic_mode(apic))
616 return ((logical_id >> 16) == (mda >> 16))
617 && (logical_id & mda & 0xffff) != 0;
618
619 logical_id = GET_APIC_LOGICAL_ID(logical_id);
620 mda = GET_APIC_DEST_FIELD(mda);
621
622 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
623 case APIC_DFR_FLAT:
624 return (logical_id & mda) != 0;
625 case APIC_DFR_CLUSTER:
626 return ((logical_id >> 4) == (mda >> 4))
627 && (logical_id & mda & 0xf) != 0;
628 default:
629 apic_debug("Bad DFR vcpu %d: %08x\n",
630 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
631 return false;
632 }
633 }
634
635 /* KVM APIC implementation has two quirks
636 * - dest always begins at 0 while xAPIC MDA has offset 24,
637 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
638 */
639 static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
640 struct kvm_lapic *target)
641 {
642 bool ipi = source != NULL;
643 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
644
645 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
646 return X2APIC_BROADCAST;
647
648 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
649 }
650
651 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
652 int short_hand, unsigned int dest, int dest_mode)
653 {
654 struct kvm_lapic *target = vcpu->arch.apic;
655 u32 mda = kvm_apic_mda(dest, source, target);
656
657 apic_debug("target %p, source %p, dest 0x%x, "
658 "dest_mode 0x%x, short_hand 0x%x\n",
659 target, source, dest, dest_mode, short_hand);
660
661 ASSERT(target);
662 switch (short_hand) {
663 case APIC_DEST_NOSHORT:
664 if (dest_mode == APIC_DEST_PHYSICAL)
665 return kvm_apic_match_physical_addr(target, mda);
666 else
667 return kvm_apic_match_logical_addr(target, mda);
668 case APIC_DEST_SELF:
669 return target == source;
670 case APIC_DEST_ALLINC:
671 return true;
672 case APIC_DEST_ALLBUT:
673 return target != source;
674 default:
675 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
676 short_hand);
677 return false;
678 }
679 }
680
681 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
682 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
683 {
684 struct kvm_apic_map *map;
685 unsigned long bitmap = 1;
686 struct kvm_lapic **dst;
687 int i;
688 bool ret, x2apic_ipi;
689
690 *r = -1;
691
692 if (irq->shorthand == APIC_DEST_SELF) {
693 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
694 return true;
695 }
696
697 if (irq->shorthand)
698 return false;
699
700 x2apic_ipi = src && apic_x2apic_mode(src);
701 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
702 return false;
703
704 ret = true;
705 rcu_read_lock();
706 map = rcu_dereference(kvm->arch.apic_map);
707
708 if (!map) {
709 ret = false;
710 goto out;
711 }
712
713 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
714 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
715 goto out;
716
717 dst = &map->phys_map[irq->dest_id];
718 } else {
719 u16 cid;
720
721 if (!kvm_apic_logical_map_valid(map)) {
722 ret = false;
723 goto out;
724 }
725
726 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
727
728 if (cid >= ARRAY_SIZE(map->logical_map))
729 goto out;
730
731 dst = map->logical_map[cid];
732
733 if (irq->delivery_mode == APIC_DM_LOWEST) {
734 int l = -1;
735 for_each_set_bit(i, &bitmap, 16) {
736 if (!dst[i])
737 continue;
738 if (l < 0)
739 l = i;
740 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
741 l = i;
742 }
743
744 bitmap = (l >= 0) ? 1 << l : 0;
745 }
746 }
747
748 for_each_set_bit(i, &bitmap, 16) {
749 if (!dst[i])
750 continue;
751 if (*r < 0)
752 *r = 0;
753 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
754 }
755 out:
756 rcu_read_unlock();
757 return ret;
758 }
759
760 /*
761 * Add a pending IRQ into lapic.
762 * Return 1 if successfully added and 0 if discarded.
763 */
764 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
765 int vector, int level, int trig_mode,
766 unsigned long *dest_map)
767 {
768 int result = 0;
769 struct kvm_vcpu *vcpu = apic->vcpu;
770
771 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
772 trig_mode, vector);
773 switch (delivery_mode) {
774 case APIC_DM_LOWEST:
775 vcpu->arch.apic_arb_prio++;
776 case APIC_DM_FIXED:
777 /* FIXME add logic for vcpu on reset */
778 if (unlikely(!apic_enabled(apic)))
779 break;
780
781 result = 1;
782
783 if (dest_map)
784 __set_bit(vcpu->vcpu_id, dest_map);
785
786 if (kvm_x86_ops->deliver_posted_interrupt)
787 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
788 else {
789 apic_set_irr(vector, apic);
790
791 kvm_make_request(KVM_REQ_EVENT, vcpu);
792 kvm_vcpu_kick(vcpu);
793 }
794 break;
795
796 case APIC_DM_REMRD:
797 result = 1;
798 vcpu->arch.pv.pv_unhalted = 1;
799 kvm_make_request(KVM_REQ_EVENT, vcpu);
800 kvm_vcpu_kick(vcpu);
801 break;
802
803 case APIC_DM_SMI:
804 apic_debug("Ignoring guest SMI\n");
805 break;
806
807 case APIC_DM_NMI:
808 result = 1;
809 kvm_inject_nmi(vcpu);
810 kvm_vcpu_kick(vcpu);
811 break;
812
813 case APIC_DM_INIT:
814 if (!trig_mode || level) {
815 result = 1;
816 /* assumes that there are only KVM_APIC_INIT/SIPI */
817 apic->pending_events = (1UL << KVM_APIC_INIT);
818 /* make sure pending_events is visible before sending
819 * the request */
820 smp_wmb();
821 kvm_make_request(KVM_REQ_EVENT, vcpu);
822 kvm_vcpu_kick(vcpu);
823 } else {
824 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
825 vcpu->vcpu_id);
826 }
827 break;
828
829 case APIC_DM_STARTUP:
830 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
831 vcpu->vcpu_id, vector);
832 result = 1;
833 apic->sipi_vector = vector;
834 /* make sure sipi_vector is visible for the receiver */
835 smp_wmb();
836 set_bit(KVM_APIC_SIPI, &apic->pending_events);
837 kvm_make_request(KVM_REQ_EVENT, vcpu);
838 kvm_vcpu_kick(vcpu);
839 break;
840
841 case APIC_DM_EXTINT:
842 /*
843 * Should only be called by kvm_apic_local_deliver() with LVT0,
844 * before NMI watchdog was enabled. Already handled by
845 * kvm_apic_accept_pic_intr().
846 */
847 break;
848
849 default:
850 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
851 delivery_mode);
852 break;
853 }
854 return result;
855 }
856
857 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
858 {
859 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
860 }
861
862 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
863 {
864 if (kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
865 int trigger_mode;
866 if (apic_test_vector(vector, apic->regs + APIC_TMR))
867 trigger_mode = IOAPIC_LEVEL_TRIG;
868 else
869 trigger_mode = IOAPIC_EDGE_TRIG;
870 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
871 }
872 }
873
874 static int apic_set_eoi(struct kvm_lapic *apic)
875 {
876 int vector = apic_find_highest_isr(apic);
877
878 trace_kvm_eoi(apic, vector);
879
880 /*
881 * Not every write EOI will has corresponding ISR,
882 * one example is when Kernel check timer on setup_IO_APIC
883 */
884 if (vector == -1)
885 return vector;
886
887 apic_clear_isr(vector, apic);
888 apic_update_ppr(apic);
889
890 kvm_ioapic_send_eoi(apic, vector);
891 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
892 return vector;
893 }
894
895 /*
896 * this interface assumes a trap-like exit, which has already finished
897 * desired side effect including vISR and vPPR update.
898 */
899 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
900 {
901 struct kvm_lapic *apic = vcpu->arch.apic;
902
903 trace_kvm_eoi(apic, vector);
904
905 kvm_ioapic_send_eoi(apic, vector);
906 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
907 }
908 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
909
910 static void apic_send_ipi(struct kvm_lapic *apic)
911 {
912 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
913 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
914 struct kvm_lapic_irq irq;
915
916 irq.vector = icr_low & APIC_VECTOR_MASK;
917 irq.delivery_mode = icr_low & APIC_MODE_MASK;
918 irq.dest_mode = icr_low & APIC_DEST_MASK;
919 irq.level = icr_low & APIC_INT_ASSERT;
920 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
921 irq.shorthand = icr_low & APIC_SHORT_MASK;
922 if (apic_x2apic_mode(apic))
923 irq.dest_id = icr_high;
924 else
925 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
926
927 trace_kvm_apic_ipi(icr_low, irq.dest_id);
928
929 apic_debug("icr_high 0x%x, icr_low 0x%x, "
930 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
931 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
932 icr_high, icr_low, irq.shorthand, irq.dest_id,
933 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
934 irq.vector);
935
936 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
937 }
938
939 static u32 apic_get_tmcct(struct kvm_lapic *apic)
940 {
941 ktime_t remaining;
942 s64 ns;
943 u32 tmcct;
944
945 ASSERT(apic != NULL);
946
947 /* if initial count is 0, current count should also be 0 */
948 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
949 apic->lapic_timer.period == 0)
950 return 0;
951
952 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
953 if (ktime_to_ns(remaining) < 0)
954 remaining = ktime_set(0, 0);
955
956 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
957 tmcct = div64_u64(ns,
958 (APIC_BUS_CYCLE_NS * apic->divide_count));
959
960 return tmcct;
961 }
962
963 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
964 {
965 struct kvm_vcpu *vcpu = apic->vcpu;
966 struct kvm_run *run = vcpu->run;
967
968 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
969 run->tpr_access.rip = kvm_rip_read(vcpu);
970 run->tpr_access.is_write = write;
971 }
972
973 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
974 {
975 if (apic->vcpu->arch.tpr_access_reporting)
976 __report_tpr_access(apic, write);
977 }
978
979 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
980 {
981 u32 val = 0;
982
983 if (offset >= LAPIC_MMIO_LENGTH)
984 return 0;
985
986 switch (offset) {
987 case APIC_ID:
988 if (apic_x2apic_mode(apic))
989 val = kvm_apic_id(apic);
990 else
991 val = kvm_apic_id(apic) << 24;
992 break;
993 case APIC_ARBPRI:
994 apic_debug("Access APIC ARBPRI register which is for P6\n");
995 break;
996
997 case APIC_TMCCT: /* Timer CCR */
998 if (apic_lvtt_tscdeadline(apic))
999 return 0;
1000
1001 val = apic_get_tmcct(apic);
1002 break;
1003 case APIC_PROCPRI:
1004 apic_update_ppr(apic);
1005 val = kvm_apic_get_reg(apic, offset);
1006 break;
1007 case APIC_TASKPRI:
1008 report_tpr_access(apic, false);
1009 /* fall thru */
1010 default:
1011 val = kvm_apic_get_reg(apic, offset);
1012 break;
1013 }
1014
1015 return val;
1016 }
1017
1018 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1019 {
1020 return container_of(dev, struct kvm_lapic, dev);
1021 }
1022
1023 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1024 void *data)
1025 {
1026 unsigned char alignment = offset & 0xf;
1027 u32 result;
1028 /* this bitmask has a bit cleared for each reserved register */
1029 static const u64 rmask = 0x43ff01ffffffe70cULL;
1030
1031 if ((alignment + len) > 4) {
1032 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1033 offset, len);
1034 return 1;
1035 }
1036
1037 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1038 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1039 offset);
1040 return 1;
1041 }
1042
1043 result = __apic_read(apic, offset & ~0xf);
1044
1045 trace_kvm_apic_read(offset, result);
1046
1047 switch (len) {
1048 case 1:
1049 case 2:
1050 case 4:
1051 memcpy(data, (char *)&result + alignment, len);
1052 break;
1053 default:
1054 printk(KERN_ERR "Local APIC read with len = %x, "
1055 "should be 1,2, or 4 instead\n", len);
1056 break;
1057 }
1058 return 0;
1059 }
1060
1061 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1062 {
1063 return kvm_apic_hw_enabled(apic) &&
1064 addr >= apic->base_address &&
1065 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1066 }
1067
1068 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1069 gpa_t address, int len, void *data)
1070 {
1071 struct kvm_lapic *apic = to_lapic(this);
1072 u32 offset = address - apic->base_address;
1073
1074 if (!apic_mmio_in_range(apic, address))
1075 return -EOPNOTSUPP;
1076
1077 apic_reg_read(apic, offset, len, data);
1078
1079 return 0;
1080 }
1081
1082 static void update_divide_count(struct kvm_lapic *apic)
1083 {
1084 u32 tmp1, tmp2, tdcr;
1085
1086 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1087 tmp1 = tdcr & 0xf;
1088 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1089 apic->divide_count = 0x1 << (tmp2 & 0x7);
1090
1091 apic_debug("timer divide count is 0x%x\n",
1092 apic->divide_count);
1093 }
1094
1095 static void apic_update_lvtt(struct kvm_lapic *apic)
1096 {
1097 u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1098 apic->lapic_timer.timer_mode_mask;
1099
1100 if (apic->lapic_timer.timer_mode != timer_mode) {
1101 apic->lapic_timer.timer_mode = timer_mode;
1102 hrtimer_cancel(&apic->lapic_timer.timer);
1103 }
1104 }
1105
1106 static void apic_timer_expired(struct kvm_lapic *apic)
1107 {
1108 struct kvm_vcpu *vcpu = apic->vcpu;
1109 wait_queue_head_t *q = &vcpu->wq;
1110 struct kvm_timer *ktimer = &apic->lapic_timer;
1111
1112 if (atomic_read(&apic->lapic_timer.pending))
1113 return;
1114
1115 atomic_inc(&apic->lapic_timer.pending);
1116 kvm_set_pending_timer(vcpu);
1117
1118 if (waitqueue_active(q))
1119 wake_up_interruptible(q);
1120
1121 if (apic_lvtt_tscdeadline(apic))
1122 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1123 }
1124
1125 /*
1126 * On APICv, this test will cause a busy wait
1127 * during a higher-priority task.
1128 */
1129
1130 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1131 {
1132 struct kvm_lapic *apic = vcpu->arch.apic;
1133 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1134
1135 if (kvm_apic_hw_enabled(apic)) {
1136 int vec = reg & APIC_VECTOR_MASK;
1137 void *bitmap = apic->regs + APIC_ISR;
1138
1139 if (kvm_x86_ops->deliver_posted_interrupt)
1140 bitmap = apic->regs + APIC_IRR;
1141
1142 if (apic_test_vector(vec, bitmap))
1143 return true;
1144 }
1145 return false;
1146 }
1147
1148 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1149 {
1150 struct kvm_lapic *apic = vcpu->arch.apic;
1151 u64 guest_tsc, tsc_deadline;
1152
1153 if (!kvm_vcpu_has_lapic(vcpu))
1154 return;
1155
1156 if (apic->lapic_timer.expired_tscdeadline == 0)
1157 return;
1158
1159 if (!lapic_timer_int_injected(vcpu))
1160 return;
1161
1162 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1163 apic->lapic_timer.expired_tscdeadline = 0;
1164 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1165 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1166
1167 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1168 if (guest_tsc < tsc_deadline)
1169 __delay(tsc_deadline - guest_tsc);
1170 }
1171
1172 static void start_apic_timer(struct kvm_lapic *apic)
1173 {
1174 ktime_t now;
1175
1176 atomic_set(&apic->lapic_timer.pending, 0);
1177
1178 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1179 /* lapic timer in oneshot or periodic mode */
1180 now = apic->lapic_timer.timer.base->get_time();
1181 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1182 * APIC_BUS_CYCLE_NS * apic->divide_count;
1183
1184 if (!apic->lapic_timer.period)
1185 return;
1186 /*
1187 * Do not allow the guest to program periodic timers with small
1188 * interval, since the hrtimers are not throttled by the host
1189 * scheduler.
1190 */
1191 if (apic_lvtt_period(apic)) {
1192 s64 min_period = min_timer_period_us * 1000LL;
1193
1194 if (apic->lapic_timer.period < min_period) {
1195 pr_info_ratelimited(
1196 "kvm: vcpu %i: requested %lld ns "
1197 "lapic timer period limited to %lld ns\n",
1198 apic->vcpu->vcpu_id,
1199 apic->lapic_timer.period, min_period);
1200 apic->lapic_timer.period = min_period;
1201 }
1202 }
1203
1204 hrtimer_start(&apic->lapic_timer.timer,
1205 ktime_add_ns(now, apic->lapic_timer.period),
1206 HRTIMER_MODE_ABS);
1207
1208 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1209 PRIx64 ", "
1210 "timer initial count 0x%x, period %lldns, "
1211 "expire @ 0x%016" PRIx64 ".\n", __func__,
1212 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1213 kvm_apic_get_reg(apic, APIC_TMICT),
1214 apic->lapic_timer.period,
1215 ktime_to_ns(ktime_add_ns(now,
1216 apic->lapic_timer.period)));
1217 } else if (apic_lvtt_tscdeadline(apic)) {
1218 /* lapic timer in tsc deadline mode */
1219 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1220 u64 ns = 0;
1221 ktime_t expire;
1222 struct kvm_vcpu *vcpu = apic->vcpu;
1223 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1224 unsigned long flags;
1225
1226 if (unlikely(!tscdeadline || !this_tsc_khz))
1227 return;
1228
1229 local_irq_save(flags);
1230
1231 now = apic->lapic_timer.timer.base->get_time();
1232 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1233 if (likely(tscdeadline > guest_tsc)) {
1234 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1235 do_div(ns, this_tsc_khz);
1236 expire = ktime_add_ns(now, ns);
1237 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1238 hrtimer_start(&apic->lapic_timer.timer,
1239 expire, HRTIMER_MODE_ABS);
1240 } else
1241 apic_timer_expired(apic);
1242
1243 local_irq_restore(flags);
1244 }
1245 }
1246
1247 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1248 {
1249 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1250
1251 if (apic_lvt_nmi_mode(lvt0_val)) {
1252 if (!nmi_wd_enabled) {
1253 apic_debug("Receive NMI setting on APIC_LVT0 "
1254 "for cpu %d\n", apic->vcpu->vcpu_id);
1255 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1256 }
1257 } else if (nmi_wd_enabled)
1258 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1259 }
1260
1261 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1262 {
1263 int ret = 0;
1264
1265 trace_kvm_apic_write(reg, val);
1266
1267 switch (reg) {
1268 case APIC_ID: /* Local APIC ID */
1269 if (!apic_x2apic_mode(apic))
1270 kvm_apic_set_id(apic, val >> 24);
1271 else
1272 ret = 1;
1273 break;
1274
1275 case APIC_TASKPRI:
1276 report_tpr_access(apic, true);
1277 apic_set_tpr(apic, val & 0xff);
1278 break;
1279
1280 case APIC_EOI:
1281 apic_set_eoi(apic);
1282 break;
1283
1284 case APIC_LDR:
1285 if (!apic_x2apic_mode(apic))
1286 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1287 else
1288 ret = 1;
1289 break;
1290
1291 case APIC_DFR:
1292 if (!apic_x2apic_mode(apic)) {
1293 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1294 recalculate_apic_map(apic->vcpu->kvm);
1295 } else
1296 ret = 1;
1297 break;
1298
1299 case APIC_SPIV: {
1300 u32 mask = 0x3ff;
1301 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1302 mask |= APIC_SPIV_DIRECTED_EOI;
1303 apic_set_spiv(apic, val & mask);
1304 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1305 int i;
1306 u32 lvt_val;
1307
1308 for (i = 0; i < APIC_LVT_NUM; i++) {
1309 lvt_val = kvm_apic_get_reg(apic,
1310 APIC_LVTT + 0x10 * i);
1311 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1312 lvt_val | APIC_LVT_MASKED);
1313 }
1314 apic_update_lvtt(apic);
1315 atomic_set(&apic->lapic_timer.pending, 0);
1316
1317 }
1318 break;
1319 }
1320 case APIC_ICR:
1321 /* No delay here, so we always clear the pending bit */
1322 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1323 apic_send_ipi(apic);
1324 break;
1325
1326 case APIC_ICR2:
1327 if (!apic_x2apic_mode(apic))
1328 val &= 0xff000000;
1329 apic_set_reg(apic, APIC_ICR2, val);
1330 break;
1331
1332 case APIC_LVT0:
1333 apic_manage_nmi_watchdog(apic, val);
1334 case APIC_LVTTHMR:
1335 case APIC_LVTPC:
1336 case APIC_LVT1:
1337 case APIC_LVTERR:
1338 /* TODO: Check vector */
1339 if (!kvm_apic_sw_enabled(apic))
1340 val |= APIC_LVT_MASKED;
1341
1342 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1343 apic_set_reg(apic, reg, val);
1344
1345 break;
1346
1347 case APIC_LVTT:
1348 if (!kvm_apic_sw_enabled(apic))
1349 val |= APIC_LVT_MASKED;
1350 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1351 apic_set_reg(apic, APIC_LVTT, val);
1352 apic_update_lvtt(apic);
1353 break;
1354
1355 case APIC_TMICT:
1356 if (apic_lvtt_tscdeadline(apic))
1357 break;
1358
1359 hrtimer_cancel(&apic->lapic_timer.timer);
1360 apic_set_reg(apic, APIC_TMICT, val);
1361 start_apic_timer(apic);
1362 break;
1363
1364 case APIC_TDCR:
1365 if (val & 4)
1366 apic_debug("KVM_WRITE:TDCR %x\n", val);
1367 apic_set_reg(apic, APIC_TDCR, val);
1368 update_divide_count(apic);
1369 break;
1370
1371 case APIC_ESR:
1372 if (apic_x2apic_mode(apic) && val != 0) {
1373 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1374 ret = 1;
1375 }
1376 break;
1377
1378 case APIC_SELF_IPI:
1379 if (apic_x2apic_mode(apic)) {
1380 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1381 } else
1382 ret = 1;
1383 break;
1384 default:
1385 ret = 1;
1386 break;
1387 }
1388 if (ret)
1389 apic_debug("Local APIC Write to read-only register %x\n", reg);
1390 return ret;
1391 }
1392
1393 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1394 gpa_t address, int len, const void *data)
1395 {
1396 struct kvm_lapic *apic = to_lapic(this);
1397 unsigned int offset = address - apic->base_address;
1398 u32 val;
1399
1400 if (!apic_mmio_in_range(apic, address))
1401 return -EOPNOTSUPP;
1402
1403 /*
1404 * APIC register must be aligned on 128-bits boundary.
1405 * 32/64/128 bits registers must be accessed thru 32 bits.
1406 * Refer SDM 8.4.1
1407 */
1408 if (len != 4 || (offset & 0xf)) {
1409 /* Don't shout loud, $infamous_os would cause only noise. */
1410 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1411 return 0;
1412 }
1413
1414 val = *(u32*)data;
1415
1416 /* too common printing */
1417 if (offset != APIC_EOI)
1418 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1419 "0x%x\n", __func__, offset, len, val);
1420
1421 apic_reg_write(apic, offset & 0xff0, val);
1422
1423 return 0;
1424 }
1425
1426 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1427 {
1428 if (kvm_vcpu_has_lapic(vcpu))
1429 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1430 }
1431 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1432
1433 /* emulate APIC access in a trap manner */
1434 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1435 {
1436 u32 val = 0;
1437
1438 /* hw has done the conditional check and inst decode */
1439 offset &= 0xff0;
1440
1441 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1442
1443 /* TODO: optimize to just emulate side effect w/o one more write */
1444 apic_reg_write(vcpu->arch.apic, offset, val);
1445 }
1446 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1447
1448 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1449 {
1450 struct kvm_lapic *apic = vcpu->arch.apic;
1451
1452 if (!vcpu->arch.apic)
1453 return;
1454
1455 hrtimer_cancel(&apic->lapic_timer.timer);
1456
1457 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1458 static_key_slow_dec_deferred(&apic_hw_disabled);
1459
1460 if (!apic->sw_enabled)
1461 static_key_slow_dec_deferred(&apic_sw_disabled);
1462
1463 if (apic->regs)
1464 free_page((unsigned long)apic->regs);
1465
1466 kfree(apic);
1467 }
1468
1469 /*
1470 *----------------------------------------------------------------------
1471 * LAPIC interface
1472 *----------------------------------------------------------------------
1473 */
1474
1475 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1476 {
1477 struct kvm_lapic *apic = vcpu->arch.apic;
1478
1479 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1480 apic_lvtt_period(apic))
1481 return 0;
1482
1483 return apic->lapic_timer.tscdeadline;
1484 }
1485
1486 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1487 {
1488 struct kvm_lapic *apic = vcpu->arch.apic;
1489
1490 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1491 apic_lvtt_period(apic))
1492 return;
1493
1494 hrtimer_cancel(&apic->lapic_timer.timer);
1495 apic->lapic_timer.tscdeadline = data;
1496 start_apic_timer(apic);
1497 }
1498
1499 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1500 {
1501 struct kvm_lapic *apic = vcpu->arch.apic;
1502
1503 if (!kvm_vcpu_has_lapic(vcpu))
1504 return;
1505
1506 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1507 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1508 }
1509
1510 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1511 {
1512 u64 tpr;
1513
1514 if (!kvm_vcpu_has_lapic(vcpu))
1515 return 0;
1516
1517 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1518
1519 return (tpr & 0xf0) >> 4;
1520 }
1521
1522 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1523 {
1524 u64 old_value = vcpu->arch.apic_base;
1525 struct kvm_lapic *apic = vcpu->arch.apic;
1526
1527 if (!apic) {
1528 value |= MSR_IA32_APICBASE_BSP;
1529 vcpu->arch.apic_base = value;
1530 return;
1531 }
1532
1533 vcpu->arch.apic_base = value;
1534
1535 /* update jump label if enable bit changes */
1536 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1537 if (value & MSR_IA32_APICBASE_ENABLE)
1538 static_key_slow_dec_deferred(&apic_hw_disabled);
1539 else
1540 static_key_slow_inc(&apic_hw_disabled.key);
1541 recalculate_apic_map(vcpu->kvm);
1542 }
1543
1544 if ((old_value ^ value) & X2APIC_ENABLE) {
1545 if (value & X2APIC_ENABLE) {
1546 u32 id = kvm_apic_id(apic);
1547 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1548 kvm_apic_set_ldr(apic, ldr);
1549 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1550 } else
1551 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1552 }
1553
1554 apic->base_address = apic->vcpu->arch.apic_base &
1555 MSR_IA32_APICBASE_BASE;
1556
1557 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1558 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1559 pr_warn_once("APIC base relocation is unsupported by KVM");
1560
1561 /* with FSB delivery interrupt, we can restart APIC functionality */
1562 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1563 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1564
1565 }
1566
1567 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1568 {
1569 struct kvm_lapic *apic;
1570 int i;
1571
1572 apic_debug("%s\n", __func__);
1573
1574 ASSERT(vcpu);
1575 apic = vcpu->arch.apic;
1576 ASSERT(apic != NULL);
1577
1578 /* Stop the timer in case it's a reset to an active apic */
1579 hrtimer_cancel(&apic->lapic_timer.timer);
1580
1581 kvm_apic_set_id(apic, vcpu->vcpu_id);
1582 kvm_apic_set_version(apic->vcpu);
1583
1584 for (i = 0; i < APIC_LVT_NUM; i++)
1585 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1586 apic_update_lvtt(apic);
1587 apic_set_reg(apic, APIC_LVT0,
1588 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1589
1590 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1591 apic_set_spiv(apic, 0xff);
1592 apic_set_reg(apic, APIC_TASKPRI, 0);
1593 kvm_apic_set_ldr(apic, 0);
1594 apic_set_reg(apic, APIC_ESR, 0);
1595 apic_set_reg(apic, APIC_ICR, 0);
1596 apic_set_reg(apic, APIC_ICR2, 0);
1597 apic_set_reg(apic, APIC_TDCR, 0);
1598 apic_set_reg(apic, APIC_TMICT, 0);
1599 for (i = 0; i < 8; i++) {
1600 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1601 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1602 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1603 }
1604 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1605 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
1606 apic->highest_isr_cache = -1;
1607 update_divide_count(apic);
1608 atomic_set(&apic->lapic_timer.pending, 0);
1609 if (kvm_vcpu_is_bsp(vcpu))
1610 kvm_lapic_set_base(vcpu,
1611 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1612 vcpu->arch.pv_eoi.msr_val = 0;
1613 apic_update_ppr(apic);
1614
1615 vcpu->arch.apic_arb_prio = 0;
1616 vcpu->arch.apic_attention = 0;
1617
1618 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1619 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1620 vcpu, kvm_apic_id(apic),
1621 vcpu->arch.apic_base, apic->base_address);
1622 }
1623
1624 /*
1625 *----------------------------------------------------------------------
1626 * timer interface
1627 *----------------------------------------------------------------------
1628 */
1629
1630 static bool lapic_is_periodic(struct kvm_lapic *apic)
1631 {
1632 return apic_lvtt_period(apic);
1633 }
1634
1635 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1636 {
1637 struct kvm_lapic *apic = vcpu->arch.apic;
1638
1639 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1640 apic_lvt_enabled(apic, APIC_LVTT))
1641 return atomic_read(&apic->lapic_timer.pending);
1642
1643 return 0;
1644 }
1645
1646 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1647 {
1648 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1649 int vector, mode, trig_mode;
1650
1651 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1652 vector = reg & APIC_VECTOR_MASK;
1653 mode = reg & APIC_MODE_MASK;
1654 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1655 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1656 NULL);
1657 }
1658 return 0;
1659 }
1660
1661 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1662 {
1663 struct kvm_lapic *apic = vcpu->arch.apic;
1664
1665 if (apic)
1666 kvm_apic_local_deliver(apic, APIC_LVT0);
1667 }
1668
1669 static const struct kvm_io_device_ops apic_mmio_ops = {
1670 .read = apic_mmio_read,
1671 .write = apic_mmio_write,
1672 };
1673
1674 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1675 {
1676 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1677 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1678
1679 apic_timer_expired(apic);
1680
1681 if (lapic_is_periodic(apic)) {
1682 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1683 return HRTIMER_RESTART;
1684 } else
1685 return HRTIMER_NORESTART;
1686 }
1687
1688 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1689 {
1690 struct kvm_lapic *apic;
1691
1692 ASSERT(vcpu != NULL);
1693 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1694
1695 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1696 if (!apic)
1697 goto nomem;
1698
1699 vcpu->arch.apic = apic;
1700
1701 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1702 if (!apic->regs) {
1703 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1704 vcpu->vcpu_id);
1705 goto nomem_free_apic;
1706 }
1707 apic->vcpu = vcpu;
1708
1709 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1710 HRTIMER_MODE_ABS);
1711 apic->lapic_timer.timer.function = apic_timer_fn;
1712
1713 /*
1714 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1715 * thinking that APIC satet has changed.
1716 */
1717 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1718 kvm_lapic_set_base(vcpu,
1719 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1720
1721 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1722 kvm_lapic_reset(vcpu);
1723 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1724
1725 return 0;
1726 nomem_free_apic:
1727 kfree(apic);
1728 nomem:
1729 return -ENOMEM;
1730 }
1731
1732 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1733 {
1734 struct kvm_lapic *apic = vcpu->arch.apic;
1735 int highest_irr;
1736
1737 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1738 return -1;
1739
1740 apic_update_ppr(apic);
1741 highest_irr = apic_find_highest_irr(apic);
1742 if ((highest_irr == -1) ||
1743 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1744 return -1;
1745 return highest_irr;
1746 }
1747
1748 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1749 {
1750 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1751 int r = 0;
1752
1753 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1754 r = 1;
1755 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1756 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1757 r = 1;
1758 return r;
1759 }
1760
1761 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1762 {
1763 struct kvm_lapic *apic = vcpu->arch.apic;
1764
1765 if (!kvm_vcpu_has_lapic(vcpu))
1766 return;
1767
1768 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1769 kvm_apic_local_deliver(apic, APIC_LVTT);
1770 if (apic_lvtt_tscdeadline(apic))
1771 apic->lapic_timer.tscdeadline = 0;
1772 atomic_set(&apic->lapic_timer.pending, 0);
1773 }
1774 }
1775
1776 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1777 {
1778 int vector = kvm_apic_has_interrupt(vcpu);
1779 struct kvm_lapic *apic = vcpu->arch.apic;
1780
1781 if (vector == -1)
1782 return -1;
1783
1784 /*
1785 * We get here even with APIC virtualization enabled, if doing
1786 * nested virtualization and L1 runs with the "acknowledge interrupt
1787 * on exit" mode. Then we cannot inject the interrupt via RVI,
1788 * because the process would deliver it through the IDT.
1789 */
1790
1791 apic_set_isr(vector, apic);
1792 apic_update_ppr(apic);
1793 apic_clear_irr(vector, apic);
1794 return vector;
1795 }
1796
1797 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1798 struct kvm_lapic_state *s)
1799 {
1800 struct kvm_lapic *apic = vcpu->arch.apic;
1801
1802 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1803 /* set SPIV separately to get count of SW disabled APICs right */
1804 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1805 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1806 /* call kvm_apic_set_id() to put apic into apic_map */
1807 kvm_apic_set_id(apic, kvm_apic_id(apic));
1808 kvm_apic_set_version(vcpu);
1809
1810 apic_update_ppr(apic);
1811 hrtimer_cancel(&apic->lapic_timer.timer);
1812 apic_update_lvtt(apic);
1813 apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1814 update_divide_count(apic);
1815 start_apic_timer(apic);
1816 apic->irr_pending = true;
1817 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
1818 1 : count_vectors(apic->regs + APIC_ISR);
1819 apic->highest_isr_cache = -1;
1820 if (kvm_x86_ops->hwapic_irr_update)
1821 kvm_x86_ops->hwapic_irr_update(vcpu,
1822 apic_find_highest_irr(apic));
1823 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1824 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1825 apic_find_highest_isr(apic));
1826 kvm_make_request(KVM_REQ_EVENT, vcpu);
1827 kvm_rtc_eoi_tracking_restore_one(vcpu);
1828 }
1829
1830 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1831 {
1832 struct hrtimer *timer;
1833
1834 if (!kvm_vcpu_has_lapic(vcpu))
1835 return;
1836
1837 timer = &vcpu->arch.apic->lapic_timer.timer;
1838 if (hrtimer_cancel(timer))
1839 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1840 }
1841
1842 /*
1843 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1844 *
1845 * Detect whether guest triggered PV EOI since the
1846 * last entry. If yes, set EOI on guests's behalf.
1847 * Clear PV EOI in guest memory in any case.
1848 */
1849 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1850 struct kvm_lapic *apic)
1851 {
1852 bool pending;
1853 int vector;
1854 /*
1855 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1856 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1857 *
1858 * KVM_APIC_PV_EOI_PENDING is unset:
1859 * -> host disabled PV EOI.
1860 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1861 * -> host enabled PV EOI, guest did not execute EOI yet.
1862 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1863 * -> host enabled PV EOI, guest executed EOI.
1864 */
1865 BUG_ON(!pv_eoi_enabled(vcpu));
1866 pending = pv_eoi_get_pending(vcpu);
1867 /*
1868 * Clear pending bit in any case: it will be set again on vmentry.
1869 * While this might not be ideal from performance point of view,
1870 * this makes sure pv eoi is only enabled when we know it's safe.
1871 */
1872 pv_eoi_clr_pending(vcpu);
1873 if (pending)
1874 return;
1875 vector = apic_set_eoi(apic);
1876 trace_kvm_pv_eoi(apic, vector);
1877 }
1878
1879 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1880 {
1881 u32 data;
1882
1883 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1884 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1885
1886 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1887 return;
1888
1889 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1890 sizeof(u32));
1891
1892 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1893 }
1894
1895 /*
1896 * apic_sync_pv_eoi_to_guest - called before vmentry
1897 *
1898 * Detect whether it's safe to enable PV EOI and
1899 * if yes do so.
1900 */
1901 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1902 struct kvm_lapic *apic)
1903 {
1904 if (!pv_eoi_enabled(vcpu) ||
1905 /* IRR set or many bits in ISR: could be nested. */
1906 apic->irr_pending ||
1907 /* Cache not set: could be safe but we don't bother. */
1908 apic->highest_isr_cache == -1 ||
1909 /* Need EOI to update ioapic. */
1910 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1911 /*
1912 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1913 * so we need not do anything here.
1914 */
1915 return;
1916 }
1917
1918 pv_eoi_set_pending(apic->vcpu);
1919 }
1920
1921 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1922 {
1923 u32 data, tpr;
1924 int max_irr, max_isr;
1925 struct kvm_lapic *apic = vcpu->arch.apic;
1926
1927 apic_sync_pv_eoi_to_guest(vcpu, apic);
1928
1929 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1930 return;
1931
1932 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1933 max_irr = apic_find_highest_irr(apic);
1934 if (max_irr < 0)
1935 max_irr = 0;
1936 max_isr = apic_find_highest_isr(apic);
1937 if (max_isr < 0)
1938 max_isr = 0;
1939 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1940
1941 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1942 sizeof(u32));
1943 }
1944
1945 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1946 {
1947 if (vapic_addr) {
1948 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1949 &vcpu->arch.apic->vapic_cache,
1950 vapic_addr, sizeof(u32)))
1951 return -EINVAL;
1952 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1953 } else {
1954 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1955 }
1956
1957 vcpu->arch.apic->vapic_addr = vapic_addr;
1958 return 0;
1959 }
1960
1961 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1962 {
1963 struct kvm_lapic *apic = vcpu->arch.apic;
1964 u32 reg = (msr - APIC_BASE_MSR) << 4;
1965
1966 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1967 return 1;
1968
1969 if (reg == APIC_ICR2)
1970 return 1;
1971
1972 /* if this is ICR write vector before command */
1973 if (reg == APIC_ICR)
1974 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1975 return apic_reg_write(apic, reg, (u32)data);
1976 }
1977
1978 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1979 {
1980 struct kvm_lapic *apic = vcpu->arch.apic;
1981 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1982
1983 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1984 return 1;
1985
1986 if (reg == APIC_DFR || reg == APIC_ICR2) {
1987 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1988 reg);
1989 return 1;
1990 }
1991
1992 if (apic_reg_read(apic, reg, 4, &low))
1993 return 1;
1994 if (reg == APIC_ICR)
1995 apic_reg_read(apic, APIC_ICR2, 4, &high);
1996
1997 *data = (((u64)high) << 32) | low;
1998
1999 return 0;
2000 }
2001
2002 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2003 {
2004 struct kvm_lapic *apic = vcpu->arch.apic;
2005
2006 if (!kvm_vcpu_has_lapic(vcpu))
2007 return 1;
2008
2009 /* if this is ICR write vector before command */
2010 if (reg == APIC_ICR)
2011 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2012 return apic_reg_write(apic, reg, (u32)data);
2013 }
2014
2015 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2016 {
2017 struct kvm_lapic *apic = vcpu->arch.apic;
2018 u32 low, high = 0;
2019
2020 if (!kvm_vcpu_has_lapic(vcpu))
2021 return 1;
2022
2023 if (apic_reg_read(apic, reg, 4, &low))
2024 return 1;
2025 if (reg == APIC_ICR)
2026 apic_reg_read(apic, APIC_ICR2, 4, &high);
2027
2028 *data = (((u64)high) << 32) | low;
2029
2030 return 0;
2031 }
2032
2033 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2034 {
2035 u64 addr = data & ~KVM_MSR_ENABLED;
2036 if (!IS_ALIGNED(addr, 4))
2037 return 1;
2038
2039 vcpu->arch.pv_eoi.msr_val = data;
2040 if (!pv_eoi_enabled(vcpu))
2041 return 0;
2042 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2043 addr, sizeof(u8));
2044 }
2045
2046 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2047 {
2048 struct kvm_lapic *apic = vcpu->arch.apic;
2049 u8 sipi_vector;
2050 unsigned long pe;
2051
2052 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2053 return;
2054
2055 pe = xchg(&apic->pending_events, 0);
2056
2057 if (test_bit(KVM_APIC_INIT, &pe)) {
2058 kvm_lapic_reset(vcpu);
2059 kvm_vcpu_reset(vcpu);
2060 if (kvm_vcpu_is_bsp(apic->vcpu))
2061 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2062 else
2063 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2064 }
2065 if (test_bit(KVM_APIC_SIPI, &pe) &&
2066 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2067 /* evaluate pending_events before reading the vector */
2068 smp_rmb();
2069 sipi_vector = apic->sipi_vector;
2070 apic_debug("vcpu %d received sipi with vector # %x\n",
2071 vcpu->vcpu_id, sipi_vector);
2072 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2073 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2074 }
2075 }
2076
2077 void kvm_lapic_init(void)
2078 {
2079 /* do not patch jump label more than once per second */
2080 jump_label_rate_limit(&apic_hw_disabled, HZ);
2081 jump_label_rate_limit(&apic_sw_disabled, HZ);
2082 }
Linux with added FPC-III support