include/media/adv7842.h

   1 /*
   2  * adv7842 - Analog Devices ADV7842 video decoder driver
   3  *
   4  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 #ifndef _ADV7842_
  22 #define _ADV7842_
  23
  24 /* Analog input muxing modes (AFE register 0x02, [2:0]) */
  25 enum adv7842_ain_sel {
  26         ADV7842_AIN1_2_3_NC_SYNC_1_2 = 0,
  27         ADV7842_AIN4_5_6_NC_SYNC_2_1 = 1,
  28         ADV7842_AIN7_8_9_NC_SYNC_3_1 = 2,
  29         ADV7842_AIN10_11_12_NC_SYNC_4_1 = 3,
  30         ADV7842_AIN9_4_5_6_SYNC_2_1 = 4,
  31 };
  32
  33 /* Bus rotation and reordering (IO register 0x04, [7:5]) */
  34 enum adv7842_op_ch_sel {
  35         ADV7842_OP_CH_SEL_GBR = 0,
  36         ADV7842_OP_CH_SEL_GRB = 1,
  37         ADV7842_OP_CH_SEL_BGR = 2,
  38         ADV7842_OP_CH_SEL_RGB = 3,
  39         ADV7842_OP_CH_SEL_BRG = 4,
  40         ADV7842_OP_CH_SEL_RBG = 5,
  41 };
  42
  43 /* Mode of operation */
  44 enum adv7842_mode {
  45         ADV7842_MODE_SDP,
  46         ADV7842_MODE_COMP,
  47         ADV7842_MODE_RGB,
  48         ADV7842_MODE_HDMI
  49 };
  50
  51 /* Video standard select (IO register 0x00, [5:0]) */
  52 enum adv7842_vid_std_select {
  53         /* SDP */
  54         ADV7842_SDP_VID_STD_CVBS_SD_4x1 = 0x01,
  55         ADV7842_SDP_VID_STD_YC_SD4_x1 = 0x09,
  56         /* RGB */
  57         ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE = 0x07,
  58         /* HDMI GR */
  59         ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE = 0x02,
  60         /* HDMI COMP */
  61         ADV7842_HDMI_COMP_VID_STD_HD_1250P = 0x1e,
  62 };
  63
  64 /* Input Color Space (IO register 0x02, [7:4]) */
  65 enum adv7842_inp_color_space {
  66         ADV7842_INP_COLOR_SPACE_LIM_RGB = 0,
  67         ADV7842_INP_COLOR_SPACE_FULL_RGB = 1,
  68         ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
  69         ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
  70         ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4,
  71         ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5,
  72         ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
  73         ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
  74         ADV7842_INP_COLOR_SPACE_AUTO = 0xf,
  75 };
  76
  77 /* Select output format (IO register 0x03, [7:0]) */
  78 enum adv7842_op_format_sel {
  79         ADV7842_OP_FORMAT_SEL_SDR_ITU656_8 = 0x00,
  80         ADV7842_OP_FORMAT_SEL_SDR_ITU656_10 = 0x01,
  81         ADV7842_OP_FORMAT_SEL_SDR_ITU656_12_MODE0 = 0x02,
  82         ADV7842_OP_FORMAT_SEL_SDR_ITU656_12_MODE1 = 0x06,
  83         ADV7842_OP_FORMAT_SEL_SDR_ITU656_12_MODE2 = 0x0a,
  84         ADV7842_OP_FORMAT_SEL_DDR_422_8 = 0x20,
  85         ADV7842_OP_FORMAT_SEL_DDR_422_10 = 0x21,
  86         ADV7842_OP_FORMAT_SEL_DDR_422_12_MODE0 = 0x22,
  87         ADV7842_OP_FORMAT_SEL_DDR_422_12_MODE1 = 0x23,
  88         ADV7842_OP_FORMAT_SEL_DDR_422_12_MODE2 = 0x24,
  89         ADV7842_OP_FORMAT_SEL_SDR_444_24 = 0x40,
  90         ADV7842_OP_FORMAT_SEL_SDR_444_30 = 0x41,
  91         ADV7842_OP_FORMAT_SEL_SDR_444_36_MODE0 = 0x42,
  92         ADV7842_OP_FORMAT_SEL_DDR_444_24 = 0x60,
  93         ADV7842_OP_FORMAT_SEL_DDR_444_30 = 0x61,
  94         ADV7842_OP_FORMAT_SEL_DDR_444_36 = 0x62,
  95         ADV7842_OP_FORMAT_SEL_SDR_ITU656_16 = 0x80,
  96         ADV7842_OP_FORMAT_SEL_SDR_ITU656_20 = 0x81,
  97         ADV7842_OP_FORMAT_SEL_SDR_ITU656_24_MODE0 = 0x82,
  98         ADV7842_OP_FORMAT_SEL_SDR_ITU656_24_MODE1 = 0x86,
  99         ADV7842_OP_FORMAT_SEL_SDR_ITU656_24_MODE2 = 0x8a,
 100 };
 101
 102 enum adv7842_select_input {
 103         ADV7842_SELECT_HDMI_PORT_A,
 104         ADV7842_SELECT_HDMI_PORT_B,
 105         ADV7842_SELECT_VGA_RGB,
 106         ADV7842_SELECT_VGA_COMP,
 107         ADV7842_SELECT_SDP_CVBS,
 108         ADV7842_SELECT_SDP_YC,
 109 };
 110
 111 enum adv7842_drive_strength {
 112         ADV7842_DR_STR_LOW = 0,
 113         ADV7842_DR_STR_MEDIUM_LOW = 1,
 114         ADV7842_DR_STR_MEDIUM_HIGH = 2,
 115         ADV7842_DR_STR_HIGH = 3,
 116 };
 117
 118 struct adv7842_sdp_csc_coeff {
 119         bool manual;
 120         uint16_t scaling;
 121         uint16_t A1;
 122         uint16_t A2;
 123         uint16_t A3;
 124         uint16_t A4;
 125         uint16_t B1;
 126         uint16_t B2;
 127         uint16_t B3;
 128         uint16_t B4;
 129         uint16_t C1;
 130         uint16_t C2;
 131         uint16_t C3;
 132         uint16_t C4;
 133 };
 134
 135 struct adv7842_sdp_io_sync_adjustment {
 136         bool adjust;
 137         uint16_t hs_beg;
 138         uint16_t hs_width;
 139         uint16_t de_beg;
 140         uint16_t de_end;
 141         uint8_t vs_beg_o;
 142         uint8_t vs_beg_e;
 143         uint8_t vs_end_o;
 144         uint8_t vs_end_e;
 145         uint8_t de_v_beg_o;
 146         uint8_t de_v_beg_e;
 147         uint8_t de_v_end_o;
 148         uint8_t de_v_end_e;
 149 };
 150
 151 /* Platform dependent definition */
 152 struct adv7842_platform_data {
 153         /* chip reset during probe */
 154         unsigned chip_reset:1;
 155
 156         /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
 157         unsigned disable_pwrdnb:1;
 158
 159         /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
 160         unsigned disable_cable_det_rst:1;
 161
 162         /* Analog input muxing mode */
 163         enum adv7842_ain_sel ain_sel;
 164
 165         /* Bus rotation and reordering */
 166         enum adv7842_op_ch_sel op_ch_sel;
 167
 168         /* Default mode */
 169         enum adv7842_mode mode;
 170
 171         /* Default input */
 172         unsigned input;
 173
 174         /* Video standard */
 175         enum adv7842_vid_std_select vid_std_select;
 176
 177         /* Select output format */
 178         enum adv7842_op_format_sel op_format_sel;
 179
 180         /* IO register 0x02 */
 181         unsigned alt_gamma:1;
 182         unsigned op_656_range:1;
 183         unsigned rgb_out:1;
 184         unsigned alt_data_sat:1;
 185
 186         /* IO register 0x05 */
 187         unsigned blank_data:1;
 188         unsigned insert_av_codes:1;
 189         unsigned replicate_av_codes:1;
 190         unsigned invert_cbcr:1;
 191
 192         /* IO register 0x30 */
 193         unsigned output_bus_lsb_to_msb:1;
 194
 195         /* IO register 0x14 */
 196         enum adv7842_drive_strength dr_str_data;
 197         enum adv7842_drive_strength dr_str_clk;
 198         enum adv7842_drive_strength dr_str_sync;
 199
 200         /*
 201          * IO register 0x19: Adjustment to the LLC DLL phase in
 202          * increments of 1/32 of a clock period.
 203          */
 204         unsigned llc_dll_phase:5;
 205
 206         /* External RAM for 3-D comb or frame synchronizer */
 207         unsigned sd_ram_size; /* ram size in MB */
 208         unsigned sd_ram_ddr:1; /* ddr or sdr sdram */
 209
 210         /* HDMI free run, CP-reg 0xBA */
 211         unsigned hdmi_free_run_enable:1;
 212         /* 0 = Mode 0: run when there is no TMDS clock
 213            1 = Mode 1: run when there is no TMDS clock or the
 214                video resolution does not match programmed one. */
 215         unsigned hdmi_free_run_mode:1;
 216
 217         /* SDP free run, CP-reg 0xDD */
 218         unsigned sdp_free_run_auto:1;
 219         unsigned sdp_free_run_man_col_en:1;
 220         unsigned sdp_free_run_cbar_en:1;
 221         unsigned sdp_free_run_force:1;
 222
 223         /* HPA manual (0) or auto (1), affects HDMI register 0x69 */
 224         unsigned hpa_auto:1;
 225
 226         struct adv7842_sdp_csc_coeff sdp_csc_coeff;
 227
 228         struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625;
 229         struct adv7842_sdp_io_sync_adjustment sdp_io_sync_525;
 230
 231         /* i2c addresses */
 232         u8 i2c_sdp_io;
 233         u8 i2c_sdp;
 234         u8 i2c_cp;
 235         u8 i2c_vdp;
 236         u8 i2c_afe;
 237         u8 i2c_hdmi;
 238         u8 i2c_repeater;
 239         u8 i2c_edid;
 240         u8 i2c_infoframe;
 241         u8 i2c_cec;
 242         u8 i2c_avlink;
 243 };
 244
 245 #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE   (V4L2_CID_DV_CLASS_BASE + 0x1000)
 246 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL   (V4L2_CID_DV_CLASS_BASE + 0x1001)
 247 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR          (V4L2_CID_DV_CLASS_BASE + 0x1002)
 248
 249 /* notify events */
 250 #define ADV7842_FMT_CHANGE      1
 251
 252 /* custom ioctl, used to test the external RAM that's used by the
 253  * deinterlacer. */
 254 #define ADV7842_CMD_RAM_TEST _IO('V', BASE_VIDIOC_PRIVATE)
 255
 256 #define ADV7842_EDID_PORT_A   0
 257 #define ADV7842_EDID_PORT_B   1
 258 #define ADV7842_EDID_PORT_VGA 2
 259
 260 #endif