include/media/tvp7002.h

   1 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
   2  * Digitizer with Horizontal PLL registers
   3  *
   4  * Copyright (C) 2009 Texas Instruments Inc
   5  * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
   6  *
   7  * This code is partially based upon the TVP5150 driver
   8  * written by Mauro Carvalho Chehab (mchehab@infradead.org),
   9  * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
  10  * and the TVP7002 driver in the TI LSP 2.10.00.14
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26 #ifndef _TVP7002_H_
  27 #define _TVP7002_H_
  28
  29 #define TVP7002_MODULE_NAME "tvp7002"
  30
  31 /**
  32  * struct tvp7002_config - Platform dependent data
  33  *@clk_polarity: Clock polarity
  34  *              0 - Data clocked out on rising edge of DATACLK signal
  35  *              1 - Data clocked out on falling edge of DATACLK signal
  36  *@hs_polarity:  HSYNC polarity
  37  *              0 - Active low HSYNC output, 1 - Active high HSYNC output
  38  *@vs_polarity: VSYNC Polarity
  39  *              0 - Active low VSYNC output, 1 - Active high VSYNC output
  40  *@fid_polarity: Active-high Field ID polarity.
  41  *              0 - The field ID output is set to logic 1 for an odd field
  42  *                  (field 1) and set to logic 0 for an even field (field 0).
  43  *              1 - Operation with polarity inverted.
  44  *@sog_polarity: Active high Sync on Green output polarity.
  45  *              0 - Normal operation, 1 - Operation with polarity inverted
  46  */
  47 struct tvp7002_config {
  48         bool clk_polarity;
  49         bool hs_polarity;
  50         bool vs_polarity;
  51         bool fid_polarity;
  52         bool sog_polarity;
  53 };
  54 #endif