Linux 4.1.18
[linux/fpc-iii.git] / include / uapi / drm / i915_drm.h
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1 /*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef _UAPI_I915_DRM_H_
28 #define _UAPI_I915_DRM_H_
30 #include <drm/drm.h>
32 /* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
36 /**
37 * DOC: uevents generated by i915 on it's device node
39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
40 * event from the gpu l3 cache. Additional information supplied is ROW,
41 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
42 * track of these events and if a specific cache-line seems to have a
43 * persistent error remap it with the l3 remapping tool supplied in
44 * intel-gpu-tools. The value supplied with the event is always 1.
46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
47 * hangcheck. The error detection event is a good indicator of when things
48 * began to go badly. The value supplied with the event is a 1 upon error
49 * detection, and a 0 upon reset completion, signifying no more error
50 * exists. NOTE: Disabling hangcheck or reset via module parameter will
51 * cause the related events to not be seen.
53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
54 * the GPU. The value supplied with the event is always 1. NOTE: Disable
55 * reset via module parameter will cause this event to not be seen.
57 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
58 #define I915_ERROR_UEVENT "ERROR"
59 #define I915_RESET_UEVENT "RESET"
61 /* Each region is a minimum of 16k, and there are at most 255 of them.
63 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
64 * of chars for next/prev indices */
65 #define I915_LOG_MIN_TEX_REGION_SIZE 14
67 typedef struct _drm_i915_init {
68 enum {
69 I915_INIT_DMA = 0x01,
70 I915_CLEANUP_DMA = 0x02,
71 I915_RESUME_DMA = 0x03
72 } func;
73 unsigned int mmio_offset;
74 int sarea_priv_offset;
75 unsigned int ring_start;
76 unsigned int ring_end;
77 unsigned int ring_size;
78 unsigned int front_offset;
79 unsigned int back_offset;
80 unsigned int depth_offset;
81 unsigned int w;
82 unsigned int h;
83 unsigned int pitch;
84 unsigned int pitch_bits;
85 unsigned int back_pitch;
86 unsigned int depth_pitch;
87 unsigned int cpp;
88 unsigned int chipset;
89 } drm_i915_init_t;
91 typedef struct _drm_i915_sarea {
92 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
93 int last_upload; /* last time texture was uploaded */
94 int last_enqueue; /* last time a buffer was enqueued */
95 int last_dispatch; /* age of the most recently dispatched buffer */
96 int ctxOwner; /* last context to upload state */
97 int texAge;
98 int pf_enabled; /* is pageflipping allowed? */
99 int pf_active;
100 int pf_current_page; /* which buffer is being displayed? */
101 int perf_boxes; /* performance boxes to be displayed */
102 int width, height; /* screen size in pixels */
104 drm_handle_t front_handle;
105 int front_offset;
106 int front_size;
108 drm_handle_t back_handle;
109 int back_offset;
110 int back_size;
112 drm_handle_t depth_handle;
113 int depth_offset;
114 int depth_size;
116 drm_handle_t tex_handle;
117 int tex_offset;
118 int tex_size;
119 int log_tex_granularity;
120 int pitch;
121 int rotation; /* 0, 90, 180 or 270 */
122 int rotated_offset;
123 int rotated_size;
124 int rotated_pitch;
125 int virtualX, virtualY;
127 unsigned int front_tiled;
128 unsigned int back_tiled;
129 unsigned int depth_tiled;
130 unsigned int rotated_tiled;
131 unsigned int rotated2_tiled;
133 int pipeA_x;
134 int pipeA_y;
135 int pipeA_w;
136 int pipeA_h;
137 int pipeB_x;
138 int pipeB_y;
139 int pipeB_w;
140 int pipeB_h;
142 /* fill out some space for old userspace triple buffer */
143 drm_handle_t unused_handle;
144 __u32 unused1, unused2, unused3;
146 /* buffer object handles for static buffers. May change
147 * over the lifetime of the client.
149 __u32 front_bo_handle;
150 __u32 back_bo_handle;
151 __u32 unused_bo_handle;
152 __u32 depth_bo_handle;
154 } drm_i915_sarea_t;
156 /* due to userspace building against these headers we need some compat here */
157 #define planeA_x pipeA_x
158 #define planeA_y pipeA_y
159 #define planeA_w pipeA_w
160 #define planeA_h pipeA_h
161 #define planeB_x pipeB_x
162 #define planeB_y pipeB_y
163 #define planeB_w pipeB_w
164 #define planeB_h pipeB_h
166 /* Flags for perf_boxes
168 #define I915_BOX_RING_EMPTY 0x1
169 #define I915_BOX_FLIP 0x2
170 #define I915_BOX_WAIT 0x4
171 #define I915_BOX_TEXTURE_LOAD 0x8
172 #define I915_BOX_LOST_CONTEXT 0x10
174 /* I915 specific ioctls
175 * The device specific ioctl range is 0x40 to 0x79.
177 #define DRM_I915_INIT 0x00
178 #define DRM_I915_FLUSH 0x01
179 #define DRM_I915_FLIP 0x02
180 #define DRM_I915_BATCHBUFFER 0x03
181 #define DRM_I915_IRQ_EMIT 0x04
182 #define DRM_I915_IRQ_WAIT 0x05
183 #define DRM_I915_GETPARAM 0x06
184 #define DRM_I915_SETPARAM 0x07
185 #define DRM_I915_ALLOC 0x08
186 #define DRM_I915_FREE 0x09
187 #define DRM_I915_INIT_HEAP 0x0a
188 #define DRM_I915_CMDBUFFER 0x0b
189 #define DRM_I915_DESTROY_HEAP 0x0c
190 #define DRM_I915_SET_VBLANK_PIPE 0x0d
191 #define DRM_I915_GET_VBLANK_PIPE 0x0e
192 #define DRM_I915_VBLANK_SWAP 0x0f
193 #define DRM_I915_HWS_ADDR 0x11
194 #define DRM_I915_GEM_INIT 0x13
195 #define DRM_I915_GEM_EXECBUFFER 0x14
196 #define DRM_I915_GEM_PIN 0x15
197 #define DRM_I915_GEM_UNPIN 0x16
198 #define DRM_I915_GEM_BUSY 0x17
199 #define DRM_I915_GEM_THROTTLE 0x18
200 #define DRM_I915_GEM_ENTERVT 0x19
201 #define DRM_I915_GEM_LEAVEVT 0x1a
202 #define DRM_I915_GEM_CREATE 0x1b
203 #define DRM_I915_GEM_PREAD 0x1c
204 #define DRM_I915_GEM_PWRITE 0x1d
205 #define DRM_I915_GEM_MMAP 0x1e
206 #define DRM_I915_GEM_SET_DOMAIN 0x1f
207 #define DRM_I915_GEM_SW_FINISH 0x20
208 #define DRM_I915_GEM_SET_TILING 0x21
209 #define DRM_I915_GEM_GET_TILING 0x22
210 #define DRM_I915_GEM_GET_APERTURE 0x23
211 #define DRM_I915_GEM_MMAP_GTT 0x24
212 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
213 #define DRM_I915_GEM_MADVISE 0x26
214 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
215 #define DRM_I915_OVERLAY_ATTRS 0x28
216 #define DRM_I915_GEM_EXECBUFFER2 0x29
217 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
218 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
219 #define DRM_I915_GEM_WAIT 0x2c
220 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
221 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
222 #define DRM_I915_GEM_SET_CACHING 0x2f
223 #define DRM_I915_GEM_GET_CACHING 0x30
224 #define DRM_I915_REG_READ 0x31
225 #define DRM_I915_GET_RESET_STATS 0x32
226 #define DRM_I915_GEM_USERPTR 0x33
227 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
228 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
230 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
231 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
232 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
233 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
234 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
235 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
236 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
237 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
238 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
239 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
240 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
241 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
242 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
243 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
244 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
245 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
246 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
247 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
248 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
249 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
250 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
251 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
252 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
253 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
254 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
255 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
256 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
257 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
258 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
259 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
260 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
261 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
262 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
263 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
264 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
265 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
266 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
267 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
268 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
269 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
270 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
271 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
272 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
273 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
274 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
275 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
276 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
277 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
278 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
279 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
280 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
281 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
283 /* Allow drivers to submit batchbuffers directly to hardware, relying
284 * on the security mechanisms provided by hardware.
286 typedef struct drm_i915_batchbuffer {
287 int start; /* agp offset */
288 int used; /* nr bytes in use */
289 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
290 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
291 int num_cliprects; /* mulitpass with multiple cliprects? */
292 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
293 } drm_i915_batchbuffer_t;
295 /* As above, but pass a pointer to userspace buffer which can be
296 * validated by the kernel prior to sending to hardware.
298 typedef struct _drm_i915_cmdbuffer {
299 char __user *buf; /* pointer to userspace command buffer */
300 int sz; /* nr bytes in buf */
301 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
302 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
303 int num_cliprects; /* mulitpass with multiple cliprects? */
304 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
305 } drm_i915_cmdbuffer_t;
307 /* Userspace can request & wait on irq's:
309 typedef struct drm_i915_irq_emit {
310 int __user *irq_seq;
311 } drm_i915_irq_emit_t;
313 typedef struct drm_i915_irq_wait {
314 int irq_seq;
315 } drm_i915_irq_wait_t;
317 /* Ioctl to query kernel params:
319 #define I915_PARAM_IRQ_ACTIVE 1
320 #define I915_PARAM_ALLOW_BATCHBUFFER 2
321 #define I915_PARAM_LAST_DISPATCH 3
322 #define I915_PARAM_CHIPSET_ID 4
323 #define I915_PARAM_HAS_GEM 5
324 #define I915_PARAM_NUM_FENCES_AVAIL 6
325 #define I915_PARAM_HAS_OVERLAY 7
326 #define I915_PARAM_HAS_PAGEFLIPPING 8
327 #define I915_PARAM_HAS_EXECBUF2 9
328 #define I915_PARAM_HAS_BSD 10
329 #define I915_PARAM_HAS_BLT 11
330 #define I915_PARAM_HAS_RELAXED_FENCING 12
331 #define I915_PARAM_HAS_COHERENT_RINGS 13
332 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
333 #define I915_PARAM_HAS_RELAXED_DELTA 15
334 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
335 #define I915_PARAM_HAS_LLC 17
336 #define I915_PARAM_HAS_ALIASING_PPGTT 18
337 #define I915_PARAM_HAS_WAIT_TIMEOUT 19
338 #define I915_PARAM_HAS_SEMAPHORES 20
339 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
340 #define I915_PARAM_HAS_VEBOX 22
341 #define I915_PARAM_HAS_SECURE_BATCHES 23
342 #define I915_PARAM_HAS_PINNED_BATCHES 24
343 #define I915_PARAM_HAS_EXEC_NO_RELOC 25
344 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
345 #define I915_PARAM_HAS_WT 27
346 #define I915_PARAM_CMD_PARSER_VERSION 28
347 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
348 #define I915_PARAM_MMAP_VERSION 30
349 #define I915_PARAM_HAS_BSD2 31
350 #define I915_PARAM_REVISION 32
351 #define I915_PARAM_SUBSLICE_TOTAL 33
352 #define I915_PARAM_EU_TOTAL 34
354 typedef struct drm_i915_getparam {
355 int param;
356 int __user *value;
357 } drm_i915_getparam_t;
359 /* Ioctl to set kernel params:
361 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
362 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
363 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
364 #define I915_SETPARAM_NUM_USED_FENCES 4
366 typedef struct drm_i915_setparam {
367 int param;
368 int value;
369 } drm_i915_setparam_t;
371 /* A memory manager for regions of shared memory:
373 #define I915_MEM_REGION_AGP 1
375 typedef struct drm_i915_mem_alloc {
376 int region;
377 int alignment;
378 int size;
379 int __user *region_offset; /* offset from start of fb or agp */
380 } drm_i915_mem_alloc_t;
382 typedef struct drm_i915_mem_free {
383 int region;
384 int region_offset;
385 } drm_i915_mem_free_t;
387 typedef struct drm_i915_mem_init_heap {
388 int region;
389 int size;
390 int start;
391 } drm_i915_mem_init_heap_t;
393 /* Allow memory manager to be torn down and re-initialized (eg on
394 * rotate):
396 typedef struct drm_i915_mem_destroy_heap {
397 int region;
398 } drm_i915_mem_destroy_heap_t;
400 /* Allow X server to configure which pipes to monitor for vblank signals
402 #define DRM_I915_VBLANK_PIPE_A 1
403 #define DRM_I915_VBLANK_PIPE_B 2
405 typedef struct drm_i915_vblank_pipe {
406 int pipe;
407 } drm_i915_vblank_pipe_t;
409 /* Schedule buffer swap at given vertical blank:
411 typedef struct drm_i915_vblank_swap {
412 drm_drawable_t drawable;
413 enum drm_vblank_seq_type seqtype;
414 unsigned int sequence;
415 } drm_i915_vblank_swap_t;
417 typedef struct drm_i915_hws_addr {
418 __u64 addr;
419 } drm_i915_hws_addr_t;
421 struct drm_i915_gem_init {
423 * Beginning offset in the GTT to be managed by the DRM memory
424 * manager.
426 __u64 gtt_start;
428 * Ending offset in the GTT to be managed by the DRM memory
429 * manager.
431 __u64 gtt_end;
434 struct drm_i915_gem_create {
436 * Requested size for the object.
438 * The (page-aligned) allocated size for the object will be returned.
440 __u64 size;
442 * Returned handle for the object.
444 * Object handles are nonzero.
446 __u32 handle;
447 __u32 pad;
450 struct drm_i915_gem_pread {
451 /** Handle for the object being read. */
452 __u32 handle;
453 __u32 pad;
454 /** Offset into the object to read from */
455 __u64 offset;
456 /** Length of data to read */
457 __u64 size;
459 * Pointer to write the data into.
461 * This is a fixed-size type for 32/64 compatibility.
463 __u64 data_ptr;
466 struct drm_i915_gem_pwrite {
467 /** Handle for the object being written to. */
468 __u32 handle;
469 __u32 pad;
470 /** Offset into the object to write to */
471 __u64 offset;
472 /** Length of data to write */
473 __u64 size;
475 * Pointer to read the data from.
477 * This is a fixed-size type for 32/64 compatibility.
479 __u64 data_ptr;
482 struct drm_i915_gem_mmap {
483 /** Handle for the object being mapped. */
484 __u32 handle;
485 __u32 pad;
486 /** Offset in the object to map. */
487 __u64 offset;
489 * Length of data to map.
491 * The value will be page-aligned.
493 __u64 size;
495 * Returned pointer the data was mapped at.
497 * This is a fixed-size type for 32/64 compatibility.
499 __u64 addr_ptr;
502 * Flags for extended behaviour.
504 * Added in version 2.
506 __u64 flags;
507 #define I915_MMAP_WC 0x1
510 struct drm_i915_gem_mmap_gtt {
511 /** Handle for the object being mapped. */
512 __u32 handle;
513 __u32 pad;
515 * Fake offset to use for subsequent mmap call
517 * This is a fixed-size type for 32/64 compatibility.
519 __u64 offset;
522 struct drm_i915_gem_set_domain {
523 /** Handle for the object */
524 __u32 handle;
526 /** New read domains */
527 __u32 read_domains;
529 /** New write domain */
530 __u32 write_domain;
533 struct drm_i915_gem_sw_finish {
534 /** Handle for the object */
535 __u32 handle;
538 struct drm_i915_gem_relocation_entry {
540 * Handle of the buffer being pointed to by this relocation entry.
542 * It's appealing to make this be an index into the mm_validate_entry
543 * list to refer to the buffer, but this allows the driver to create
544 * a relocation list for state buffers and not re-write it per
545 * exec using the buffer.
547 __u32 target_handle;
550 * Value to be added to the offset of the target buffer to make up
551 * the relocation entry.
553 __u32 delta;
555 /** Offset in the buffer the relocation entry will be written into */
556 __u64 offset;
559 * Offset value of the target buffer that the relocation entry was last
560 * written as.
562 * If the buffer has the same offset as last time, we can skip syncing
563 * and writing the relocation. This value is written back out by
564 * the execbuffer ioctl when the relocation is written.
566 __u64 presumed_offset;
569 * Target memory domains read by this operation.
571 __u32 read_domains;
574 * Target memory domains written by this operation.
576 * Note that only one domain may be written by the whole
577 * execbuffer operation, so that where there are conflicts,
578 * the application will get -EINVAL back.
580 __u32 write_domain;
583 /** @{
584 * Intel memory domains
586 * Most of these just align with the various caches in
587 * the system and are used to flush and invalidate as
588 * objects end up cached in different domains.
590 /** CPU cache */
591 #define I915_GEM_DOMAIN_CPU 0x00000001
592 /** Render cache, used by 2D and 3D drawing */
593 #define I915_GEM_DOMAIN_RENDER 0x00000002
594 /** Sampler cache, used by texture engine */
595 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
596 /** Command queue, used to load batch buffers */
597 #define I915_GEM_DOMAIN_COMMAND 0x00000008
598 /** Instruction cache, used by shader programs */
599 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
600 /** Vertex address cache */
601 #define I915_GEM_DOMAIN_VERTEX 0x00000020
602 /** GTT domain - aperture and scanout */
603 #define I915_GEM_DOMAIN_GTT 0x00000040
604 /** @} */
606 struct drm_i915_gem_exec_object {
608 * User's handle for a buffer to be bound into the GTT for this
609 * operation.
611 __u32 handle;
613 /** Number of relocations to be performed on this buffer */
614 __u32 relocation_count;
616 * Pointer to array of struct drm_i915_gem_relocation_entry containing
617 * the relocations to be performed in this buffer.
619 __u64 relocs_ptr;
621 /** Required alignment in graphics aperture */
622 __u64 alignment;
625 * Returned value of the updated offset of the object, for future
626 * presumed_offset writes.
628 __u64 offset;
631 struct drm_i915_gem_execbuffer {
633 * List of buffers to be validated with their relocations to be
634 * performend on them.
636 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
638 * These buffers must be listed in an order such that all relocations
639 * a buffer is performing refer to buffers that have already appeared
640 * in the validate list.
642 __u64 buffers_ptr;
643 __u32 buffer_count;
645 /** Offset in the batchbuffer to start execution from. */
646 __u32 batch_start_offset;
647 /** Bytes used in batchbuffer from batch_start_offset */
648 __u32 batch_len;
649 __u32 DR1;
650 __u32 DR4;
651 __u32 num_cliprects;
652 /** This is a struct drm_clip_rect *cliprects */
653 __u64 cliprects_ptr;
656 struct drm_i915_gem_exec_object2 {
658 * User's handle for a buffer to be bound into the GTT for this
659 * operation.
661 __u32 handle;
663 /** Number of relocations to be performed on this buffer */
664 __u32 relocation_count;
666 * Pointer to array of struct drm_i915_gem_relocation_entry containing
667 * the relocations to be performed in this buffer.
669 __u64 relocs_ptr;
671 /** Required alignment in graphics aperture */
672 __u64 alignment;
675 * Returned value of the updated offset of the object, for future
676 * presumed_offset writes.
678 __u64 offset;
680 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
681 #define EXEC_OBJECT_NEEDS_GTT (1<<1)
682 #define EXEC_OBJECT_WRITE (1<<2)
683 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
684 __u64 flags;
686 __u64 rsvd1;
687 __u64 rsvd2;
690 struct drm_i915_gem_execbuffer2 {
692 * List of gem_exec_object2 structs
694 __u64 buffers_ptr;
695 __u32 buffer_count;
697 /** Offset in the batchbuffer to start execution from. */
698 __u32 batch_start_offset;
699 /** Bytes used in batchbuffer from batch_start_offset */
700 __u32 batch_len;
701 __u32 DR1;
702 __u32 DR4;
703 __u32 num_cliprects;
704 /** This is a struct drm_clip_rect *cliprects */
705 __u64 cliprects_ptr;
706 #define I915_EXEC_RING_MASK (7<<0)
707 #define I915_EXEC_DEFAULT (0<<0)
708 #define I915_EXEC_RENDER (1<<0)
709 #define I915_EXEC_BSD (2<<0)
710 #define I915_EXEC_BLT (3<<0)
711 #define I915_EXEC_VEBOX (4<<0)
713 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
714 * Gen6+ only supports relative addressing to dynamic state (default) and
715 * absolute addressing.
717 * These flags are ignored for the BSD and BLT rings.
719 #define I915_EXEC_CONSTANTS_MASK (3<<6)
720 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
721 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
722 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
723 __u64 flags;
724 __u64 rsvd1; /* now used for context info */
725 __u64 rsvd2;
728 /** Resets the SO write offset registers for transform feedback on gen7. */
729 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
731 /** Request a privileged ("secure") batch buffer. Note only available for
732 * DRM_ROOT_ONLY | DRM_MASTER processes.
734 #define I915_EXEC_SECURE (1<<9)
736 /** Inform the kernel that the batch is and will always be pinned. This
737 * negates the requirement for a workaround to be performed to avoid
738 * an incoherent CS (such as can be found on 830/845). If this flag is
739 * not passed, the kernel will endeavour to make sure the batch is
740 * coherent with the CS before execution. If this flag is passed,
741 * userspace assumes the responsibility for ensuring the same.
743 #define I915_EXEC_IS_PINNED (1<<10)
745 /** Provide a hint to the kernel that the command stream and auxiliary
746 * state buffers already holds the correct presumed addresses and so the
747 * relocation process may be skipped if no buffers need to be moved in
748 * preparation for the execbuffer.
750 #define I915_EXEC_NO_RELOC (1<<11)
752 /** Use the reloc.handle as an index into the exec object array rather
753 * than as the per-file handle.
755 #define I915_EXEC_HANDLE_LUT (1<<12)
757 /** Used for switching BSD rings on the platforms with two BSD rings */
758 #define I915_EXEC_BSD_MASK (3<<13)
759 #define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */
760 #define I915_EXEC_BSD_RING1 (1<<13)
761 #define I915_EXEC_BSD_RING2 (2<<13)
763 #define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
765 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
766 #define i915_execbuffer2_set_context_id(eb2, context) \
767 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
768 #define i915_execbuffer2_get_context_id(eb2) \
769 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
771 struct drm_i915_gem_pin {
772 /** Handle of the buffer to be pinned. */
773 __u32 handle;
774 __u32 pad;
776 /** alignment required within the aperture */
777 __u64 alignment;
779 /** Returned GTT offset of the buffer. */
780 __u64 offset;
783 struct drm_i915_gem_unpin {
784 /** Handle of the buffer to be unpinned. */
785 __u32 handle;
786 __u32 pad;
789 struct drm_i915_gem_busy {
790 /** Handle of the buffer to check for busy */
791 __u32 handle;
793 /** Return busy status (1 if busy, 0 if idle).
794 * The high word is used to indicate on which rings the object
795 * currently resides:
796 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
798 __u32 busy;
802 * I915_CACHING_NONE
804 * GPU access is not coherent with cpu caches. Default for machines without an
805 * LLC.
807 #define I915_CACHING_NONE 0
809 * I915_CACHING_CACHED
811 * GPU access is coherent with cpu caches and furthermore the data is cached in
812 * last-level caches shared between cpu cores and the gpu GT. Default on
813 * machines with HAS_LLC.
815 #define I915_CACHING_CACHED 1
817 * I915_CACHING_DISPLAY
819 * Special GPU caching mode which is coherent with the scanout engines.
820 * Transparently falls back to I915_CACHING_NONE on platforms where no special
821 * cache mode (like write-through or gfdt flushing) is available. The kernel
822 * automatically sets this mode when using a buffer as a scanout target.
823 * Userspace can manually set this mode to avoid a costly stall and clflush in
824 * the hotpath of drawing the first frame.
826 #define I915_CACHING_DISPLAY 2
828 struct drm_i915_gem_caching {
830 * Handle of the buffer to set/get the caching level of. */
831 __u32 handle;
834 * Cacheing level to apply or return value
836 * bits0-15 are for generic caching control (i.e. the above defined
837 * values). bits16-31 are reserved for platform-specific variations
838 * (e.g. l3$ caching on gen7). */
839 __u32 caching;
842 #define I915_TILING_NONE 0
843 #define I915_TILING_X 1
844 #define I915_TILING_Y 2
846 #define I915_BIT_6_SWIZZLE_NONE 0
847 #define I915_BIT_6_SWIZZLE_9 1
848 #define I915_BIT_6_SWIZZLE_9_10 2
849 #define I915_BIT_6_SWIZZLE_9_11 3
850 #define I915_BIT_6_SWIZZLE_9_10_11 4
851 /* Not seen by userland */
852 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
853 /* Seen by userland. */
854 #define I915_BIT_6_SWIZZLE_9_17 6
855 #define I915_BIT_6_SWIZZLE_9_10_17 7
857 struct drm_i915_gem_set_tiling {
858 /** Handle of the buffer to have its tiling state updated */
859 __u32 handle;
862 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
863 * I915_TILING_Y).
865 * This value is to be set on request, and will be updated by the
866 * kernel on successful return with the actual chosen tiling layout.
868 * The tiling mode may be demoted to I915_TILING_NONE when the system
869 * has bit 6 swizzling that can't be managed correctly by GEM.
871 * Buffer contents become undefined when changing tiling_mode.
873 __u32 tiling_mode;
876 * Stride in bytes for the object when in I915_TILING_X or
877 * I915_TILING_Y.
879 __u32 stride;
882 * Returned address bit 6 swizzling required for CPU access through
883 * mmap mapping.
885 __u32 swizzle_mode;
888 struct drm_i915_gem_get_tiling {
889 /** Handle of the buffer to get tiling state for. */
890 __u32 handle;
893 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
894 * I915_TILING_Y).
896 __u32 tiling_mode;
899 * Returned address bit 6 swizzling required for CPU access through
900 * mmap mapping.
902 __u32 swizzle_mode;
905 * Returned address bit 6 swizzling required for CPU access through
906 * mmap mapping whilst bound.
908 __u32 phys_swizzle_mode;
911 struct drm_i915_gem_get_aperture {
912 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
913 __u64 aper_size;
916 * Available space in the aperture used by i915_gem_execbuffer, in
917 * bytes
919 __u64 aper_available_size;
922 struct drm_i915_get_pipe_from_crtc_id {
923 /** ID of CRTC being requested **/
924 __u32 crtc_id;
926 /** pipe of requested CRTC **/
927 __u32 pipe;
930 #define I915_MADV_WILLNEED 0
931 #define I915_MADV_DONTNEED 1
932 #define __I915_MADV_PURGED 2 /* internal state */
934 struct drm_i915_gem_madvise {
935 /** Handle of the buffer to change the backing store advice */
936 __u32 handle;
938 /* Advice: either the buffer will be needed again in the near future,
939 * or wont be and could be discarded under memory pressure.
941 __u32 madv;
943 /** Whether the backing store still exists. */
944 __u32 retained;
947 /* flags */
948 #define I915_OVERLAY_TYPE_MASK 0xff
949 #define I915_OVERLAY_YUV_PLANAR 0x01
950 #define I915_OVERLAY_YUV_PACKED 0x02
951 #define I915_OVERLAY_RGB 0x03
953 #define I915_OVERLAY_DEPTH_MASK 0xff00
954 #define I915_OVERLAY_RGB24 0x1000
955 #define I915_OVERLAY_RGB16 0x2000
956 #define I915_OVERLAY_RGB15 0x3000
957 #define I915_OVERLAY_YUV422 0x0100
958 #define I915_OVERLAY_YUV411 0x0200
959 #define I915_OVERLAY_YUV420 0x0300
960 #define I915_OVERLAY_YUV410 0x0400
962 #define I915_OVERLAY_SWAP_MASK 0xff0000
963 #define I915_OVERLAY_NO_SWAP 0x000000
964 #define I915_OVERLAY_UV_SWAP 0x010000
965 #define I915_OVERLAY_Y_SWAP 0x020000
966 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
968 #define I915_OVERLAY_FLAGS_MASK 0xff000000
969 #define I915_OVERLAY_ENABLE 0x01000000
971 struct drm_intel_overlay_put_image {
972 /* various flags and src format description */
973 __u32 flags;
974 /* source picture description */
975 __u32 bo_handle;
976 /* stride values and offsets are in bytes, buffer relative */
977 __u16 stride_Y; /* stride for packed formats */
978 __u16 stride_UV;
979 __u32 offset_Y; /* offset for packet formats */
980 __u32 offset_U;
981 __u32 offset_V;
982 /* in pixels */
983 __u16 src_width;
984 __u16 src_height;
985 /* to compensate the scaling factors for partially covered surfaces */
986 __u16 src_scan_width;
987 __u16 src_scan_height;
988 /* output crtc description */
989 __u32 crtc_id;
990 __u16 dst_x;
991 __u16 dst_y;
992 __u16 dst_width;
993 __u16 dst_height;
996 /* flags */
997 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
998 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
999 struct drm_intel_overlay_attrs {
1000 __u32 flags;
1001 __u32 color_key;
1002 __s32 brightness;
1003 __u32 contrast;
1004 __u32 saturation;
1005 __u32 gamma0;
1006 __u32 gamma1;
1007 __u32 gamma2;
1008 __u32 gamma3;
1009 __u32 gamma4;
1010 __u32 gamma5;
1014 * Intel sprite handling
1016 * Color keying works with a min/mask/max tuple. Both source and destination
1017 * color keying is allowed.
1019 * Source keying:
1020 * Sprite pixels within the min & max values, masked against the color channels
1021 * specified in the mask field, will be transparent. All other pixels will
1022 * be displayed on top of the primary plane. For RGB surfaces, only the min
1023 * and mask fields will be used; ranged compares are not allowed.
1025 * Destination keying:
1026 * Primary plane pixels that match the min value, masked against the color
1027 * channels specified in the mask field, will be replaced by corresponding
1028 * pixels from the sprite plane.
1030 * Note that source & destination keying are exclusive; only one can be
1031 * active on a given plane.
1034 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
1035 #define I915_SET_COLORKEY_DESTINATION (1<<1)
1036 #define I915_SET_COLORKEY_SOURCE (1<<2)
1037 struct drm_intel_sprite_colorkey {
1038 __u32 plane_id;
1039 __u32 min_value;
1040 __u32 channel_mask;
1041 __u32 max_value;
1042 __u32 flags;
1045 struct drm_i915_gem_wait {
1046 /** Handle of BO we shall wait on */
1047 __u32 bo_handle;
1048 __u32 flags;
1049 /** Number of nanoseconds to wait, Returns time remaining. */
1050 __s64 timeout_ns;
1053 struct drm_i915_gem_context_create {
1054 /* output: id of new context*/
1055 __u32 ctx_id;
1056 __u32 pad;
1059 struct drm_i915_gem_context_destroy {
1060 __u32 ctx_id;
1061 __u32 pad;
1064 struct drm_i915_reg_read {
1065 __u64 offset;
1066 __u64 val; /* Return value */
1068 /* Known registers:
1070 * Render engine timestamp - 0x2358 + 64bit - gen7+
1071 * - Note this register returns an invalid value if using the default
1072 * single instruction 8byte read, in order to workaround that use
1073 * offset (0x2538 | 1) instead.
1077 struct drm_i915_reset_stats {
1078 __u32 ctx_id;
1079 __u32 flags;
1081 /* All resets since boot/module reload, for all contexts */
1082 __u32 reset_count;
1084 /* Number of batches lost when active in GPU, for this context */
1085 __u32 batch_active;
1087 /* Number of batches lost pending for execution, for this context */
1088 __u32 batch_pending;
1090 __u32 pad;
1093 struct drm_i915_gem_userptr {
1094 __u64 user_ptr;
1095 __u64 user_size;
1096 __u32 flags;
1097 #define I915_USERPTR_READ_ONLY 0x1
1098 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1100 * Returned handle for the object.
1102 * Object handles are nonzero.
1104 __u32 handle;
1107 struct drm_i915_gem_context_param {
1108 __u32 ctx_id;
1109 __u32 size;
1110 __u64 param;
1111 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1112 __u64 value;
1115 #endif /* _UAPI_I915_DRM_H_ */