drivers/usb/host/fusbh200.h

   1 #ifndef __LINUX_FUSBH200_H
   2 #define __LINUX_FUSBH200_H
   3
   4 /* definitions used for the EHCI driver */
   5
   6 /*
   7  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
   8  * __leXX (normally) or __beXX (given FUSBH200_BIG_ENDIAN_DESC), depending on
   9  * the host controller implementation.
  10  *
  11  * To facilitate the strongest possible byte-order checking from "sparse"
  12  * and so on, we use __leXX unless that's not practical.
  13  */
  14 #define __hc32  __le32
  15 #define __hc16  __le16
  16
  17 /* statistics can be kept for tuning/monitoring */
  18 struct fusbh200_stats {
  19         /* irq usage */
  20         unsigned long           normal;
  21         unsigned long           error;
  22         unsigned long           iaa;
  23         unsigned long           lost_iaa;
  24
  25         /* termination of urbs from core */
  26         unsigned long           complete;
  27         unsigned long           unlink;
  28 };
  29
  30 /* fusbh200_hcd->lock guards shared data against other CPUs:
  31  *   fusbh200_hcd:      async, unlink, periodic (and shadow), ...
  32  *   usb_host_endpoint: hcpriv
  33  *   fusbh200_qh:       qh_next, qtd_list
  34  *   fusbh200_qtd:      qtd_list
  35  *
  36  * Also, hold this lock when talking to HC registers or
  37  * when updating hw_* fields in shared qh/qtd/... structures.
  38  */
  39
  40 #define FUSBH200_MAX_ROOT_PORTS 1               /* see HCS_N_PORTS */
  41
  42 /*
  43  * fusbh200_rh_state values of FUSBH200_RH_RUNNING or above mean that the
  44  * controller may be doing DMA.  Lower values mean there's no DMA.
  45  */
  46 enum fusbh200_rh_state {
  47         FUSBH200_RH_HALTED,
  48         FUSBH200_RH_SUSPENDED,
  49         FUSBH200_RH_RUNNING,
  50         FUSBH200_RH_STOPPING
  51 };
  52
  53 /*
  54  * Timer events, ordered by increasing delay length.
  55  * Always update event_delays_ns[] and event_handlers[] (defined in
  56  * ehci-timer.c) in parallel with this list.
  57  */
  58 enum fusbh200_hrtimer_event {
  59         FUSBH200_HRTIMER_POLL_ASS,              /* Poll for async schedule off */
  60         FUSBH200_HRTIMER_POLL_PSS,              /* Poll for periodic schedule off */
  61         FUSBH200_HRTIMER_POLL_DEAD,             /* Wait for dead controller to stop */
  62         FUSBH200_HRTIMER_UNLINK_INTR,   /* Wait for interrupt QH unlink */
  63         FUSBH200_HRTIMER_FREE_ITDS,             /* Wait for unused iTDs and siTDs */
  64         FUSBH200_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
  65         FUSBH200_HRTIMER_IAA_WATCHDOG,  /* Handle lost IAA interrupts */
  66         FUSBH200_HRTIMER_DISABLE_PERIODIC,      /* Wait to disable periodic sched */
  67         FUSBH200_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
  68         FUSBH200_HRTIMER_IO_WATCHDOG,   /* Check for missing IRQs */
  69         FUSBH200_HRTIMER_NUM_EVENTS             /* Must come last */
  70 };
  71 #define FUSBH200_HRTIMER_NO_EVENT       99
  72
  73 struct fusbh200_hcd {                   /* one per controller */
  74         /* timing support */
  75         enum fusbh200_hrtimer_event     next_hrtimer_event;
  76         unsigned                enabled_hrtimer_events;
  77         ktime_t                 hr_timeouts[FUSBH200_HRTIMER_NUM_EVENTS];
  78         struct hrtimer          hrtimer;
  79
  80         int                     PSS_poll_count;
  81         int                     ASS_poll_count;
  82         int                     died_poll_count;
  83
  84         /* glue to PCI and HCD framework */
  85         struct fusbh200_caps __iomem *caps;
  86         struct fusbh200_regs __iomem *regs;
  87         struct fusbh200_dbg_port __iomem *debug;
  88
  89         __u32                   hcs_params;     /* cached register copy */
  90         spinlock_t              lock;
  91         enum fusbh200_rh_state  rh_state;
  92
  93         /* general schedule support */
  94         bool                    scanning:1;
  95         bool                    need_rescan:1;
  96         bool                    intr_unlinking:1;
  97         bool                    async_unlinking:1;
  98         bool                    shutdown:1;
  99         struct fusbh200_qh              *qh_scan_next;
 100
 101         /* async schedule support */
 102         struct fusbh200_qh              *async;
 103         struct fusbh200_qh              *dummy;         /* For AMD quirk use */
 104         struct fusbh200_qh              *async_unlink;
 105         struct fusbh200_qh              *async_unlink_last;
 106         struct fusbh200_qh              *async_iaa;
 107         unsigned                async_unlink_cycle;
 108         unsigned                async_count;    /* async activity count */
 109
 110         /* periodic schedule support */
 111 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
 112         unsigned                periodic_size;
 113         __hc32                  *periodic;      /* hw periodic table */
 114         dma_addr_t              periodic_dma;
 115         struct list_head        intr_qh_list;
 116         unsigned                i_thresh;       /* uframes HC might cache */
 117
 118         union fusbh200_shadow   *pshadow;       /* mirror hw periodic table */
 119         struct fusbh200_qh              *intr_unlink;
 120         struct fusbh200_qh              *intr_unlink_last;
 121         unsigned                intr_unlink_cycle;
 122         unsigned                now_frame;      /* frame from HC hardware */
 123         unsigned                next_frame;     /* scan periodic, start here */
 124         unsigned                intr_count;     /* intr activity count */
 125         unsigned                isoc_count;     /* isoc activity count */
 126         unsigned                periodic_count; /* periodic activity count */
 127         unsigned                uframe_periodic_max; /* max periodic time per uframe */
 128
 129
 130         /* list of itds completed while now_frame was still active */
 131         struct list_head        cached_itd_list;
 132         struct fusbh200_itd     *last_itd_to_free;
 133
 134         /* per root hub port */
 135         unsigned long           reset_done [FUSBH200_MAX_ROOT_PORTS];
 136
 137         /* bit vectors (one bit per port) */
 138         unsigned long           bus_suspended;          /* which ports were
 139                         already suspended at the start of a bus suspend */
 140         unsigned long           companion_ports;        /* which ports are
 141                         dedicated to the companion controller */
 142         unsigned long           owned_ports;            /* which ports are
 143                         owned by the companion during a bus suspend */
 144         unsigned long           port_c_suspend;         /* which ports have
 145                         the change-suspend feature turned on */
 146         unsigned long           suspended_ports;        /* which ports are
 147                         suspended */
 148         unsigned long           resuming_ports;         /* which ports have
 149                         started to resume */
 150
 151         /* per-HC memory pools (could be per-bus, but ...) */
 152         struct dma_pool         *qh_pool;       /* qh per active urb */
 153         struct dma_pool         *qtd_pool;      /* one or more per qh */
 154         struct dma_pool         *itd_pool;      /* itd per iso urb */
 155
 156         unsigned                random_frame;
 157         unsigned long           next_statechange;
 158         ktime_t                 last_periodic_enable;
 159         u32                     command;
 160
 161         /* SILICON QUIRKS */
 162         unsigned                need_io_watchdog:1;
 163         unsigned                fs_i_thresh:1;  /* Intel iso scheduling */
 164
 165         u8                      sbrn;           /* packed release number */
 166
 167         /* irq statistics */
 168 #ifdef FUSBH200_STATS
 169         struct fusbh200_stats   stats;
 170 #       define COUNT(x) do { (x)++; } while (0)
 171 #else
 172 #       define COUNT(x) do {} while (0)
 173 #endif
 174
 175         /* debug files */
 176 #ifdef DEBUG
 177         struct dentry           *debug_dir;
 178 #endif
 179 };
 180
 181 /* convert between an HCD pointer and the corresponding FUSBH200_HCD */
 182 static inline struct fusbh200_hcd *hcd_to_fusbh200 (struct usb_hcd *hcd)
 183 {
 184         return (struct fusbh200_hcd *) (hcd->hcd_priv);
 185 }
 186 static inline struct usb_hcd *fusbh200_to_hcd (struct fusbh200_hcd *fusbh200)
 187 {
 188         return container_of ((void *) fusbh200, struct usb_hcd, hcd_priv);
 189 }
 190
 191 /*-------------------------------------------------------------------------*/
 192
 193 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 194
 195 /* Section 2.2 Host Controller Capability Registers */
 196 struct fusbh200_caps {
 197         /* these fields are specified as 8 and 16 bit registers,
 198          * but some hosts can't perform 8 or 16 bit PCI accesses.
 199          * some hosts treat caplength and hciversion as parts of a 32-bit
 200          * register, others treat them as two separate registers, this
 201          * affects the memory map for big endian controllers.
 202          */
 203         u32             hc_capbase;
 204 #define HC_LENGTH(fusbh200, p)  (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
 205                                 (fusbh200_big_endian_capbase(fusbh200) ? 24 : 0)))
 206 #define HC_VERSION(fusbh200, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
 207                                 (fusbh200_big_endian_capbase(fusbh200) ? 0 : 16)))
 208         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 209 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 210
 211         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 212 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 213 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 214         u8              portroute[8];    /* nibbles for routing - offset 0xC */
 215 };
 216
 217
 218 /* Section 2.3 Host Controller Operational Registers */
 219 struct fusbh200_regs {
 220
 221         /* USBCMD: offset 0x00 */
 222         u32             command;
 223
 224 /* EHCI 1.1 addendum */
 225 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 226 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 227 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 228 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 229 #define CMD_ASE         (1<<5)          /* async schedule enable */
 230 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 231 /* 3:2 is periodic frame list size */
 232 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 233 #define CMD_RUN         (1<<0)          /* start/stop HC */
 234
 235         /* USBSTS: offset 0x04 */
 236         u32             status;
 237 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 238 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 239 #define STS_RECL        (1<<13)         /* Reclamation */
 240 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 241 /* some bits reserved */
 242         /* these STS_* flags are also intr_enable bits (USBINTR) */
 243 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 244 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 245 #define STS_FLR         (1<<3)          /* frame list rolled over */
 246 #define STS_PCD         (1<<2)          /* port change detect */
 247 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 248 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 249
 250         /* USBINTR: offset 0x08 */
 251         u32             intr_enable;
 252
 253         /* FRINDEX: offset 0x0C */
 254         u32             frame_index;    /* current microframe number */
 255         /* CTRLDSSEGMENT: offset 0x10 */
 256         u32             segment;        /* address bits 63:32 if needed */
 257         /* PERIODICLISTBASE: offset 0x14 */
 258         u32             frame_list;     /* points to periodic list */
 259         /* ASYNCLISTADDR: offset 0x18 */
 260         u32             async_next;     /* address of next async queue head */
 261
 262         u32     reserved1;
 263         /* PORTSC: offset 0x20 */
 264         u32     port_status;
 265 /* 31:23 reserved */
 266 #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))        /* USB 1.1 device */
 267 #define PORT_RESET      (1<<8)          /* reset port */
 268 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 269 #define PORT_RESUME     (1<<6)          /* resume it */
 270 #define PORT_PEC        (1<<3)          /* port enable change */
 271 #define PORT_PE         (1<<2)          /* port enable */
 272 #define PORT_CSC        (1<<1)          /* connect status change */
 273 #define PORT_CONNECT    (1<<0)          /* device connected */
 274 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC)
 275
 276         u32     reserved2[3];
 277
 278         /* BMCSR: offset 0x30 */
 279         u32     bmcsr; /* Bus Moniter Control/Status Register */
 280 #define BMCSR_HOST_SPD_TYP      (3<<9)
 281 #define BMCSR_VBUS_OFF          (1<<4)
 282 #define BMCSR_INT_POLARITY      (1<<3)
 283
 284         /* BMISR: offset 0x34 */
 285         u32     bmisr; /* Bus Moniter Interrupt Status Register*/
 286 #define BMISR_OVC               (1<<1)
 287
 288         /* BMIER: offset 0x38 */
 289         u32     bmier; /* Bus Moniter Interrupt Enable Register */
 290 #define BMIER_OVC_EN            (1<<1)
 291 #define BMIER_VBUS_ERR_EN       (1<<0)
 292 };
 293
 294 /* Appendix C, Debug port ... intended for use with special "debug devices"
 295  * that can help if there's no serial console.  (nonstandard enumeration.)
 296  */
 297 struct fusbh200_dbg_port {
 298         u32     control;
 299 #define DBGP_OWNER      (1<<30)
 300 #define DBGP_ENABLED    (1<<28)
 301 #define DBGP_DONE       (1<<16)
 302 #define DBGP_INUSE      (1<<10)
 303 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 304 #       define DBGP_ERR_BAD     1
 305 #       define DBGP_ERR_SIGNAL  2
 306 #define DBGP_ERROR      (1<<6)
 307 #define DBGP_GO         (1<<5)
 308 #define DBGP_OUT        (1<<4)
 309 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 310         u32     pids;
 311 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 312 #define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
 313         u32     data03;
 314         u32     data47;
 315         u32     address;
 316 #define DBGP_EPADDR(dev, ep)    (((dev)<<8)|(ep))
 317 };
 318
 319 #ifdef CONFIG_EARLY_PRINTK_DBGP
 320 #include <linux/init.h>
 321 extern int __init early_dbgp_init(char *s);
 322 extern struct console early_dbgp_console;
 323 #endif /* CONFIG_EARLY_PRINTK_DBGP */
 324
 325 struct usb_hcd;
 326
 327 static inline int xen_dbgp_reset_prep(struct usb_hcd *hcd)
 328 {
 329         return 1; /* Shouldn't this be 0? */
 330 }
 331
 332 static inline int xen_dbgp_external_startup(struct usb_hcd *hcd)
 333 {
 334         return -1;
 335 }
 336
 337 #ifdef CONFIG_EARLY_PRINTK_DBGP
 338 /* Call backs from fusbh200 host driver to fusbh200 debug driver */
 339 extern int dbgp_external_startup(struct usb_hcd *);
 340 extern int dbgp_reset_prep(struct usb_hcd *hcd);
 341 #else
 342 static inline int dbgp_reset_prep(struct usb_hcd *hcd)
 343 {
 344         return xen_dbgp_reset_prep(hcd);
 345 }
 346 static inline int dbgp_external_startup(struct usb_hcd *hcd)
 347 {
 348         return xen_dbgp_external_startup(hcd);
 349 }
 350 #endif
 351
 352 /*-------------------------------------------------------------------------*/
 353
 354 #define QTD_NEXT(fusbh200, dma) cpu_to_hc32(fusbh200, (u32)dma)
 355
 356 /*
 357  * EHCI Specification 0.95 Section 3.5
 358  * QTD: describe data transfer components (buffer, direction, ...)
 359  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 360  *
 361  * These are associated only with "QH" (Queue Head) structures,
 362  * used with control, bulk, and interrupt transfers.
 363  */
 364 struct fusbh200_qtd {
 365         /* first part defined by EHCI spec */
 366         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 367         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 368         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 369 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 370 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 371 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 372 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 373 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 374 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 375 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 376 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 377 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 378 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 379 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 380 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 381 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 382
 383 #define ACTIVE_BIT(fusbh200)    cpu_to_hc32(fusbh200, QTD_STS_ACTIVE)
 384 #define HALT_BIT(fusbh200)              cpu_to_hc32(fusbh200, QTD_STS_HALT)
 385 #define STATUS_BIT(fusbh200)    cpu_to_hc32(fusbh200, QTD_STS_STS)
 386
 387         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 388         __hc32                  hw_buf_hi [5];        /* Appendix B */
 389
 390         /* the rest is HCD-private */
 391         dma_addr_t              qtd_dma;                /* qtd address */
 392         struct list_head        qtd_list;               /* sw qtd list */
 393         struct urb              *urb;                   /* qtd's urb */
 394         size_t                  length;                 /* length of buffer */
 395 } __attribute__ ((aligned (32)));
 396
 397 /* mask NakCnt+T in qh->hw_alt_next */
 398 #define QTD_MASK(fusbh200)      cpu_to_hc32 (fusbh200, ~0x1f)
 399
 400 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 401
 402 /*-------------------------------------------------------------------------*/
 403
 404 /* type tag from {qh,itd,fstn}->hw_next */
 405 #define Q_NEXT_TYPE(fusbh200,dma)       ((dma) & cpu_to_hc32(fusbh200, 3 << 1))
 406
 407 /*
 408  * Now the following defines are not converted using the
 409  * cpu_to_le32() macro anymore, since we have to support
 410  * "dynamic" switching between be and le support, so that the driver
 411  * can be used on one system with SoC EHCI controller using big-endian
 412  * descriptors as well as a normal little-endian PCI EHCI controller.
 413  */
 414 /* values for that type tag */
 415 #define Q_TYPE_ITD      (0 << 1)
 416 #define Q_TYPE_QH       (1 << 1)
 417 #define Q_TYPE_SITD     (2 << 1)
 418 #define Q_TYPE_FSTN     (3 << 1)
 419
 420 /* next async queue entry, or pointer to interrupt/periodic QH */
 421 #define QH_NEXT(fusbh200,dma)   (cpu_to_hc32(fusbh200, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 422
 423 /* for periodic/async schedules and qtd lists, mark end of list */
 424 #define FUSBH200_LIST_END(fusbh200)     cpu_to_hc32(fusbh200, 1) /* "null pointer" to hw */
 425
 426 /*
 427  * Entries in periodic shadow table are pointers to one of four kinds
 428  * of data structure.  That's dictated by the hardware; a type tag is
 429  * encoded in the low bits of the hardware's periodic schedule.  Use
 430  * Q_NEXT_TYPE to get the tag.
 431  *
 432  * For entries in the async schedule, the type tag always says "qh".
 433  */
 434 union fusbh200_shadow {
 435         struct fusbh200_qh      *qh;            /* Q_TYPE_QH */
 436         struct fusbh200_itd     *itd;           /* Q_TYPE_ITD */
 437         struct fusbh200_fstn    *fstn;          /* Q_TYPE_FSTN */
 438         __hc32                  *hw_next;       /* (all types) */
 439         void                    *ptr;
 440 };
 441
 442 /*-------------------------------------------------------------------------*/
 443
 444 /*
 445  * EHCI Specification 0.95 Section 3.6
 446  * QH: describes control/bulk/interrupt endpoints
 447  * See Fig 3-7 "Queue Head Structure Layout".
 448  *
 449  * These appear in both the async and (for interrupt) periodic schedules.
 450  */
 451
 452 /* first part defined by EHCI spec */
 453 struct fusbh200_qh_hw {
 454         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 455         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 456 #define QH_CONTROL_EP   (1 << 27)       /* FS/LS control endpoint */
 457 #define QH_HEAD         (1 << 15)       /* Head of async reclamation list */
 458 #define QH_TOGGLE_CTL   (1 << 14)       /* Data toggle control */
 459 #define QH_HIGH_SPEED   (2 << 12)       /* Endpoint speed */
 460 #define QH_LOW_SPEED    (1 << 12)
 461 #define QH_FULL_SPEED   (0 << 12)
 462 #define QH_INACTIVATE   (1 << 7)        /* Inactivate on next transaction */
 463         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 464 #define QH_SMASK        0x000000ff
 465 #define QH_CMASK        0x0000ff00
 466 #define QH_HUBADDR      0x007f0000
 467 #define QH_HUBPORT      0x3f800000
 468 #define QH_MULT         0xc0000000
 469         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 470
 471         /* qtd overlay (hardware parts of a struct fusbh200_qtd) */
 472         __hc32                  hw_qtd_next;
 473         __hc32                  hw_alt_next;
 474         __hc32                  hw_token;
 475         __hc32                  hw_buf [5];
 476         __hc32                  hw_buf_hi [5];
 477 } __attribute__ ((aligned(32)));
 478
 479 struct fusbh200_qh {
 480         struct fusbh200_qh_hw   *hw;            /* Must come first */
 481         /* the rest is HCD-private */
 482         dma_addr_t              qh_dma;         /* address of qh */
 483         union fusbh200_shadow   qh_next;        /* ptr to qh; or periodic */
 484         struct list_head        qtd_list;       /* sw qtd list */
 485         struct list_head        intr_node;      /* list of intr QHs */
 486         struct fusbh200_qtd             *dummy;
 487         struct fusbh200_qh              *unlink_next;   /* next on unlink list */
 488
 489         unsigned                unlink_cycle;
 490
 491         u8                      needs_rescan;   /* Dequeue during giveback */
 492         u8                      qh_state;
 493 #define QH_STATE_LINKED         1               /* HC sees this */
 494 #define QH_STATE_UNLINK         2               /* HC may still see this */
 495 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 496 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on unlink q */
 497 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 498
 499         u8                      xacterrs;       /* XactErr retry counter */
 500 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 501
 502         /* periodic schedule info */
 503         u8                      usecs;          /* intr bandwidth */
 504         u8                      gap_uf;         /* uframes split/csplit gap */
 505         u8                      c_usecs;        /* ... split completion bw */
 506         u16                     tt_usecs;       /* tt downstream bandwidth */
 507         unsigned short          period;         /* polling interval */
 508         unsigned short          start;          /* where polling starts */
 509 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 510
 511         struct usb_device       *dev;           /* access to TT */
 512         unsigned                is_out:1;       /* bulk or intr OUT */
 513         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 514 };
 515
 516 /*-------------------------------------------------------------------------*/
 517
 518 /* description of one iso transaction (up to 3 KB data if highspeed) */
 519 struct fusbh200_iso_packet {
 520         /* These will be copied to iTD when scheduling */
 521         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 522         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 523         u8                      cross;          /* buf crosses pages */
 524         /* for full speed OUT splits */
 525         u32                     buf1;
 526 };
 527
 528 /* temporary schedule data for packets from iso urbs (both speeds)
 529  * each packet is one logical usb transaction to the device (not TT),
 530  * beginning at stream->next_uframe
 531  */
 532 struct fusbh200_iso_sched {
 533         struct list_head        td_list;
 534         unsigned                span;
 535         struct fusbh200_iso_packet      packet [0];
 536 };
 537
 538 /*
 539  * fusbh200_iso_stream - groups all (s)itds for this endpoint.
 540  * acts like a qh would, if EHCI had them for ISO.
 541  */
 542 struct fusbh200_iso_stream {
 543         /* first field matches fusbh200_hq, but is NULL */
 544         struct fusbh200_qh_hw   *hw;
 545
 546         u8                      bEndpointAddress;
 547         u8                      highspeed;
 548         struct list_head        td_list;        /* queued itds */
 549         struct list_head        free_list;      /* list of unused itds */
 550         struct usb_device       *udev;
 551         struct usb_host_endpoint *ep;
 552
 553         /* output of (re)scheduling */
 554         int                     next_uframe;
 555         __hc32                  splits;
 556
 557         /* the rest is derived from the endpoint descriptor,
 558          * trusting urb->interval == f(epdesc->bInterval) and
 559          * including the extra info for hw_bufp[0..2]
 560          */
 561         u8                      usecs, c_usecs;
 562         u16                     interval;
 563         u16                     tt_usecs;
 564         u16                     maxp;
 565         u16                     raw_mask;
 566         unsigned                bandwidth;
 567
 568         /* This is used to initialize iTD's hw_bufp fields */
 569         __hc32                  buf0;
 570         __hc32                  buf1;
 571         __hc32                  buf2;
 572
 573         /* this is used to initialize sITD's tt info */
 574         __hc32                  address;
 575 };
 576
 577 /*-------------------------------------------------------------------------*/
 578
 579 /*
 580  * EHCI Specification 0.95 Section 3.3
 581  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 582  *
 583  * Schedule records for high speed iso xfers
 584  */
 585 struct fusbh200_itd {
 586         /* first part defined by EHCI spec */
 587         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 588         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 589 #define FUSBH200_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 590 #define FUSBH200_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 591 #define FUSBH200_ISOC_BABBLE        (1<<29)        /* babble detected */
 592 #define FUSBH200_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 593 #define FUSBH200_ITD_LENGTH(tok)        (((tok)>>16) & 0x0fff)
 594 #define FUSBH200_ITD_IOC                (1 << 15)       /* interrupt on complete */
 595
 596 #define ITD_ACTIVE(fusbh200)    cpu_to_hc32(fusbh200, FUSBH200_ISOC_ACTIVE)
 597
 598         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 599         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 600
 601         /* the rest is HCD-private */
 602         dma_addr_t              itd_dma;        /* for this itd */
 603         union fusbh200_shadow   itd_next;       /* ptr to periodic q entry */
 604
 605         struct urb              *urb;
 606         struct fusbh200_iso_stream      *stream;        /* endpoint's queue */
 607         struct list_head        itd_list;       /* list of stream's itds */
 608
 609         /* any/all hw_transactions here may be used by that urb */
 610         unsigned                frame;          /* where scheduled */
 611         unsigned                pg;
 612         unsigned                index[8];       /* in urb->iso_frame_desc */
 613 } __attribute__ ((aligned (32)));
 614
 615 /*-------------------------------------------------------------------------*/
 616
 617 /*
 618  * EHCI Specification 0.96 Section 3.7
 619  * Periodic Frame Span Traversal Node (FSTN)
 620  *
 621  * Manages split interrupt transactions (using TT) that span frame boundaries
 622  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 623  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 624  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 625  */
 626 struct fusbh200_fstn {
 627         __hc32                  hw_next;        /* any periodic q entry */
 628         __hc32                  hw_prev;        /* qh or FUSBH200_LIST_END */
 629
 630         /* the rest is HCD-private */
 631         dma_addr_t              fstn_dma;
 632         union fusbh200_shadow   fstn_next;      /* ptr to periodic q entry */
 633 } __attribute__ ((aligned (32)));
 634
 635 /*-------------------------------------------------------------------------*/
 636
 637 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
 638
 639 #define fusbh200_prepare_ports_for_controller_suspend(fusbh200, do_wakeup)      \
 640                 fusbh200_adjust_port_wakeup_flags(fusbh200, true, do_wakeup);
 641
 642 #define fusbh200_prepare_ports_for_controller_resume(fusbh200)                  \
 643                 fusbh200_adjust_port_wakeup_flags(fusbh200, false, false);
 644
 645 /*-------------------------------------------------------------------------*/
 646
 647 /*
 648  * Some EHCI controllers have a Transaction Translator built into the
 649  * root hub. This is a non-standard feature.  Each controller will need
 650  * to add code to the following inline functions, and call them as
 651  * needed (mostly in root hub code).
 652  */
 653
 654 static inline unsigned int
 655 fusbh200_get_speed(struct fusbh200_hcd *fusbh200, unsigned int portsc)
 656 {
 657         return (readl(&fusbh200->regs->bmcsr)
 658                 & BMCSR_HOST_SPD_TYP) >> 9;
 659 }
 660
 661 /* Returns the speed of a device attached to a port on the root hub. */
 662 static inline unsigned int
 663 fusbh200_port_speed(struct fusbh200_hcd *fusbh200, unsigned int portsc)
 664 {
 665         switch (fusbh200_get_speed(fusbh200, portsc)) {
 666         case 0:
 667                 return 0;
 668         case 1:
 669                 return USB_PORT_STAT_LOW_SPEED;
 670         case 2:
 671         default:
 672                 return USB_PORT_STAT_HIGH_SPEED;
 673         }
 674 }
 675
 676 /*-------------------------------------------------------------------------*/
 677
 678 #define fusbh200_has_fsl_portno_bug(e)          (0)
 679
 680 /*
 681  * While most USB host controllers implement their registers in
 682  * little-endian format, a minority (celleb companion chip) implement
 683  * them in big endian format.
 684  *
 685  * This attempts to support either format at compile time without a
 686  * runtime penalty, or both formats with the additional overhead
 687  * of checking a flag bit.
 688  *
 689  */
 690
 691 #define fusbh200_big_endian_mmio(e)     0
 692 #define fusbh200_big_endian_capbase(e)  0
 693
 694 static inline unsigned int fusbh200_readl(const struct fusbh200_hcd *fusbh200,
 695                 __u32 __iomem * regs)
 696 {
 697         return readl(regs);
 698 }
 699
 700 static inline void fusbh200_writel(const struct fusbh200_hcd *fusbh200,
 701                 const unsigned int val, __u32 __iomem *regs)
 702 {
 703         writel(val, regs);
 704 }
 705
 706 /* cpu to fusbh200 */
 707 static inline __hc32 cpu_to_hc32 (const struct fusbh200_hcd *fusbh200, const u32 x)
 708 {
 709         return cpu_to_le32(x);
 710 }
 711
 712 /* fusbh200 to cpu */
 713 static inline u32 hc32_to_cpu (const struct fusbh200_hcd *fusbh200, const __hc32 x)
 714 {
 715         return le32_to_cpu(x);
 716 }
 717
 718 static inline u32 hc32_to_cpup (const struct fusbh200_hcd *fusbh200, const __hc32 *x)
 719 {
 720         return le32_to_cpup(x);
 721 }
 722
 723 /*-------------------------------------------------------------------------*/
 724
 725 static inline unsigned fusbh200_read_frame_index(struct fusbh200_hcd *fusbh200)
 726 {
 727         return fusbh200_readl(fusbh200, &fusbh200->regs->frame_index);
 728 }
 729
 730 #define fusbh200_itdlen(urb, desc, t) ({                        \
 731         usb_pipein((urb)->pipe) ?                               \
 732         (desc)->length - FUSBH200_ITD_LENGTH(t) :                       \
 733         FUSBH200_ITD_LENGTH(t);                                 \
 734 })
 735 /*-------------------------------------------------------------------------*/
 736
 737 #ifndef DEBUG
 738 #define STUB_DEBUG_FILES
 739 #endif  /* DEBUG */
 740
 741 /*-------------------------------------------------------------------------*/
 742
 743 #endif /* __LINUX_FUSBH200_H */