arch/arm/mach-davinci/include/mach/mux.h

   1 /*
   2  * Table of the DAVINCI register configurations for the PINMUX combinations
   3  *
   4  * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
   5  *
   6  * Based on linux/include/asm-arm/arch-omap/mux.h:
   7  * Copyright (C) 2003 - 2005 Nokia Corporation
   8  *
   9  * Written by Tony Lindgren
  10  *
  11  * 2007 (c) MontaVista Software, Inc. This file is licensed under
  12  * the terms of the GNU General Public License version 2. This program
  13  * is licensed "as is" without any warranty of any kind, whether express
  14  * or implied.
  15  *
  16  * Copyright (C) 2008 Texas Instruments.
  17  */
  18
  19 #ifndef __INC_MACH_MUX_H
  20 #define __INC_MACH_MUX_H
  21
  22 struct mux_config {
  23         const char *name;
  24         const char *mux_reg_name;
  25         const unsigned char mux_reg;
  26         const unsigned char mask_offset;
  27         const unsigned char mask;
  28         const unsigned char mode;
  29         bool debug;
  30 };
  31
  32 enum davinci_dm644x_index {
  33         /* ATA and HDDIR functions */
  34         DM644X_HDIREN,
  35         DM644X_ATAEN,
  36         DM644X_ATAEN_DISABLE,
  37
  38         /* HPI functions */
  39         DM644X_HPIEN_DISABLE,
  40
  41         /* AEAW functions */
  42         DM644X_AEAW,
  43
  44         /* Memory Stick */
  45         DM644X_MSTK,
  46
  47         /* I2C */
  48         DM644X_I2C,
  49
  50         /* ASP function */
  51         DM644X_MCBSP,
  52
  53         /* UART1 */
  54         DM644X_UART1,
  55
  56         /* UART2 */
  57         DM644X_UART2,
  58
  59         /* PWM0 */
  60         DM644X_PWM0,
  61
  62         /* PWM1 */
  63         DM644X_PWM1,
  64
  65         /* PWM2 */
  66         DM644X_PWM2,
  67
  68         /* VLYNQ function */
  69         DM644X_VLYNQEN,
  70         DM644X_VLSCREN,
  71         DM644X_VLYNQWD,
  72
  73         /* EMAC and MDIO function */
  74         DM644X_EMACEN,
  75
  76         /* GPIO3V[0:16] pins */
  77         DM644X_GPIO3V,
  78
  79         /* GPIO pins */
  80         DM644X_GPIO0,
  81         DM644X_GPIO3,
  82         DM644X_GPIO43_44,
  83         DM644X_GPIO46_47,
  84
  85         /* VPBE */
  86         DM644X_RGB666,
  87
  88         /* LCD */
  89         DM644X_LOEEN,
  90         DM644X_LFLDEN,
  91 };
  92
  93 enum davinci_dm646x_index {
  94         /* ATA function */
  95         DM646X_ATAEN,
  96
  97         /* AUDIO Clock */
  98         DM646X_AUDCK1,
  99         DM646X_AUDCK0,
 100
 101         /* CRGEN Control */
 102         DM646X_CRGMUX,
 103
 104         /* VPIF Control */
 105         DM646X_STSOMUX_DISABLE,
 106         DM646X_STSIMUX_DISABLE,
 107         DM646X_PTSOMUX_DISABLE,
 108         DM646X_PTSIMUX_DISABLE,
 109
 110         /* TSIF Control */
 111         DM646X_STSOMUX,
 112         DM646X_STSIMUX,
 113         DM646X_PTSOMUX_PARALLEL,
 114         DM646X_PTSIMUX_PARALLEL,
 115         DM646X_PTSOMUX_SERIAL,
 116         DM646X_PTSIMUX_SERIAL,
 117 };
 118
 119 enum davinci_dm355_index {
 120         /* MMC/SD 0 */
 121         DM355_MMCSD0,
 122
 123         /* MMC/SD 1 */
 124         DM355_SD1_CLK,
 125         DM355_SD1_CMD,
 126         DM355_SD1_DATA3,
 127         DM355_SD1_DATA2,
 128         DM355_SD1_DATA1,
 129         DM355_SD1_DATA0,
 130
 131         /* I2C */
 132         DM355_I2C_SDA,
 133         DM355_I2C_SCL,
 134
 135         /* ASP0 function */
 136         DM355_MCBSP0_BDX,
 137         DM355_MCBSP0_X,
 138         DM355_MCBSP0_BFSX,
 139         DM355_MCBSP0_BDR,
 140         DM355_MCBSP0_R,
 141         DM355_MCBSP0_BFSR,
 142
 143         /* SPI0 */
 144         DM355_SPI0_SDI,
 145         DM355_SPI0_SDENA0,
 146         DM355_SPI0_SDENA1,
 147
 148         /* IRQ muxing */
 149         DM355_INT_EDMA_CC,
 150         DM355_INT_EDMA_TC0_ERR,
 151         DM355_INT_EDMA_TC1_ERR,
 152
 153         /* EDMA event muxing */
 154         DM355_EVT8_ASP1_TX,
 155         DM355_EVT9_ASP1_RX,
 156         DM355_EVT26_MMC0_RX,
 157 };
 158
 159 #ifdef CONFIG_DAVINCI_MUX
 160 /* setup pin muxing */
 161 extern int davinci_cfg_reg(unsigned long reg_cfg);
 162 #else
 163 /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
 164 static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
 165 #endif
 166
 167 #endif /* __INC_MACH_MUX_H */