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debugfs: Modified default dir of debugfs for debugging UHCI.
[linux/fpc-iii.git] / arch / arm / mach-omap2 / serial.c
blobce22344b94e73929e67c43f39418776e4c88c08b
1 /*
2 * arch/arm/mach-omap2/serial.c
3 *
4 * OMAP2 serial support.
5 *
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * Major rework for PM support by Kevin Hilman
10 *
11 * Based off of arch/arm/mach-omap/omap1/serial.c
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
25 #include <linux/io.h>
26
27 #include <mach/common.h>
28 #include <mach/board.h>
29 #include <mach/clock.h>
30 #include <mach/control.h>
31
32 #include "prm.h"
33 #include "pm.h"
34 #include "prm-regbits-34xx.h"
35
36 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
37
38 #define DEFAULT_TIMEOUT (5 * HZ)
39
40 struct omap_uart_state {
41 int num;
42 int can_sleep;
43 struct timer_list timer;
44 u32 timeout;
45
46 void __iomem *wk_st;
47 void __iomem *wk_en;
48 u32 wk_mask;
49 u32 padconf;
50
51 struct clk *ick;
52 struct clk *fck;
53 int clocked;
54
55 struct plat_serial8250_port *p;
56 struct list_head node;
57 struct platform_device pdev;
58
59 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
60 int context_valid;
61
62 /* Registers to be saved/restored for OFF-mode */
63 u16 dll;
64 u16 dlh;
65 u16 ier;
66 u16 sysc;
67 u16 scr;
68 u16 wer;
69 #endif
70 };
71
72 static LIST_HEAD(uart_list);
73
74 static struct plat_serial8250_port serial_platform_data0[] = {
75 {
76 .membase = IO_ADDRESS(OMAP_UART1_BASE),
77 .mapbase = OMAP_UART1_BASE,
78 .irq = 72,
79 .flags = UPF_BOOT_AUTOCONF,
80 .iotype = UPIO_MEM,
81 .regshift = 2,
82 .uartclk = OMAP24XX_BASE_BAUD * 16,
83 }, {
84 .flags = 0
85 }
86 };
87
88 static struct plat_serial8250_port serial_platform_data1[] = {
89 {
90 .membase = IO_ADDRESS(OMAP_UART2_BASE),
91 .mapbase = OMAP_UART2_BASE,
92 .irq = 73,
93 .flags = UPF_BOOT_AUTOCONF,
94 .iotype = UPIO_MEM,
95 .regshift = 2,
96 .uartclk = OMAP24XX_BASE_BAUD * 16,
97 }, {
98 .flags = 0
99 }
100 };
101
102 static struct plat_serial8250_port serial_platform_data2[] = {
103 {
104 .membase = IO_ADDRESS(OMAP_UART3_BASE),
105 .mapbase = OMAP_UART3_BASE,
106 .irq = 74,
107 .flags = UPF_BOOT_AUTOCONF,
108 .iotype = UPIO_MEM,
109 .regshift = 2,
110 .uartclk = OMAP24XX_BASE_BAUD * 16,
111 }, {
112 #ifdef CONFIG_ARCH_OMAP4
113 .membase = IO_ADDRESS(OMAP_UART4_BASE),
114 .mapbase = OMAP_UART4_BASE,
115 .irq = 70,
116 .flags = UPF_BOOT_AUTOCONF,
117 .iotype = UPIO_MEM,
118 .regshift = 2,
119 .uartclk = OMAP24XX_BASE_BAUD * 16,
120 }, {
121 #endif
122 .flags = 0
123 }
124 };
125
126 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
127 int offset)
128 {
129 offset <<= up->regshift;
130 return (unsigned int)__raw_readb(up->membase + offset);
131 }
132
133 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
134 int value)
135 {
136 offset <<= p->regshift;
137 __raw_writeb(value, p->membase + offset);
138 }
139
140 /*
141 * Internal UARTs need to be initialized for the 8250 autoconfig to work
142 * properly. Note that the TX watermark initialization may not be needed
143 * once the 8250.c watermark handling code is merged.
144 */
145 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
146 {
147 struct plat_serial8250_port *p = uart->p;
148
149 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
150 serial_write_reg(p, UART_OMAP_SCR, 0x08);
151 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
152 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
153 }
154
155 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
156
157 static int enable_off_mode; /* to be removed by full off-mode patches */
158
159 static void omap_uart_save_context(struct omap_uart_state *uart)
160 {
161 u16 lcr = 0;
162 struct plat_serial8250_port *p = uart->p;
163
164 if (!enable_off_mode)
165 return;
166
167 lcr = serial_read_reg(p, UART_LCR);
168 serial_write_reg(p, UART_LCR, 0xBF);
169 uart->dll = serial_read_reg(p, UART_DLL);
170 uart->dlh = serial_read_reg(p, UART_DLM);
171 serial_write_reg(p, UART_LCR, lcr);
172 uart->ier = serial_read_reg(p, UART_IER);
173 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
174 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
175 uart->wer = serial_read_reg(p, UART_OMAP_WER);
176
177 uart->context_valid = 1;
178 }
179
180 static void omap_uart_restore_context(struct omap_uart_state *uart)
181 {
182 u16 efr = 0;
183 struct plat_serial8250_port *p = uart->p;
184
185 if (!enable_off_mode)
186 return;
187
188 if (!uart->context_valid)
189 return;
190
191 uart->context_valid = 0;
192
193 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
194 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
195 efr = serial_read_reg(p, UART_EFR);
196 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
197 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
198 serial_write_reg(p, UART_IER, 0x0);
199 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
200 serial_write_reg(p, UART_DLL, uart->dll);
201 serial_write_reg(p, UART_DLM, uart->dlh);
202 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
203 serial_write_reg(p, UART_IER, uart->ier);
204 serial_write_reg(p, UART_FCR, 0xA1);
205 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
206 serial_write_reg(p, UART_EFR, efr);
207 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
208 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
209 serial_write_reg(p, UART_OMAP_WER, uart->wer);
210 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
211 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
212 }
213 #else
214 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
215 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
216 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
217
218 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
219 {
220 if (uart->clocked)
221 return;
222
223 clk_enable(uart->ick);
224 clk_enable(uart->fck);
225 uart->clocked = 1;
226 omap_uart_restore_context(uart);
227 }
228
229 #ifdef CONFIG_PM
230
231 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
232 {
233 if (!uart->clocked)
234 return;
235
236 omap_uart_save_context(uart);
237 uart->clocked = 0;
238 clk_disable(uart->ick);
239 clk_disable(uart->fck);
240 }
241
242 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
243 {
244 /* Set wake-enable bit */
245 if (uart->wk_en && uart->wk_mask) {
246 u32 v = __raw_readl(uart->wk_en);
247 v |= uart->wk_mask;
248 __raw_writel(v, uart->wk_en);
249 }
250
251 /* Ensure IOPAD wake-enables are set */
252 if (cpu_is_omap34xx() && uart->padconf) {
253 u16 v = omap_ctrl_readw(uart->padconf);
254 v |= OMAP3_PADCONF_WAKEUPENABLE0;
255 omap_ctrl_writew(v, uart->padconf);
256 }
257 }
258
259 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
260 {
261 /* Clear wake-enable bit */
262 if (uart->wk_en && uart->wk_mask) {
263 u32 v = __raw_readl(uart->wk_en);
264 v &= ~uart->wk_mask;
265 __raw_writel(v, uart->wk_en);
266 }
267
268 /* Ensure IOPAD wake-enables are cleared */
269 if (cpu_is_omap34xx() && uart->padconf) {
270 u16 v = omap_ctrl_readw(uart->padconf);
271 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
272 omap_ctrl_writew(v, uart->padconf);
273 }
274 }
275
276 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
277 int enable)
278 {
279 struct plat_serial8250_port *p = uart->p;
280 u16 sysc;
281
282 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
283 if (enable)
284 sysc |= 0x2 << 3;
285 else
286 sysc |= 0x1 << 3;
287
288 serial_write_reg(p, UART_OMAP_SYSC, sysc);
289 }
290
291 static void omap_uart_block_sleep(struct omap_uart_state *uart)
292 {
293 omap_uart_enable_clocks(uart);
294
295 omap_uart_smart_idle_enable(uart, 0);
296 uart->can_sleep = 0;
297 if (uart->timeout)
298 mod_timer(&uart->timer, jiffies + uart->timeout);
299 else
300 del_timer(&uart->timer);
301 }
302
303 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
304 {
305 if (device_may_wakeup(&uart->pdev.dev))
306 omap_uart_enable_wakeup(uart);
307 else
308 omap_uart_disable_wakeup(uart);
309
310 if (!uart->clocked)
311 return;
312
313 omap_uart_smart_idle_enable(uart, 1);
314 uart->can_sleep = 1;
315 del_timer(&uart->timer);
316 }
317
318 static void omap_uart_idle_timer(unsigned long data)
319 {
320 struct omap_uart_state *uart = (struct omap_uart_state *)data;
321
322 omap_uart_allow_sleep(uart);
323 }
324
325 void omap_uart_prepare_idle(int num)
326 {
327 struct omap_uart_state *uart;
328
329 list_for_each_entry(uart, &uart_list, node) {
330 if (num == uart->num && uart->can_sleep) {
331 omap_uart_disable_clocks(uart);
332 return;
333 }
334 }
335 }
336
337 void omap_uart_resume_idle(int num)
338 {
339 struct omap_uart_state *uart;
340
341 list_for_each_entry(uart, &uart_list, node) {
342 if (num == uart->num) {
343 omap_uart_enable_clocks(uart);
344
345 /* Check for IO pad wakeup */
346 if (cpu_is_omap34xx() && uart->padconf) {
347 u16 p = omap_ctrl_readw(uart->padconf);
348
349 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
350 omap_uart_block_sleep(uart);
351 }
352
353 /* Check for normal UART wakeup */
354 if (__raw_readl(uart->wk_st) & uart->wk_mask)
355 omap_uart_block_sleep(uart);
356 return;
357 }
358 }
359 }
360
361 void omap_uart_prepare_suspend(void)
362 {
363 struct omap_uart_state *uart;
364
365 list_for_each_entry(uart, &uart_list, node) {
366 omap_uart_allow_sleep(uart);
367 }
368 }
369
370 int omap_uart_can_sleep(void)
371 {
372 struct omap_uart_state *uart;
373 int can_sleep = 1;
374
375 list_for_each_entry(uart, &uart_list, node) {
376 if (!uart->clocked)
377 continue;
378
379 if (!uart->can_sleep) {
380 can_sleep = 0;
381 continue;
382 }
383
384 /* This UART can now safely sleep. */
385 omap_uart_allow_sleep(uart);
386 }
387
388 return can_sleep;
389 }
390
391 /**
392 * omap_uart_interrupt()
393 *
394 * This handler is used only to detect that *any* UART interrupt has
395 * occurred. It does _nothing_ to handle the interrupt. Rather,
396 * any UART interrupt will trigger the inactivity timer so the
397 * UART will not idle or sleep for its timeout period.
398 *
399 **/
400 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
401 {
402 struct omap_uart_state *uart = dev_id;
403
404 omap_uart_block_sleep(uart);
405
406 return IRQ_NONE;
407 }
408
409 static void omap_uart_idle_init(struct omap_uart_state *uart)
410 {
411 struct plat_serial8250_port *p = uart->p;
412 int ret;
413
414 uart->can_sleep = 0;
415 uart->timeout = DEFAULT_TIMEOUT;
416 setup_timer(&uart->timer, omap_uart_idle_timer,
417 (unsigned long) uart);
418 mod_timer(&uart->timer, jiffies + uart->timeout);
419 omap_uart_smart_idle_enable(uart, 0);
420
421 if (cpu_is_omap34xx()) {
422 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
423 u32 wk_mask = 0;
424 u32 padconf = 0;
425
426 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
427 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
428 switch (uart->num) {
429 case 0:
430 wk_mask = OMAP3430_ST_UART1_MASK;
431 padconf = 0x182;
432 break;
433 case 1:
434 wk_mask = OMAP3430_ST_UART2_MASK;
435 padconf = 0x17a;
436 break;
437 case 2:
438 wk_mask = OMAP3430_ST_UART3_MASK;
439 padconf = 0x19e;
440 break;
441 }
442 uart->wk_mask = wk_mask;
443 uart->padconf = padconf;
444 } else if (cpu_is_omap24xx()) {
445 u32 wk_mask = 0;
446
447 if (cpu_is_omap2430()) {
448 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
449 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
450 } else if (cpu_is_omap2420()) {
451 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
452 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
453 }
454 switch (uart->num) {
455 case 0:
456 wk_mask = OMAP24XX_ST_UART1_MASK;
457 break;
458 case 1:
459 wk_mask = OMAP24XX_ST_UART2_MASK;
460 break;
461 case 2:
462 wk_mask = OMAP24XX_ST_UART3_MASK;
463 break;
464 }
465 uart->wk_mask = wk_mask;
466 } else {
467 uart->wk_en = 0;
468 uart->wk_st = 0;
469 uart->wk_mask = 0;
470 uart->padconf = 0;
471 }
472
473 p->flags |= UPF_SHARE_IRQ;
474 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
475 "serial idle", (void *)uart);
476 WARN_ON(ret);
477 }
478
479 void omap_uart_enable_irqs(int enable)
480 {
481 int ret;
482 struct omap_uart_state *uart;
483
484 list_for_each_entry(uart, &uart_list, node) {
485 if (enable)
486 ret = request_irq(uart->p->irq, omap_uart_interrupt,
487 IRQF_SHARED, "serial idle", (void *)uart);
488 else
489 free_irq(uart->p->irq, (void *)uart);
490 }
491 }
492
493 static ssize_t sleep_timeout_show(struct device *dev,
494 struct device_attribute *attr,
495 char *buf)
496 {
497 struct platform_device *pdev = container_of(dev,
498 struct platform_device, dev);
499 struct omap_uart_state *uart = container_of(pdev,
500 struct omap_uart_state, pdev);
501
502 return sprintf(buf, "%u\n", uart->timeout / HZ);
503 }
504
505 static ssize_t sleep_timeout_store(struct device *dev,
506 struct device_attribute *attr,
507 const char *buf, size_t n)
508 {
509 struct platform_device *pdev = container_of(dev,
510 struct platform_device, dev);
511 struct omap_uart_state *uart = container_of(pdev,
512 struct omap_uart_state, pdev);
513 unsigned int value;
514
515 if (sscanf(buf, "%u", &value) != 1) {
516 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
517 return -EINVAL;
518 }
519
520 uart->timeout = value * HZ;
521 if (uart->timeout)
522 mod_timer(&uart->timer, jiffies + uart->timeout);
523 else
524 /* A zero value means disable timeout feature */
525 omap_uart_block_sleep(uart);
526
527 return n;
528 }
529
530 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
531 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
532 #else
533 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
534 #define DEV_CREATE_FILE(dev, attr)
535 #endif /* CONFIG_PM */
536
537 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
538 {
539 .pdev = {
540 .name = "serial8250",
541 .id = PLAT8250_DEV_PLATFORM,
542 .dev = {
543 .platform_data = serial_platform_data0,
544 },
545 },
546 }, {
547 .pdev = {
548 .name = "serial8250",
549 .id = PLAT8250_DEV_PLATFORM1,
550 .dev = {
551 .platform_data = serial_platform_data1,
552 },
553 },
554 }, {
555 .pdev = {
556 .name = "serial8250",
557 .id = PLAT8250_DEV_PLATFORM2,
558 .dev = {
559 .platform_data = serial_platform_data2,
560 },
561 },
562 },
563 };
564
565 void __init omap_serial_init(void)
566 {
567 int i;
568 const struct omap_uart_config *info;
569 char name[16];
570
571 /*
572 * Make sure the serial ports are muxed on at this point.
573 * You have to mux them off in device drivers later on
574 * if not needed.
575 */
576
577 info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
578
579 if (info == NULL)
580 return;
581
582 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
583 struct omap_uart_state *uart = &omap_uart[i];
584 struct platform_device *pdev = &uart->pdev;
585 struct device *dev = &pdev->dev;
586 struct plat_serial8250_port *p = dev->platform_data;
587
588 if (!(info->enabled_uarts & (1 << i))) {
589 p->membase = NULL;
590 p->mapbase = 0;
591 continue;
592 }
593
594 sprintf(name, "uart%d_ick", i+1);
595 uart->ick = clk_get(NULL, name);
596 if (IS_ERR(uart->ick)) {
597 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
598 uart->ick = NULL;
599 }
600
601 sprintf(name, "uart%d_fck", i+1);
602 uart->fck = clk_get(NULL, name);
603 if (IS_ERR(uart->fck)) {
604 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
605 uart->fck = NULL;
606 }
607
608 if (!uart->ick || !uart->fck)
609 continue;
610
611 uart->num = i;
612 p->private_data = uart;
613 uart->p = p;
614 list_add_tail(&uart->node, &uart_list);
615
616 if (cpu_is_omap44xx())
617 p->irq += 32;
618
619 omap_uart_enable_clocks(uart);
620 omap_uart_reset(uart);
621 omap_uart_idle_init(uart);
622
623 if (WARN_ON(platform_device_register(pdev)))
624 continue;
625 if ((cpu_is_omap34xx() && uart->padconf) ||
626 (uart->wk_en && uart->wk_mask)) {
627 device_init_wakeup(dev, true);
628 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
629 }
630 }
631 }
Linux with added FPC-III support