arch/sh/include/asm/pci.h

   1 #ifndef __ASM_SH_PCI_H
   2 #define __ASM_SH_PCI_H
   3
   4 #ifdef __KERNEL__
   5
   6 #include <linux/dma-mapping.h>
   7
   8 /* Can be used to override the logic in pci_scan_bus for skipping
   9    already-configured bus numbers - to be used for buggy BIOSes
  10    or architectures with incomplete PCI setup by the loader */
  11
  12 #define pcibios_assign_all_busses()     1
  13 #define pcibios_scan_all_fns(a, b)      0
  14
  15 /*
  16  * A board can define one or more PCI channels that represent built-in (or
  17  * external) PCI controllers.
  18  */
  19 struct pci_channel {
  20         struct pci_channel      *next;
  21
  22         struct pci_ops          *pci_ops;
  23         struct resource         *io_resource;
  24         struct resource         *mem_resource;
  25
  26         unsigned long           io_offset;
  27         unsigned long           mem_offset;
  28
  29         unsigned long           reg_base;
  30
  31         unsigned long           io_map_base;
  32 };
  33
  34 extern void register_pci_controller(struct pci_channel *hose);
  35
  36 extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
  37
  38 struct pci_dev;
  39
  40 #define HAVE_PCI_MMAP
  41 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  42         enum pci_mmap_state mmap_state, int write_combine);
  43 extern void pcibios_set_master(struct pci_dev *dev);
  44
  45 static inline void pcibios_penalize_isa_irq(int irq, int active)
  46 {
  47         /* We don't do dynamic PCI IRQ allocation */
  48 }
  49
  50 /* Dynamic DMA mapping stuff.
  51  * SuperH has everything mapped statically like x86.
  52  */
  53
  54 /* The PCI address space does equal the physical memory
  55  * address space.  The networking and block device layers use
  56  * this boolean for bounce buffer decisions.
  57  */
  58 #define PCI_DMA_BUS_IS_PHYS     (1)
  59
  60 #include <linux/types.h>
  61 #include <linux/slab.h>
  62 #include <asm/scatterlist.h>
  63 #include <linux/string.h>
  64 #include <asm/io.h>
  65
  66 /* pci_unmap_{single,page} being a nop depends upon the
  67  * configuration.
  68  */
  69 #ifdef CONFIG_SH_PCIDMA_NONCOHERENT
  70 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
  71         dma_addr_t ADDR_NAME;
  72 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
  73         __u32 LEN_NAME;
  74 #define pci_unmap_addr(PTR, ADDR_NAME)                  \
  75         ((PTR)->ADDR_NAME)
  76 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
  77         (((PTR)->ADDR_NAME) = (VAL))
  78 #define pci_unmap_len(PTR, LEN_NAME)                    \
  79         ((PTR)->LEN_NAME)
  80 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
  81         (((PTR)->LEN_NAME) = (VAL))
  82 #else
  83 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
  84 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
  85 #define pci_unmap_addr(PTR, ADDR_NAME)          (0)
  86 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
  87 #define pci_unmap_len(PTR, LEN_NAME)            (0)
  88 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
  89 #endif
  90
  91 #ifdef CONFIG_PCI
  92 /*
  93  * None of the SH PCI controllers support MWI, it is always treated as a
  94  * direct memory write.
  95  */
  96 #define PCI_DISABLE_MWI
  97
  98 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  99                                         enum pci_dma_burst_strategy *strat,
 100                                         unsigned long *strategy_parameter)
 101 {
 102         unsigned long cacheline_size;
 103         u8 byte;
 104
 105         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
 106
 107         if (byte == 0)
 108                 cacheline_size = L1_CACHE_BYTES;
 109         else
 110                 cacheline_size = byte << 2;
 111
 112         *strat = PCI_DMA_BURST_MULTIPLE;
 113         *strategy_parameter = cacheline_size;
 114 }
 115 #endif
 116
 117 #ifdef CONFIG_SUPERH32
 118 /*
 119  * If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
 120  * at the end of the address space in a special non-translatable area.
 121  */
 122 #define PCI_MEM_FIXED_START     0xfd000000
 123 #define PCI_MEM_FIXED_END       (PCI_MEM_FIXED_START + 0x01000000)
 124
 125 #define is_pci_memory_fixed_range(s, e) \
 126         ((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
 127 #else
 128 #define is_pci_memory_fixed_range(s, e) (0)
 129 #endif
 130
 131 /* Board-specific fixup routines. */
 132 int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
 133
 134 extern void pcibios_resource_to_bus(struct pci_dev *dev,
 135         struct pci_bus_region *region, struct resource *res);
 136
 137 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 138                                     struct pci_bus_region *region);
 139
 140 /* Chances are this interrupt is wired PC-style ...  */
 141 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 142 {
 143         return channel ? 15 : 14;
 144 }
 145
 146 /* generic DMA-mapping stuff */
 147 #include <asm-generic/pci-dma-compat.h>
 148
 149 #endif /* __KERNEL__ */
 150 #endif /* __ASM_SH_PCI_H */
 151