arch/sh/include/asm/processor.h

   1 #ifndef __ASM_SH_PROCESSOR_H
   2 #define __ASM_SH_PROCESSOR_H
   3
   4 #include <asm/cpu-features.h>
   5 #include <asm/segment.h>
   6 #include <asm/cache.h>
   7
   8 #ifndef __ASSEMBLY__
   9 /*
  10  *  CPU type and hardware bug flags. Kept separately for each CPU.
  11  *
  12  *  Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
  13  *  in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
  14  *  for parsing the subtype in get_cpu_subtype().
  15  */
  16 enum cpu_type {
  17         /* SH-2 types */
  18         CPU_SH7619,
  19
  20         /* SH-2A types */
  21         CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
  22
  23         /* SH-3 types */
  24         CPU_SH7705, CPU_SH7706, CPU_SH7707,
  25         CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
  26         CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
  27         CPU_SH7720, CPU_SH7721, CPU_SH7729,
  28
  29         /* SH-4 types */
  30         CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
  31         CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
  32
  33         /* SH-4A types */
  34         CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
  35         CPU_SH7723, CPU_SH7724, CPU_SHX3,
  36
  37         /* SH4AL-DSP types */
  38         CPU_SH7343, CPU_SH7722, CPU_SH7366,
  39
  40         /* SH-5 types */
  41         CPU_SH5_101, CPU_SH5_103,
  42
  43         /* Unknown subtype */
  44         CPU_SH_NONE
  45 };
  46
  47 /*
  48  * TLB information structure
  49  *
  50  * Defined for both I and D tlb, per-processor.
  51  */
  52 struct tlb_info {
  53         unsigned long long next;
  54         unsigned long long first;
  55         unsigned long long last;
  56
  57         unsigned int entries;
  58         unsigned int step;
  59
  60         unsigned long flags;
  61 };
  62
  63 struct sh_cpuinfo {
  64         unsigned int type;
  65         int cut_major, cut_minor;
  66         unsigned long loops_per_jiffy;
  67         unsigned long asid_cache;
  68
  69         struct cache_info icache;       /* Primary I-cache */
  70         struct cache_info dcache;       /* Primary D-cache */
  71         struct cache_info scache;       /* Secondary cache */
  72
  73         /* TLB info */
  74         struct tlb_info itlb;
  75         struct tlb_info dtlb;
  76
  77         unsigned long flags;
  78 } __attribute__ ((aligned(L1_CACHE_BYTES)));
  79
  80 extern struct sh_cpuinfo cpu_data[];
  81 #define boot_cpu_data cpu_data[0]
  82 #define current_cpu_data cpu_data[smp_processor_id()]
  83 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
  84
  85 #define cpu_sleep()     __asm__ __volatile__ ("sleep" : : : "memory")
  86 #define cpu_relax()     barrier()
  87
  88 /* Forward decl */
  89 struct seq_operations;
  90
  91 extern struct pt_regs fake_swapper_regs;
  92
  93 /* arch/sh/kernel/setup.c */
  94 const char *get_cpu_subtype(struct sh_cpuinfo *c);
  95 extern const struct seq_operations cpuinfo_op;
  96
  97 /* processor boot mode configuration */
  98 #define MODE_PIN0 (1 << 0)
  99 #define MODE_PIN1 (1 << 1)
 100 #define MODE_PIN2 (1 << 2)
 101 #define MODE_PIN3 (1 << 3)
 102 #define MODE_PIN4 (1 << 4)
 103 #define MODE_PIN5 (1 << 5)
 104 #define MODE_PIN6 (1 << 6)
 105 #define MODE_PIN7 (1 << 7)
 106 #define MODE_PIN8 (1 << 8)
 107 #define MODE_PIN9 (1 << 9)
 108 #define MODE_PIN10 (1 << 10)
 109 #define MODE_PIN11 (1 << 11)
 110 #define MODE_PIN12 (1 << 12)
 111 #define MODE_PIN13 (1 << 13)
 112 #define MODE_PIN14 (1 << 14)
 113 #define MODE_PIN15 (1 << 15)
 114
 115 int generic_mode_pins(void);
 116 int test_mode_pin(int pin);
 117
 118 #ifdef CONFIG_VSYSCALL
 119 int vsyscall_init(void);
 120 #else
 121 #define vsyscall_init() do { } while (0)
 122 #endif
 123
 124 #endif /* __ASSEMBLY__ */
 125
 126 #ifdef CONFIG_SUPERH32
 127 # include "processor_32.h"
 128 #else
 129 # include "processor_64.h"
 130 #endif
 131
 132 #endif /* __ASM_SH_PROCESSOR_H */