arch/sh/kernel/cpu/sh4a/clock-sh7722.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
   3  *
   4  * SH7722 clock framework support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <asm/clock.h>
  25
  26 /* SH7722 registers */
  27 #define FRQCR           0xa4150000
  28 #define VCLKCR          0xa4150004
  29 #define SCLKACR         0xa4150008
  30 #define SCLKBCR         0xa415000c
  31 #define IRDACLKCR       0xa4150018
  32 #define PLLCR           0xa4150024
  33 #define MSTPCR0         0xa4150030
  34 #define MSTPCR1         0xa4150034
  35 #define MSTPCR2         0xa4150038
  36 #define DLLFRQ          0xa4150050
  37
  38 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
  39 static struct clk r_clk = {
  40         .name           = "rclk",
  41         .id             = -1,
  42         .rate           = 32768,
  43 };
  44
  45 /*
  46  * Default rate for the root input clock, reset this with clk_set_rate()
  47  * from the platform code.
  48  */
  49 struct clk extal_clk = {
  50         .name           = "extal",
  51         .id             = -1,
  52         .rate           = 33333333,
  53 };
  54
  55 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
  56 static unsigned long dll_recalc(struct clk *clk)
  57 {
  58         unsigned long mult;
  59
  60         if (__raw_readl(PLLCR) & 0x1000)
  61                 mult = __raw_readl(DLLFRQ);
  62         else
  63                 mult = 0;
  64
  65         return clk->parent->rate * mult;
  66 }
  67
  68 static struct clk_ops dll_clk_ops = {
  69         .recalc         = dll_recalc,
  70 };
  71
  72 static struct clk dll_clk = {
  73         .name           = "dll_clk",
  74         .id             = -1,
  75         .ops            = &dll_clk_ops,
  76         .parent         = &r_clk,
  77         .flags          = CLK_ENABLE_ON_INIT,
  78 };
  79
  80 static unsigned long pll_recalc(struct clk *clk)
  81 {
  82         unsigned long mult = 1;
  83         unsigned long div = 1;
  84
  85         if (__raw_readl(PLLCR) & 0x4000)
  86                 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
  87         else
  88                 div = 2;
  89
  90         return (clk->parent->rate * mult) / div;
  91 }
  92
  93 static struct clk_ops pll_clk_ops = {
  94         .recalc         = pll_recalc,
  95 };
  96
  97 static struct clk pll_clk = {
  98         .name           = "pll_clk",
  99         .id             = -1,
 100         .ops            = &pll_clk_ops,
 101         .flags          = CLK_ENABLE_ON_INIT,
 102 };
 103
 104 struct clk *main_clks[] = {
 105         &r_clk,
 106         &extal_clk,
 107         &dll_clk,
 108         &pll_clk,
 109 };
 110
 111 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 112 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 113
 114 static struct clk_div_mult_table div4_table = {
 115         .divisors = divisors,
 116         .nr_divisors = ARRAY_SIZE(divisors),
 117         .multipliers = multipliers,
 118         .nr_multipliers = ARRAY_SIZE(multipliers),
 119 };
 120
 121 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
 122        DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
 123
 124 #define DIV4(_str, _reg, _bit, _mask, _flags) \
 125   SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
 126
 127 struct clk div4_clks[DIV4_NR] = {
 128         [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
 129         [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
 130         [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
 131         [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
 132         [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
 133         [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
 134         [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
 135         [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
 136         [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
 137 };
 138
 139 struct clk div6_clks[] = {
 140         SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
 141 };
 142
 143 #define MSTP(_str, _parent, _reg, _bit, _flags) \
 144   SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
 145
 146 static struct clk mstp_clks[] = {
 147         MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
 148         MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
 149         MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
 150         MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
 151         MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
 152         MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
 153         MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
 154         MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
 155         MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
 156
 157         MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
 158         MSTP("rtc0", &r_clk, MSTPCR1, 8, 0),
 159
 160         MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
 161         MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
 162         MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
 163         MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
 164         MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
 165         MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
 166         MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
 167         MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
 168         MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
 169         MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
 170         MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
 171         MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
 172 };
 173
 174 int __init arch_clk_init(void)
 175 {
 176         int k, ret = 0;
 177
 178         /* autodetect extal or dll configuration */
 179         if (__raw_readl(PLLCR) & 0x1000)
 180                 pll_clk.parent = &dll_clk;
 181         else
 182                 pll_clk.parent = &extal_clk;
 183
 184         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 185                 ret = clk_register(main_clks[k]);
 186
 187         if (!ret)
 188                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 189
 190         if (!ret)
 191                 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
 192
 193         if (!ret)
 194                 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
 195
 196         return ret;
 197 }