arch/sh/kernel/cpu/sh4a/clock-sh7724.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
   3  *
   4  * SH7724 clock framework support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <asm/clock.h>
  25
  26 /* SH7724 registers */
  27 #define FRQCRA          0xa4150000
  28 #define FRQCRB          0xa4150004
  29 #define VCLKCR          0xa4150048
  30 #define FCLKACR         0xa4150008
  31 #define FCLKBCR         0xa415000c
  32 #define IRDACLKCR       0xa4150018
  33 #define PLLCR           0xa4150024
  34 #define MSTPCR0         0xa4150030
  35 #define MSTPCR1         0xa4150034
  36 #define MSTPCR2         0xa4150038
  37 #define SPUCLKCR        0xa415003c
  38 #define FLLFRQ          0xa4150050
  39 #define LSTATS          0xa4150060
  40
  41 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
  42 static struct clk r_clk = {
  43         .name           = "rclk",
  44         .id             = -1,
  45         .rate           = 32768,
  46 };
  47
  48 /*
  49  * Default rate for the root input clock, reset this with clk_set_rate()
  50  * from the platform code.
  51  */
  52 struct clk extal_clk = {
  53         .name           = "extal",
  54         .id             = -1,
  55         .rate           = 33333333,
  56 };
  57
  58 /* The fll multiplies the 32khz r_clk, may be used instead of extal */
  59 static unsigned long fll_recalc(struct clk *clk)
  60 {
  61         unsigned long mult = 0;
  62         unsigned long div = 1;
  63
  64         if (__raw_readl(PLLCR) & 0x1000)
  65                 mult = __raw_readl(FLLFRQ) & 0x3ff;
  66
  67         if (__raw_readl(FLLFRQ) & 0x4000)
  68                 div = 2;
  69
  70         return (clk->parent->rate * mult) / div;
  71 }
  72
  73 static struct clk_ops fll_clk_ops = {
  74         .recalc         = fll_recalc,
  75 };
  76
  77 static struct clk fll_clk = {
  78         .name           = "fll_clk",
  79         .id             = -1,
  80         .ops            = &fll_clk_ops,
  81         .parent         = &r_clk,
  82         .flags          = CLK_ENABLE_ON_INIT,
  83 };
  84
  85 static unsigned long pll_recalc(struct clk *clk)
  86 {
  87         unsigned long mult = 1;
  88
  89         if (__raw_readl(PLLCR) & 0x4000)
  90                 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
  91
  92         return clk->parent->rate * mult;
  93 }
  94
  95 static struct clk_ops pll_clk_ops = {
  96         .recalc         = pll_recalc,
  97 };
  98
  99 static struct clk pll_clk = {
 100         .name           = "pll_clk",
 101         .id             = -1,
 102         .ops            = &pll_clk_ops,
 103         .flags          = CLK_ENABLE_ON_INIT,
 104 };
 105
 106 /* A fixed divide-by-3 block use by the div6 clocks */
 107 static unsigned long div3_recalc(struct clk *clk)
 108 {
 109         return clk->parent->rate / 3;
 110 }
 111
 112 static struct clk_ops div3_clk_ops = {
 113         .recalc         = div3_recalc,
 114 };
 115
 116 static struct clk div3_clk = {
 117         .name           = "div3_clk",
 118         .id             = -1,
 119         .ops            = &div3_clk_ops,
 120         .parent         = &pll_clk,
 121 };
 122
 123 struct clk *main_clks[] = {
 124         &r_clk,
 125         &extal_clk,
 126         &fll_clk,
 127         &pll_clk,
 128         &div3_clk,
 129 };
 130
 131 static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
 132
 133 static struct clk_div_mult_table div4_table = {
 134         .divisors = divisors,
 135         .nr_divisors = ARRAY_SIZE(divisors),
 136 };
 137
 138 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
 139
 140 #define DIV4(_str, _reg, _bit, _mask, _flags) \
 141   SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
 142
 143 struct clk div4_clks[DIV4_NR] = {
 144         [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
 145         [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
 146         [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
 147         [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
 148         [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
 149 };
 150
 151 struct clk div6_clks[] = {
 152         SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
 153         SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
 154         SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
 155         SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
 156         SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0),
 157 };
 158
 159 #define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
 160   SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
 161
 162 static struct clk mstp_clks[] = {
 163         MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
 164         MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
 165         MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
 166         MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0),
 167         MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
 168         MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0),
 169         MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
 170         MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0),
 171         MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
 172         MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
 173         MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
 174         MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
 175         MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
 176         MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
 177         MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
 178         MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
 179         MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
 180         MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
 181         MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
 182         MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
 183         MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
 184         MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
 185         MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
 186         MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
 187         MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
 188
 189         MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0),
 190         MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0),
 191         MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
 192         MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0),
 193
 194         MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0),
 195         MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0),
 196         MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0),
 197         MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
 198         MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
 199         MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
 200         MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
 201         MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1),
 202         MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1),
 203         MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
 204         MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
 205         MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1),
 206         MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1),
 207         MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1),
 208         MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1),
 209         MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0),
 210         MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
 211         MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
 212         MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
 213         MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
 214         MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
 215         MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
 216         MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
 217 };
 218
 219 int __init arch_clk_init(void)
 220 {
 221         int k, ret = 0;
 222
 223         /* autodetect extal or fll configuration */
 224         if (__raw_readl(PLLCR) & 0x1000)
 225                 pll_clk.parent = &fll_clk;
 226         else
 227                 pll_clk.parent = &extal_clk;
 228
 229         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 230                 ret = clk_register(main_clks[k]);
 231
 232         if (!ret)
 233                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 234
 235         if (!ret)
 236                 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
 237
 238         if (!ret)
 239                 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
 240
 241         return ret;
 242 }