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debugfs: Modified default dir of debugfs for debugging UHCI.
[linux/fpc-iii.git] / drivers / net / e1000e / phy.c
blob994401fd0664fbc188980ea188e33bdf95fdb0ec
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/delay.h>
30
31 #include "e1000.h"
32
33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
43
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] =
46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47
48 static const u16 e1000_igp_2_cable_length_table[] =
49 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
50 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
51 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
52 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
53 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
54 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
55 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
56 124};
57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
58 ARRAY_SIZE(e1000_igp_2_cable_length_table)
59
60 #define BM_PHY_REG_PAGE(offset) \
61 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
62 #define BM_PHY_REG_NUM(offset) \
63 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
64 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
65 ~MAX_PHY_REG_ADDRESS)))
66
67 #define HV_INTC_FC_PAGE_START 768
68 #define I82578_ADDR_REG 29
69 #define I82577_ADDR_REG 16
70 #define I82577_CFG_REG 22
71 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73 #define I82577_CTRL_REG 23
74 #define I82577_CTRL_DOWNSHIFT_MASK (7 << 10)
75
76 /* 82577 specific PHY registers */
77 #define I82577_PHY_CTRL_2 18
78 #define I82577_PHY_STATUS_2 26
79 #define I82577_PHY_DIAG_STATUS 31
80
81 /* I82577 PHY Status 2 */
82 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
83 #define I82577_PHY_STATUS2_MDIX 0x0800
84 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
85 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
86
87 /* I82577 PHY Control 2 */
88 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
89 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
90
91 /* I82577 PHY Diagnostics Status */
92 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
93 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
94
95 /* BM PHY Copper Specific Control 1 */
96 #define BM_CS_CTRL1 16
97
98 /* BM PHY Copper Specific Status */
99 #define BM_CS_STATUS 17
100 #define BM_CS_STATUS_LINK_UP 0x0400
101 #define BM_CS_STATUS_RESOLVED 0x0800
102 #define BM_CS_STATUS_SPEED_MASK 0xC000
103 #define BM_CS_STATUS_SPEED_1000 0x8000
104
105 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
106 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
107 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
108
109 /**
110 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
111 * @hw: pointer to the HW structure
112 *
113 * Read the PHY management control register and check whether a PHY reset
114 * is blocked. If a reset is not blocked return 0, otherwise
115 * return E1000_BLK_PHY_RESET (12).
116 **/
117 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
118 {
119 u32 manc;
120
121 manc = er32(MANC);
122
123 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
124 E1000_BLK_PHY_RESET : 0;
125 }
126
127 /**
128 * e1000e_get_phy_id - Retrieve the PHY ID and revision
129 * @hw: pointer to the HW structure
130 *
131 * Reads the PHY registers and stores the PHY ID and possibly the PHY
132 * revision in the hardware structure.
133 **/
134 s32 e1000e_get_phy_id(struct e1000_hw *hw)
135 {
136 struct e1000_phy_info *phy = &hw->phy;
137 s32 ret_val = 0;
138 u16 phy_id;
139 u16 retry_count = 0;
140
141 if (!(phy->ops.read_phy_reg))
142 goto out;
143
144 while (retry_count < 2) {
145 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
146 if (ret_val)
147 goto out;
148
149 phy->id = (u32)(phy_id << 16);
150 udelay(20);
151 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
152 if (ret_val)
153 goto out;
154
155 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
156 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
157
158 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
159 goto out;
160
161 /*
162 * If the PHY ID is still unknown, we may have an 82577i
163 * without link. We will try again after setting Slow
164 * MDIC mode. No harm in trying again in this case since
165 * the PHY ID is unknown at this point anyway
166 */
167 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
168 if (ret_val)
169 goto out;
170
171 retry_count++;
172 }
173 out:
174 /* Revert to MDIO fast mode, if applicable */
175 if (retry_count)
176 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
177
178 return ret_val;
179 }
180
181 /**
182 * e1000e_phy_reset_dsp - Reset PHY DSP
183 * @hw: pointer to the HW structure
184 *
185 * Reset the digital signal processor.
186 **/
187 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
188 {
189 s32 ret_val;
190
191 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
192 if (ret_val)
193 return ret_val;
194
195 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
196 }
197
198 /**
199 * e1000e_read_phy_reg_mdic - Read MDI control register
200 * @hw: pointer to the HW structure
201 * @offset: register offset to be read
202 * @data: pointer to the read data
203 *
204 * Reads the MDI control register in the PHY at offset and stores the
205 * information read to data.
206 **/
207 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
208 {
209 struct e1000_phy_info *phy = &hw->phy;
210 u32 i, mdic = 0;
211
212 if (offset > MAX_PHY_REG_ADDRESS) {
213 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
214 return -E1000_ERR_PARAM;
215 }
216
217 /*
218 * Set up Op-code, Phy Address, and register offset in the MDI
219 * Control register. The MAC will take care of interfacing with the
220 * PHY to retrieve the desired data.
221 */
222 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
223 (phy->addr << E1000_MDIC_PHY_SHIFT) |
224 (E1000_MDIC_OP_READ));
225
226 ew32(MDIC, mdic);
227
228 /*
229 * Poll the ready bit to see if the MDI read completed
230 * Increasing the time out as testing showed failures with
231 * the lower time out
232 */
233 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
234 udelay(50);
235 mdic = er32(MDIC);
236 if (mdic & E1000_MDIC_READY)
237 break;
238 }
239 if (!(mdic & E1000_MDIC_READY)) {
240 hw_dbg(hw, "MDI Read did not complete\n");
241 return -E1000_ERR_PHY;
242 }
243 if (mdic & E1000_MDIC_ERROR) {
244 hw_dbg(hw, "MDI Error\n");
245 return -E1000_ERR_PHY;
246 }
247 *data = (u16) mdic;
248
249 return 0;
250 }
251
252 /**
253 * e1000e_write_phy_reg_mdic - Write MDI control register
254 * @hw: pointer to the HW structure
255 * @offset: register offset to write to
256 * @data: data to write to register at offset
257 *
258 * Writes data to MDI control register in the PHY at offset.
259 **/
260 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
261 {
262 struct e1000_phy_info *phy = &hw->phy;
263 u32 i, mdic = 0;
264
265 if (offset > MAX_PHY_REG_ADDRESS) {
266 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
267 return -E1000_ERR_PARAM;
268 }
269
270 /*
271 * Set up Op-code, Phy Address, and register offset in the MDI
272 * Control register. The MAC will take care of interfacing with the
273 * PHY to retrieve the desired data.
274 */
275 mdic = (((u32)data) |
276 (offset << E1000_MDIC_REG_SHIFT) |
277 (phy->addr << E1000_MDIC_PHY_SHIFT) |
278 (E1000_MDIC_OP_WRITE));
279
280 ew32(MDIC, mdic);
281
282 /*
283 * Poll the ready bit to see if the MDI read completed
284 * Increasing the time out as testing showed failures with
285 * the lower time out
286 */
287 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
288 udelay(50);
289 mdic = er32(MDIC);
290 if (mdic & E1000_MDIC_READY)
291 break;
292 }
293 if (!(mdic & E1000_MDIC_READY)) {
294 hw_dbg(hw, "MDI Write did not complete\n");
295 return -E1000_ERR_PHY;
296 }
297 if (mdic & E1000_MDIC_ERROR) {
298 hw_dbg(hw, "MDI Error\n");
299 return -E1000_ERR_PHY;
300 }
301
302 return 0;
303 }
304
305 /**
306 * e1000e_read_phy_reg_m88 - Read m88 PHY register
307 * @hw: pointer to the HW structure
308 * @offset: register offset to be read
309 * @data: pointer to the read data
310 *
311 * Acquires semaphore, if necessary, then reads the PHY register at offset
312 * and storing the retrieved information in data. Release any acquired
313 * semaphores before exiting.
314 **/
315 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
316 {
317 s32 ret_val;
318
319 ret_val = hw->phy.ops.acquire_phy(hw);
320 if (ret_val)
321 return ret_val;
322
323 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
324 data);
325
326 hw->phy.ops.release_phy(hw);
327
328 return ret_val;
329 }
330
331 /**
332 * e1000e_write_phy_reg_m88 - Write m88 PHY register
333 * @hw: pointer to the HW structure
334 * @offset: register offset to write to
335 * @data: data to write at register offset
336 *
337 * Acquires semaphore, if necessary, then writes the data to PHY register
338 * at the offset. Release any acquired semaphores before exiting.
339 **/
340 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
341 {
342 s32 ret_val;
343
344 ret_val = hw->phy.ops.acquire_phy(hw);
345 if (ret_val)
346 return ret_val;
347
348 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
349 data);
350
351 hw->phy.ops.release_phy(hw);
352
353 return ret_val;
354 }
355
356 /**
357 * e1000e_read_phy_reg_igp - Read igp PHY register
358 * @hw: pointer to the HW structure
359 * @offset: register offset to be read
360 * @data: pointer to the read data
361 *
362 * Acquires semaphore, if necessary, then reads the PHY register at offset
363 * and storing the retrieved information in data. Release any acquired
364 * semaphores before exiting.
365 **/
366 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
367 {
368 s32 ret_val;
369
370 ret_val = hw->phy.ops.acquire_phy(hw);
371 if (ret_val)
372 return ret_val;
373
374 if (offset > MAX_PHY_MULTI_PAGE_REG) {
375 ret_val = e1000e_write_phy_reg_mdic(hw,
376 IGP01E1000_PHY_PAGE_SELECT,
377 (u16)offset);
378 if (ret_val) {
379 hw->phy.ops.release_phy(hw);
380 return ret_val;
381 }
382 }
383
384 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
385 data);
386
387 hw->phy.ops.release_phy(hw);
388
389 return ret_val;
390 }
391
392 /**
393 * e1000e_write_phy_reg_igp - Write igp PHY register
394 * @hw: pointer to the HW structure
395 * @offset: register offset to write to
396 * @data: data to write at register offset
397 *
398 * Acquires semaphore, if necessary, then writes the data to PHY register
399 * at the offset. Release any acquired semaphores before exiting.
400 **/
401 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
402 {
403 s32 ret_val;
404
405 ret_val = hw->phy.ops.acquire_phy(hw);
406 if (ret_val)
407 return ret_val;
408
409 if (offset > MAX_PHY_MULTI_PAGE_REG) {
410 ret_val = e1000e_write_phy_reg_mdic(hw,
411 IGP01E1000_PHY_PAGE_SELECT,
412 (u16)offset);
413 if (ret_val) {
414 hw->phy.ops.release_phy(hw);
415 return ret_val;
416 }
417 }
418
419 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
420 data);
421
422 hw->phy.ops.release_phy(hw);
423
424 return ret_val;
425 }
426
427 /**
428 * e1000e_read_kmrn_reg - Read kumeran register
429 * @hw: pointer to the HW structure
430 * @offset: register offset to be read
431 * @data: pointer to the read data
432 *
433 * Acquires semaphore, if necessary. Then reads the PHY register at offset
434 * using the kumeran interface. The information retrieved is stored in data.
435 * Release any acquired semaphores before exiting.
436 **/
437 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
438 {
439 u32 kmrnctrlsta;
440 s32 ret_val;
441
442 ret_val = hw->phy.ops.acquire_phy(hw);
443 if (ret_val)
444 return ret_val;
445
446 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
447 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
448 ew32(KMRNCTRLSTA, kmrnctrlsta);
449
450 udelay(2);
451
452 kmrnctrlsta = er32(KMRNCTRLSTA);
453 *data = (u16)kmrnctrlsta;
454
455 hw->phy.ops.release_phy(hw);
456
457 return ret_val;
458 }
459
460 /**
461 * e1000e_write_kmrn_reg - Write kumeran register
462 * @hw: pointer to the HW structure
463 * @offset: register offset to write to
464 * @data: data to write at register offset
465 *
466 * Acquires semaphore, if necessary. Then write the data to PHY register
467 * at the offset using the kumeran interface. Release any acquired semaphores
468 * before exiting.
469 **/
470 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
471 {
472 u32 kmrnctrlsta;
473 s32 ret_val;
474
475 ret_val = hw->phy.ops.acquire_phy(hw);
476 if (ret_val)
477 return ret_val;
478
479 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
480 E1000_KMRNCTRLSTA_OFFSET) | data;
481 ew32(KMRNCTRLSTA, kmrnctrlsta);
482
483 udelay(2);
484 hw->phy.ops.release_phy(hw);
485
486 return ret_val;
487 }
488
489 /**
490 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
491 * @hw: pointer to the HW structure
492 *
493 * Sets up Carrier-sense on Transmit and downshift values.
494 **/
495 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
496 {
497 struct e1000_phy_info *phy = &hw->phy;
498 s32 ret_val;
499 u16 phy_data;
500
501 /* Enable CRS on TX. This must be set for half-duplex operation. */
502 ret_val = phy->ops.read_phy_reg(hw, I82577_CFG_REG, &phy_data);
503 if (ret_val)
504 goto out;
505
506 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
507
508 /* Enable downshift */
509 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
510
511 ret_val = phy->ops.write_phy_reg(hw, I82577_CFG_REG, phy_data);
512 if (ret_val)
513 goto out;
514
515 /* Set number of link attempts before downshift */
516 ret_val = phy->ops.read_phy_reg(hw, I82577_CTRL_REG, &phy_data);
517 if (ret_val)
518 goto out;
519 phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK;
520 ret_val = phy->ops.write_phy_reg(hw, I82577_CTRL_REG, phy_data);
521
522 out:
523 return ret_val;
524 }
525
526 /**
527 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
528 * @hw: pointer to the HW structure
529 *
530 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
531 * and downshift values are set also.
532 **/
533 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
534 {
535 struct e1000_phy_info *phy = &hw->phy;
536 s32 ret_val;
537 u16 phy_data;
538
539 /* Enable CRS on Tx. This must be set for half-duplex operation. */
540 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
541 if (ret_val)
542 return ret_val;
543
544 /* For BM PHY this bit is downshift enable */
545 if (phy->type != e1000_phy_bm)
546 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
547
548 /*
549 * Options:
550 * MDI/MDI-X = 0 (default)
551 * 0 - Auto for all speeds
552 * 1 - MDI mode
553 * 2 - MDI-X mode
554 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
555 */
556 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
557
558 switch (phy->mdix) {
559 case 1:
560 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
561 break;
562 case 2:
563 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
564 break;
565 case 3:
566 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
567 break;
568 case 0:
569 default:
570 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
571 break;
572 }
573
574 /*
575 * Options:
576 * disable_polarity_correction = 0 (default)
577 * Automatic Correction for Reversed Cable Polarity
578 * 0 - Disabled
579 * 1 - Enabled
580 */
581 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
582 if (phy->disable_polarity_correction == 1)
583 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
584
585 /* Enable downshift on BM (disabled by default) */
586 if (phy->type == e1000_phy_bm)
587 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
588
589 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
590 if (ret_val)
591 return ret_val;
592
593 if ((phy->type == e1000_phy_m88) &&
594 (phy->revision < E1000_REVISION_4) &&
595 (phy->id != BME1000_E_PHY_ID_R2)) {
596 /*
597 * Force TX_CLK in the Extended PHY Specific Control Register
598 * to 25MHz clock.
599 */
600 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
601 if (ret_val)
602 return ret_val;
603
604 phy_data |= M88E1000_EPSCR_TX_CLK_25;
605
606 if ((phy->revision == 2) &&
607 (phy->id == M88E1111_I_PHY_ID)) {
608 /* 82573L PHY - set the downshift counter to 5x. */
609 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
610 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
611 } else {
612 /* Configure Master and Slave downshift values */
613 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
614 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
615 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
616 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
617 }
618 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
619 if (ret_val)
620 return ret_val;
621 }
622
623 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
624 /* Set PHY page 0, register 29 to 0x0003 */
625 ret_val = e1e_wphy(hw, 29, 0x0003);
626 if (ret_val)
627 return ret_val;
628
629 /* Set PHY page 0, register 30 to 0x0000 */
630 ret_val = e1e_wphy(hw, 30, 0x0000);
631 if (ret_val)
632 return ret_val;
633 }
634
635 /* Commit the changes. */
636 ret_val = e1000e_commit_phy(hw);
637 if (ret_val) {
638 hw_dbg(hw, "Error committing the PHY changes\n");
639 return ret_val;
640 }
641
642 if (phy->type == e1000_phy_82578) {
643 ret_val = phy->ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
644 &phy_data);
645 if (ret_val)
646 return ret_val;
647
648 /* 82578 PHY - set the downshift count to 1x. */
649 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
650 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
651 ret_val = phy->ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
652 phy_data);
653 if (ret_val)
654 return ret_val;
655 }
656
657 return 0;
658 }
659
660 /**
661 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
662 * @hw: pointer to the HW structure
663 *
664 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
665 * igp PHY's.
666 **/
667 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
668 {
669 struct e1000_phy_info *phy = &hw->phy;
670 s32 ret_val;
671 u16 data;
672
673 ret_val = e1000_phy_hw_reset(hw);
674 if (ret_val) {
675 hw_dbg(hw, "Error resetting the PHY.\n");
676 return ret_val;
677 }
678
679 /*
680 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
681 * timeout issues when LFS is enabled.
682 */
683 msleep(100);
684
685 /* disable lplu d0 during driver init */
686 ret_val = e1000_set_d0_lplu_state(hw, 0);
687 if (ret_val) {
688 hw_dbg(hw, "Error Disabling LPLU D0\n");
689 return ret_val;
690 }
691 /* Configure mdi-mdix settings */
692 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
693 if (ret_val)
694 return ret_val;
695
696 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
697
698 switch (phy->mdix) {
699 case 1:
700 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
701 break;
702 case 2:
703 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
704 break;
705 case 0:
706 default:
707 data |= IGP01E1000_PSCR_AUTO_MDIX;
708 break;
709 }
710 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
711 if (ret_val)
712 return ret_val;
713
714 /* set auto-master slave resolution settings */
715 if (hw->mac.autoneg) {
716 /*
717 * when autonegotiation advertisement is only 1000Mbps then we
718 * should disable SmartSpeed and enable Auto MasterSlave
719 * resolution as hardware default.
720 */
721 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
722 /* Disable SmartSpeed */
723 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
724 &data);
725 if (ret_val)
726 return ret_val;
727
728 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
729 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
730 data);
731 if (ret_val)
732 return ret_val;
733
734 /* Set auto Master/Slave resolution process */
735 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
736 if (ret_val)
737 return ret_val;
738
739 data &= ~CR_1000T_MS_ENABLE;
740 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
741 if (ret_val)
742 return ret_val;
743 }
744
745 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
746 if (ret_val)
747 return ret_val;
748
749 /* load defaults for future use */
750 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
751 ((data & CR_1000T_MS_VALUE) ?
752 e1000_ms_force_master :
753 e1000_ms_force_slave) :
754 e1000_ms_auto;
755
756 switch (phy->ms_type) {
757 case e1000_ms_force_master:
758 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
759 break;
760 case e1000_ms_force_slave:
761 data |= CR_1000T_MS_ENABLE;
762 data &= ~(CR_1000T_MS_VALUE);
763 break;
764 case e1000_ms_auto:
765 data &= ~CR_1000T_MS_ENABLE;
766 default:
767 break;
768 }
769 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
770 }
771
772 return ret_val;
773 }
774
775 /**
776 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
777 * @hw: pointer to the HW structure
778 *
779 * Reads the MII auto-neg advertisement register and/or the 1000T control
780 * register and if the PHY is already setup for auto-negotiation, then
781 * return successful. Otherwise, setup advertisement and flow control to
782 * the appropriate values for the wanted auto-negotiation.
783 **/
784 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
785 {
786 struct e1000_phy_info *phy = &hw->phy;
787 s32 ret_val;
788 u16 mii_autoneg_adv_reg;
789 u16 mii_1000t_ctrl_reg = 0;
790
791 phy->autoneg_advertised &= phy->autoneg_mask;
792
793 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
794 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
795 if (ret_val)
796 return ret_val;
797
798 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
799 /* Read the MII 1000Base-T Control Register (Address 9). */
800 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
801 if (ret_val)
802 return ret_val;
803 }
804
805 /*
806 * Need to parse both autoneg_advertised and fc and set up
807 * the appropriate PHY registers. First we will parse for
808 * autoneg_advertised software override. Since we can advertise
809 * a plethora of combinations, we need to check each bit
810 * individually.
811 */
812
813 /*
814 * First we clear all the 10/100 mb speed bits in the Auto-Neg
815 * Advertisement Register (Address 4) and the 1000 mb speed bits in
816 * the 1000Base-T Control Register (Address 9).
817 */
818 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
819 NWAY_AR_100TX_HD_CAPS |
820 NWAY_AR_10T_FD_CAPS |
821 NWAY_AR_10T_HD_CAPS);
822 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
823
824 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
825
826 /* Do we want to advertise 10 Mb Half Duplex? */
827 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
828 hw_dbg(hw, "Advertise 10mb Half duplex\n");
829 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
830 }
831
832 /* Do we want to advertise 10 Mb Full Duplex? */
833 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
834 hw_dbg(hw, "Advertise 10mb Full duplex\n");
835 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
836 }
837
838 /* Do we want to advertise 100 Mb Half Duplex? */
839 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
840 hw_dbg(hw, "Advertise 100mb Half duplex\n");
841 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
842 }
843
844 /* Do we want to advertise 100 Mb Full Duplex? */
845 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
846 hw_dbg(hw, "Advertise 100mb Full duplex\n");
847 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
848 }
849
850 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
851 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
852 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
853
854 /* Do we want to advertise 1000 Mb Full Duplex? */
855 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
856 hw_dbg(hw, "Advertise 1000mb Full duplex\n");
857 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
858 }
859
860 /*
861 * Check for a software override of the flow control settings, and
862 * setup the PHY advertisement registers accordingly. If
863 * auto-negotiation is enabled, then software will have to set the
864 * "PAUSE" bits to the correct value in the Auto-Negotiation
865 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
866 * negotiation.
867 *
868 * The possible values of the "fc" parameter are:
869 * 0: Flow control is completely disabled
870 * 1: Rx flow control is enabled (we can receive pause frames
871 * but not send pause frames).
872 * 2: Tx flow control is enabled (we can send pause frames
873 * but we do not support receiving pause frames).
874 * 3: Both Rx and Tx flow control (symmetric) are enabled.
875 * other: No software override. The flow control configuration
876 * in the EEPROM is used.
877 */
878 switch (hw->fc.current_mode) {
879 case e1000_fc_none:
880 /*
881 * Flow control (Rx & Tx) is completely disabled by a
882 * software over-ride.
883 */
884 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
885 break;
886 case e1000_fc_rx_pause:
887 /*
888 * Rx Flow control is enabled, and Tx Flow control is
889 * disabled, by a software over-ride.
890 *
891 * Since there really isn't a way to advertise that we are
892 * capable of Rx Pause ONLY, we will advertise that we
893 * support both symmetric and asymmetric Rx PAUSE. Later
894 * (in e1000e_config_fc_after_link_up) we will disable the
895 * hw's ability to send PAUSE frames.
896 */
897 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
898 break;
899 case e1000_fc_tx_pause:
900 /*
901 * Tx Flow control is enabled, and Rx Flow control is
902 * disabled, by a software over-ride.
903 */
904 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
905 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
906 break;
907 case e1000_fc_full:
908 /*
909 * Flow control (both Rx and Tx) is enabled by a software
910 * over-ride.
911 */
912 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
913 break;
914 default:
915 hw_dbg(hw, "Flow control param set incorrectly\n");
916 ret_val = -E1000_ERR_CONFIG;
917 return ret_val;
918 }
919
920 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
921 if (ret_val)
922 return ret_val;
923
924 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
925
926 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
927 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
928 }
929
930 return ret_val;
931 }
932
933 /**
934 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
935 * @hw: pointer to the HW structure
936 *
937 * Performs initial bounds checking on autoneg advertisement parameter, then
938 * configure to advertise the full capability. Setup the PHY to autoneg
939 * and restart the negotiation process between the link partner. If
940 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
941 **/
942 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
943 {
944 struct e1000_phy_info *phy = &hw->phy;
945 s32 ret_val;
946 u16 phy_ctrl;
947
948 /*
949 * Perform some bounds checking on the autoneg advertisement
950 * parameter.
951 */
952 phy->autoneg_advertised &= phy->autoneg_mask;
953
954 /*
955 * If autoneg_advertised is zero, we assume it was not defaulted
956 * by the calling code so we set to advertise full capability.
957 */
958 if (phy->autoneg_advertised == 0)
959 phy->autoneg_advertised = phy->autoneg_mask;
960
961 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
962 ret_val = e1000_phy_setup_autoneg(hw);
963 if (ret_val) {
964 hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
965 return ret_val;
966 }
967 hw_dbg(hw, "Restarting Auto-Neg\n");
968
969 /*
970 * Restart auto-negotiation by setting the Auto Neg Enable bit and
971 * the Auto Neg Restart bit in the PHY control register.
972 */
973 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
974 if (ret_val)
975 return ret_val;
976
977 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
978 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
979 if (ret_val)
980 return ret_val;
981
982 /*
983 * Does the user want to wait for Auto-Neg to complete here, or
984 * check at a later time (for example, callback routine).
985 */
986 if (phy->autoneg_wait_to_complete) {
987 ret_val = e1000_wait_autoneg(hw);
988 if (ret_val) {
989 hw_dbg(hw, "Error while waiting for "
990 "autoneg to complete\n");
991 return ret_val;
992 }
993 }
994
995 hw->mac.get_link_status = 1;
996
997 return ret_val;
998 }
999
1000 /**
1001 * e1000e_setup_copper_link - Configure copper link settings
1002 * @hw: pointer to the HW structure
1003 *
1004 * Calls the appropriate function to configure the link for auto-neg or forced
1005 * speed and duplex. Then we check for link, once link is established calls
1006 * to configure collision distance and flow control are called. If link is
1007 * not established, we return -E1000_ERR_PHY (-2).
1008 **/
1009 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1010 {
1011 s32 ret_val;
1012 bool link;
1013
1014 if (hw->mac.autoneg) {
1015 /*
1016 * Setup autoneg and flow control advertisement and perform
1017 * autonegotiation.
1018 */
1019 ret_val = e1000_copper_link_autoneg(hw);
1020 if (ret_val)
1021 return ret_val;
1022 } else {
1023 /*
1024 * PHY will be set to 10H, 10F, 100H or 100F
1025 * depending on user settings.
1026 */
1027 hw_dbg(hw, "Forcing Speed and Duplex\n");
1028 ret_val = e1000_phy_force_speed_duplex(hw);
1029 if (ret_val) {
1030 hw_dbg(hw, "Error Forcing Speed and Duplex\n");
1031 return ret_val;
1032 }
1033 }
1034
1035 /*
1036 * Check link status. Wait up to 100 microseconds for link to become
1037 * valid.
1038 */
1039 ret_val = e1000e_phy_has_link_generic(hw,
1040 COPPER_LINK_UP_LIMIT,
1041 10,
1042 &link);
1043 if (ret_val)
1044 return ret_val;
1045
1046 if (link) {
1047 hw_dbg(hw, "Valid link established!!!\n");
1048 e1000e_config_collision_dist(hw);
1049 ret_val = e1000e_config_fc_after_link_up(hw);
1050 } else {
1051 hw_dbg(hw, "Unable to establish link!!!\n");
1052 }
1053
1054 return ret_val;
1055 }
1056
1057 /**
1058 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1059 * @hw: pointer to the HW structure
1060 *
1061 * Calls the PHY setup function to force speed and duplex. Clears the
1062 * auto-crossover to force MDI manually. Waits for link and returns
1063 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1064 **/
1065 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1066 {
1067 struct e1000_phy_info *phy = &hw->phy;
1068 s32 ret_val;
1069 u16 phy_data;
1070 bool link;
1071
1072 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1073 if (ret_val)
1074 return ret_val;
1075
1076 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1077
1078 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1079 if (ret_val)
1080 return ret_val;
1081
1082 /*
1083 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1084 * forced whenever speed and duplex are forced.
1085 */
1086 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1087 if (ret_val)
1088 return ret_val;
1089
1090 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1091 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1092
1093 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1094 if (ret_val)
1095 return ret_val;
1096
1097 hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
1098
1099 udelay(1);
1100
1101 if (phy->autoneg_wait_to_complete) {
1102 hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
1103
1104 ret_val = e1000e_phy_has_link_generic(hw,
1105 PHY_FORCE_LIMIT,
1106 100000,
1107 &link);
1108 if (ret_val)
1109 return ret_val;
1110
1111 if (!link)
1112 hw_dbg(hw, "Link taking longer than expected.\n");
1113
1114 /* Try once more */
1115 ret_val = e1000e_phy_has_link_generic(hw,
1116 PHY_FORCE_LIMIT,
1117 100000,
1118 &link);
1119 if (ret_val)
1120 return ret_val;
1121 }
1122
1123 return ret_val;
1124 }
1125
1126 /**
1127 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1128 * @hw: pointer to the HW structure
1129 *
1130 * Calls the PHY setup function to force speed and duplex. Clears the
1131 * auto-crossover to force MDI manually. Resets the PHY to commit the
1132 * changes. If time expires while waiting for link up, we reset the DSP.
1133 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1134 * successful completion, else return corresponding error code.
1135 **/
1136 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1137 {
1138 struct e1000_phy_info *phy = &hw->phy;
1139 s32 ret_val;
1140 u16 phy_data;
1141 bool link;
1142
1143 /*
1144 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1145 * forced whenever speed and duplex are forced.
1146 */
1147 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1148 if (ret_val)
1149 return ret_val;
1150
1151 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1152 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1153 if (ret_val)
1154 return ret_val;
1155
1156 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
1157
1158 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1159 if (ret_val)
1160 return ret_val;
1161
1162 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1163
1164 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1165 if (ret_val)
1166 return ret_val;
1167
1168 /* Reset the phy to commit changes. */
1169 ret_val = e1000e_commit_phy(hw);
1170 if (ret_val)
1171 return ret_val;
1172
1173 if (phy->autoneg_wait_to_complete) {
1174 hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
1175
1176 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1177 100000, &link);
1178 if (ret_val)
1179 return ret_val;
1180
1181 if (!link) {
1182 /*
1183 * We didn't get link.
1184 * Reset the DSP and cross our fingers.
1185 */
1186 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1187 0x001d);
1188 if (ret_val)
1189 return ret_val;
1190 ret_val = e1000e_phy_reset_dsp(hw);
1191 if (ret_val)
1192 return ret_val;
1193 }
1194
1195 /* Try once more */
1196 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1197 100000, &link);
1198 if (ret_val)
1199 return ret_val;
1200 }
1201
1202 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1203 if (ret_val)
1204 return ret_val;
1205
1206 /*
1207 * Resetting the phy means we need to re-force TX_CLK in the
1208 * Extended PHY Specific Control Register to 25MHz clock from
1209 * the reset value of 2.5MHz.
1210 */
1211 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1212 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1213 if (ret_val)
1214 return ret_val;
1215
1216 /*
1217 * In addition, we must re-enable CRS on Tx for both half and full
1218 * duplex.
1219 */
1220 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1221 if (ret_val)
1222 return ret_val;
1223
1224 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1225 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1226
1227 return ret_val;
1228 }
1229
1230 /**
1231 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1232 * @hw: pointer to the HW structure
1233 * @phy_ctrl: pointer to current value of PHY_CONTROL
1234 *
1235 * Forces speed and duplex on the PHY by doing the following: disable flow
1236 * control, force speed/duplex on the MAC, disable auto speed detection,
1237 * disable auto-negotiation, configure duplex, configure speed, configure
1238 * the collision distance, write configuration to CTRL register. The
1239 * caller must write to the PHY_CONTROL register for these settings to
1240 * take affect.
1241 **/
1242 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1243 {
1244 struct e1000_mac_info *mac = &hw->mac;
1245 u32 ctrl;
1246
1247 /* Turn off flow control when forcing speed/duplex */
1248 hw->fc.current_mode = e1000_fc_none;
1249
1250 /* Force speed/duplex on the mac */
1251 ctrl = er32(CTRL);
1252 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1253 ctrl &= ~E1000_CTRL_SPD_SEL;
1254
1255 /* Disable Auto Speed Detection */
1256 ctrl &= ~E1000_CTRL_ASDE;
1257
1258 /* Disable autoneg on the phy */
1259 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1260
1261 /* Forcing Full or Half Duplex? */
1262 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1263 ctrl &= ~E1000_CTRL_FD;
1264 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1265 hw_dbg(hw, "Half Duplex\n");
1266 } else {
1267 ctrl |= E1000_CTRL_FD;
1268 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1269 hw_dbg(hw, "Full Duplex\n");
1270 }
1271
1272 /* Forcing 10mb or 100mb? */
1273 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1274 ctrl |= E1000_CTRL_SPD_100;
1275 *phy_ctrl |= MII_CR_SPEED_100;
1276 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1277 hw_dbg(hw, "Forcing 100mb\n");
1278 } else {
1279 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1280 *phy_ctrl |= MII_CR_SPEED_10;
1281 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1282 hw_dbg(hw, "Forcing 10mb\n");
1283 }
1284
1285 e1000e_config_collision_dist(hw);
1286
1287 ew32(CTRL, ctrl);
1288 }
1289
1290 /**
1291 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1292 * @hw: pointer to the HW structure
1293 * @active: boolean used to enable/disable lplu
1294 *
1295 * Success returns 0, Failure returns 1
1296 *
1297 * The low power link up (lplu) state is set to the power management level D3
1298 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1299 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1300 * is used during Dx states where the power conservation is most important.
1301 * During driver activity, SmartSpeed should be enabled so performance is
1302 * maintained.
1303 **/
1304 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1305 {
1306 struct e1000_phy_info *phy = &hw->phy;
1307 s32 ret_val;
1308 u16 data;
1309
1310 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1311 if (ret_val)
1312 return ret_val;
1313
1314 if (!active) {
1315 data &= ~IGP02E1000_PM_D3_LPLU;
1316 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1317 if (ret_val)
1318 return ret_val;
1319 /*
1320 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1321 * during Dx states where the power conservation is most
1322 * important. During driver activity we should enable
1323 * SmartSpeed, so performance is maintained.
1324 */
1325 if (phy->smart_speed == e1000_smart_speed_on) {
1326 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1327 &data);
1328 if (ret_val)
1329 return ret_val;
1330
1331 data |= IGP01E1000_PSCFR_SMART_SPEED;
1332 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1333 data);
1334 if (ret_val)
1335 return ret_val;
1336 } else if (phy->smart_speed == e1000_smart_speed_off) {
1337 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1338 &data);
1339 if (ret_val)
1340 return ret_val;
1341
1342 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1343 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1344 data);
1345 if (ret_val)
1346 return ret_val;
1347 }
1348 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1349 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1350 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1351 data |= IGP02E1000_PM_D3_LPLU;
1352 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1353 if (ret_val)
1354 return ret_val;
1355
1356 /* When LPLU is enabled, we should disable SmartSpeed */
1357 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1358 if (ret_val)
1359 return ret_val;
1360
1361 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1362 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1363 }
1364
1365 return ret_val;
1366 }
1367
1368 /**
1369 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1370 * @hw: pointer to the HW structure
1371 *
1372 * Success returns 0, Failure returns 1
1373 *
1374 * A downshift is detected by querying the PHY link health.
1375 **/
1376 s32 e1000e_check_downshift(struct e1000_hw *hw)
1377 {
1378 struct e1000_phy_info *phy = &hw->phy;
1379 s32 ret_val;
1380 u16 phy_data, offset, mask;
1381
1382 switch (phy->type) {
1383 case e1000_phy_m88:
1384 case e1000_phy_gg82563:
1385 case e1000_phy_82578:
1386 case e1000_phy_82577:
1387 offset = M88E1000_PHY_SPEC_STATUS;
1388 mask = M88E1000_PSSR_DOWNSHIFT;
1389 break;
1390 case e1000_phy_igp_2:
1391 case e1000_phy_igp_3:
1392 offset = IGP01E1000_PHY_LINK_HEALTH;
1393 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1394 break;
1395 default:
1396 /* speed downshift not supported */
1397 phy->speed_downgraded = 0;
1398 return 0;
1399 }
1400
1401 ret_val = e1e_rphy(hw, offset, &phy_data);
1402
1403 if (!ret_val)
1404 phy->speed_downgraded = (phy_data & mask);
1405
1406 return ret_val;
1407 }
1408
1409 /**
1410 * e1000_check_polarity_m88 - Checks the polarity.
1411 * @hw: pointer to the HW structure
1412 *
1413 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1414 *
1415 * Polarity is determined based on the PHY specific status register.
1416 **/
1417 static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1418 {
1419 struct e1000_phy_info *phy = &hw->phy;
1420 s32 ret_val;
1421 u16 data;
1422
1423 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1424
1425 if (!ret_val)
1426 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1427 ? e1000_rev_polarity_reversed
1428 : e1000_rev_polarity_normal;
1429
1430 return ret_val;
1431 }
1432
1433 /**
1434 * e1000_check_polarity_igp - Checks the polarity.
1435 * @hw: pointer to the HW structure
1436 *
1437 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1438 *
1439 * Polarity is determined based on the PHY port status register, and the
1440 * current speed (since there is no polarity at 100Mbps).
1441 **/
1442 static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1443 {
1444 struct e1000_phy_info *phy = &hw->phy;
1445 s32 ret_val;
1446 u16 data, offset, mask;
1447
1448 /*
1449 * Polarity is determined based on the speed of
1450 * our connection.
1451 */
1452 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1453 if (ret_val)
1454 return ret_val;
1455
1456 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1457 IGP01E1000_PSSR_SPEED_1000MBPS) {
1458 offset = IGP01E1000_PHY_PCS_INIT_REG;
1459 mask = IGP01E1000_PHY_POLARITY_MASK;
1460 } else {
1461 /*
1462 * This really only applies to 10Mbps since
1463 * there is no polarity for 100Mbps (always 0).
1464 */
1465 offset = IGP01E1000_PHY_PORT_STATUS;
1466 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1467 }
1468
1469 ret_val = e1e_rphy(hw, offset, &data);
1470
1471 if (!ret_val)
1472 phy->cable_polarity = (data & mask)
1473 ? e1000_rev_polarity_reversed
1474 : e1000_rev_polarity_normal;
1475
1476 return ret_val;
1477 }
1478
1479 /**
1480 * e1000_wait_autoneg - Wait for auto-neg completion
1481 * @hw: pointer to the HW structure
1482 *
1483 * Waits for auto-negotiation to complete or for the auto-negotiation time
1484 * limit to expire, which ever happens first.
1485 **/
1486 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1487 {
1488 s32 ret_val = 0;
1489 u16 i, phy_status;
1490
1491 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1492 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1493 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1494 if (ret_val)
1495 break;
1496 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1497 if (ret_val)
1498 break;
1499 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1500 break;
1501 msleep(100);
1502 }
1503
1504 /*
1505 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1506 * has completed.
1507 */
1508 return ret_val;
1509 }
1510
1511 /**
1512 * e1000e_phy_has_link_generic - Polls PHY for link
1513 * @hw: pointer to the HW structure
1514 * @iterations: number of times to poll for link
1515 * @usec_interval: delay between polling attempts
1516 * @success: pointer to whether polling was successful or not
1517 *
1518 * Polls the PHY status register for link, 'iterations' number of times.
1519 **/
1520 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1521 u32 usec_interval, bool *success)
1522 {
1523 s32 ret_val = 0;
1524 u16 i, phy_status;
1525
1526 for (i = 0; i < iterations; i++) {
1527 /*
1528 * Some PHYs require the PHY_STATUS register to be read
1529 * twice due to the link bit being sticky. No harm doing
1530 * it across the board.
1531 */
1532 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1533 if (ret_val)
1534 /*
1535 * If the first read fails, another entity may have
1536 * ownership of the resources, wait and try again to
1537 * see if they have relinquished the resources yet.
1538 */
1539 udelay(usec_interval);
1540 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1541 if (ret_val)
1542 break;
1543 if (phy_status & MII_SR_LINK_STATUS)
1544 break;
1545 if (usec_interval >= 1000)
1546 mdelay(usec_interval/1000);
1547 else
1548 udelay(usec_interval);
1549 }
1550
1551 *success = (i < iterations);
1552
1553 return ret_val;
1554 }
1555
1556 /**
1557 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1558 * @hw: pointer to the HW structure
1559 *
1560 * Reads the PHY specific status register to retrieve the cable length
1561 * information. The cable length is determined by averaging the minimum and
1562 * maximum values to get the "average" cable length. The m88 PHY has four
1563 * possible cable length values, which are:
1564 * Register Value Cable Length
1565 * 0 < 50 meters
1566 * 1 50 - 80 meters
1567 * 2 80 - 110 meters
1568 * 3 110 - 140 meters
1569 * 4 > 140 meters
1570 **/
1571 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1572 {
1573 struct e1000_phy_info *phy = &hw->phy;
1574 s32 ret_val;
1575 u16 phy_data, index;
1576
1577 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1578 if (ret_val)
1579 return ret_val;
1580
1581 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1582 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1583 phy->min_cable_length = e1000_m88_cable_length_table[index];
1584 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1585
1586 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1587
1588 return ret_val;
1589 }
1590
1591 /**
1592 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1593 * @hw: pointer to the HW structure
1594 *
1595 * The automatic gain control (agc) normalizes the amplitude of the
1596 * received signal, adjusting for the attenuation produced by the
1597 * cable. By reading the AGC registers, which represent the
1598 * combination of course and fine gain value, the value can be put
1599 * into a lookup table to obtain the approximate cable length
1600 * for each channel.
1601 **/
1602 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1603 {
1604 struct e1000_phy_info *phy = &hw->phy;
1605 s32 ret_val;
1606 u16 phy_data, i, agc_value = 0;
1607 u16 cur_agc_index, max_agc_index = 0;
1608 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1609 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1610 {IGP02E1000_PHY_AGC_A,
1611 IGP02E1000_PHY_AGC_B,
1612 IGP02E1000_PHY_AGC_C,
1613 IGP02E1000_PHY_AGC_D};
1614
1615 /* Read the AGC registers for all channels */
1616 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1617 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1618 if (ret_val)
1619 return ret_val;
1620
1621 /*
1622 * Getting bits 15:9, which represent the combination of
1623 * course and fine gain values. The result is a number
1624 * that can be put into the lookup table to obtain the
1625 * approximate cable length.
1626 */
1627 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1628 IGP02E1000_AGC_LENGTH_MASK;
1629
1630 /* Array index bound check. */
1631 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1632 (cur_agc_index == 0))
1633 return -E1000_ERR_PHY;
1634
1635 /* Remove min & max AGC values from calculation. */
1636 if (e1000_igp_2_cable_length_table[min_agc_index] >
1637 e1000_igp_2_cable_length_table[cur_agc_index])
1638 min_agc_index = cur_agc_index;
1639 if (e1000_igp_2_cable_length_table[max_agc_index] <
1640 e1000_igp_2_cable_length_table[cur_agc_index])
1641 max_agc_index = cur_agc_index;
1642
1643 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1644 }
1645
1646 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1647 e1000_igp_2_cable_length_table[max_agc_index]);
1648 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1649
1650 /* Calculate cable length with the error range of +/- 10 meters. */
1651 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1652 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1653 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1654
1655 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1656
1657 return ret_val;
1658 }
1659
1660 /**
1661 * e1000e_get_phy_info_m88 - Retrieve PHY information
1662 * @hw: pointer to the HW structure
1663 *
1664 * Valid for only copper links. Read the PHY status register (sticky read)
1665 * to verify that link is up. Read the PHY special control register to
1666 * determine the polarity and 10base-T extended distance. Read the PHY
1667 * special status register to determine MDI/MDIx and current speed. If
1668 * speed is 1000, then determine cable length, local and remote receiver.
1669 **/
1670 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1671 {
1672 struct e1000_phy_info *phy = &hw->phy;
1673 s32 ret_val;
1674 u16 phy_data;
1675 bool link;
1676
1677 if (hw->phy.media_type != e1000_media_type_copper) {
1678 hw_dbg(hw, "Phy info is only valid for copper media\n");
1679 return -E1000_ERR_CONFIG;
1680 }
1681
1682 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1683 if (ret_val)
1684 return ret_val;
1685
1686 if (!link) {
1687 hw_dbg(hw, "Phy info is only valid if link is up\n");
1688 return -E1000_ERR_CONFIG;
1689 }
1690
1691 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1692 if (ret_val)
1693 return ret_val;
1694
1695 phy->polarity_correction = (phy_data &
1696 M88E1000_PSCR_POLARITY_REVERSAL);
1697
1698 ret_val = e1000_check_polarity_m88(hw);
1699 if (ret_val)
1700 return ret_val;
1701
1702 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1703 if (ret_val)
1704 return ret_val;
1705
1706 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1707
1708 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1709 ret_val = e1000_get_cable_length(hw);
1710 if (ret_val)
1711 return ret_val;
1712
1713 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1714 if (ret_val)
1715 return ret_val;
1716
1717 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1718 ? e1000_1000t_rx_status_ok
1719 : e1000_1000t_rx_status_not_ok;
1720
1721 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1722 ? e1000_1000t_rx_status_ok
1723 : e1000_1000t_rx_status_not_ok;
1724 } else {
1725 /* Set values to "undefined" */
1726 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1727 phy->local_rx = e1000_1000t_rx_status_undefined;
1728 phy->remote_rx = e1000_1000t_rx_status_undefined;
1729 }
1730
1731 return ret_val;
1732 }
1733
1734 /**
1735 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1736 * @hw: pointer to the HW structure
1737 *
1738 * Read PHY status to determine if link is up. If link is up, then
1739 * set/determine 10base-T extended distance and polarity correction. Read
1740 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1741 * determine on the cable length, local and remote receiver.
1742 **/
1743 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1744 {
1745 struct e1000_phy_info *phy = &hw->phy;
1746 s32 ret_val;
1747 u16 data;
1748 bool link;
1749
1750 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1751 if (ret_val)
1752 return ret_val;
1753
1754 if (!link) {
1755 hw_dbg(hw, "Phy info is only valid if link is up\n");
1756 return -E1000_ERR_CONFIG;
1757 }
1758
1759 phy->polarity_correction = 1;
1760
1761 ret_val = e1000_check_polarity_igp(hw);
1762 if (ret_val)
1763 return ret_val;
1764
1765 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1766 if (ret_val)
1767 return ret_val;
1768
1769 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
1770
1771 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1772 IGP01E1000_PSSR_SPEED_1000MBPS) {
1773 ret_val = e1000_get_cable_length(hw);
1774 if (ret_val)
1775 return ret_val;
1776
1777 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
1778 if (ret_val)
1779 return ret_val;
1780
1781 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1782 ? e1000_1000t_rx_status_ok
1783 : e1000_1000t_rx_status_not_ok;
1784
1785 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1786 ? e1000_1000t_rx_status_ok
1787 : e1000_1000t_rx_status_not_ok;
1788 } else {
1789 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1790 phy->local_rx = e1000_1000t_rx_status_undefined;
1791 phy->remote_rx = e1000_1000t_rx_status_undefined;
1792 }
1793
1794 return ret_val;
1795 }
1796
1797 /**
1798 * e1000e_phy_sw_reset - PHY software reset
1799 * @hw: pointer to the HW structure
1800 *
1801 * Does a software reset of the PHY by reading the PHY control register and
1802 * setting/write the control register reset bit to the PHY.
1803 **/
1804 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
1805 {
1806 s32 ret_val;
1807 u16 phy_ctrl;
1808
1809 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1810 if (ret_val)
1811 return ret_val;
1812
1813 phy_ctrl |= MII_CR_RESET;
1814 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1815 if (ret_val)
1816 return ret_val;
1817
1818 udelay(1);
1819
1820 return ret_val;
1821 }
1822
1823 /**
1824 * e1000e_phy_hw_reset_generic - PHY hardware reset
1825 * @hw: pointer to the HW structure
1826 *
1827 * Verify the reset block is not blocking us from resetting. Acquire
1828 * semaphore (if necessary) and read/set/write the device control reset
1829 * bit in the PHY. Wait the appropriate delay time for the device to
1830 * reset and release the semaphore (if necessary).
1831 **/
1832 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1833 {
1834 struct e1000_phy_info *phy = &hw->phy;
1835 s32 ret_val;
1836 u32 ctrl;
1837
1838 ret_val = e1000_check_reset_block(hw);
1839 if (ret_val)
1840 return 0;
1841
1842 ret_val = phy->ops.acquire_phy(hw);
1843 if (ret_val)
1844 return ret_val;
1845
1846 ctrl = er32(CTRL);
1847 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
1848 e1e_flush();
1849
1850 udelay(phy->reset_delay_us);
1851
1852 ew32(CTRL, ctrl);
1853 e1e_flush();
1854
1855 udelay(150);
1856
1857 phy->ops.release_phy(hw);
1858
1859 return e1000_get_phy_cfg_done(hw);
1860 }
1861
1862 /**
1863 * e1000e_get_cfg_done - Generic configuration done
1864 * @hw: pointer to the HW structure
1865 *
1866 * Generic function to wait 10 milli-seconds for configuration to complete
1867 * and return success.
1868 **/
1869 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
1870 {
1871 mdelay(10);
1872 return 0;
1873 }
1874
1875 /**
1876 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
1877 * @hw: pointer to the HW structure
1878 *
1879 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1880 **/
1881 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
1882 {
1883 hw_dbg(hw, "Running IGP 3 PHY init script\n");
1884
1885 /* PHY init IGP 3 */
1886 /* Enable rise/fall, 10-mode work in class-A */
1887 e1e_wphy(hw, 0x2F5B, 0x9018);
1888 /* Remove all caps from Replica path filter */
1889 e1e_wphy(hw, 0x2F52, 0x0000);
1890 /* Bias trimming for ADC, AFE and Driver (Default) */
1891 e1e_wphy(hw, 0x2FB1, 0x8B24);
1892 /* Increase Hybrid poly bias */
1893 e1e_wphy(hw, 0x2FB2, 0xF8F0);
1894 /* Add 4% to Tx amplitude in Gig mode */
1895 e1e_wphy(hw, 0x2010, 0x10B0);
1896 /* Disable trimming (TTT) */
1897 e1e_wphy(hw, 0x2011, 0x0000);
1898 /* Poly DC correction to 94.6% + 2% for all channels */
1899 e1e_wphy(hw, 0x20DD, 0x249A);
1900 /* ABS DC correction to 95.9% */
1901 e1e_wphy(hw, 0x20DE, 0x00D3);
1902 /* BG temp curve trim */
1903 e1e_wphy(hw, 0x28B4, 0x04CE);
1904 /* Increasing ADC OPAMP stage 1 currents to max */
1905 e1e_wphy(hw, 0x2F70, 0x29E4);
1906 /* Force 1000 ( required for enabling PHY regs configuration) */
1907 e1e_wphy(hw, 0x0000, 0x0140);
1908 /* Set upd_freq to 6 */
1909 e1e_wphy(hw, 0x1F30, 0x1606);
1910 /* Disable NPDFE */
1911 e1e_wphy(hw, 0x1F31, 0xB814);
1912 /* Disable adaptive fixed FFE (Default) */
1913 e1e_wphy(hw, 0x1F35, 0x002A);
1914 /* Enable FFE hysteresis */
1915 e1e_wphy(hw, 0x1F3E, 0x0067);
1916 /* Fixed FFE for short cable lengths */
1917 e1e_wphy(hw, 0x1F54, 0x0065);
1918 /* Fixed FFE for medium cable lengths */
1919 e1e_wphy(hw, 0x1F55, 0x002A);
1920 /* Fixed FFE for long cable lengths */
1921 e1e_wphy(hw, 0x1F56, 0x002A);
1922 /* Enable Adaptive Clip Threshold */
1923 e1e_wphy(hw, 0x1F72, 0x3FB0);
1924 /* AHT reset limit to 1 */
1925 e1e_wphy(hw, 0x1F76, 0xC0FF);
1926 /* Set AHT master delay to 127 msec */
1927 e1e_wphy(hw, 0x1F77, 0x1DEC);
1928 /* Set scan bits for AHT */
1929 e1e_wphy(hw, 0x1F78, 0xF9EF);
1930 /* Set AHT Preset bits */
1931 e1e_wphy(hw, 0x1F79, 0x0210);
1932 /* Change integ_factor of channel A to 3 */
1933 e1e_wphy(hw, 0x1895, 0x0003);
1934 /* Change prop_factor of channels BCD to 8 */
1935 e1e_wphy(hw, 0x1796, 0x0008);
1936 /* Change cg_icount + enable integbp for channels BCD */
1937 e1e_wphy(hw, 0x1798, 0xD008);
1938 /*
1939 * Change cg_icount + enable integbp + change prop_factor_master
1940 * to 8 for channel A
1941 */
1942 e1e_wphy(hw, 0x1898, 0xD918);
1943 /* Disable AHT in Slave mode on channel A */
1944 e1e_wphy(hw, 0x187A, 0x0800);
1945 /*
1946 * Enable LPLU and disable AN to 1000 in non-D0a states,
1947 * Enable SPD+B2B
1948 */
1949 e1e_wphy(hw, 0x0019, 0x008D);
1950 /* Enable restart AN on an1000_dis change */
1951 e1e_wphy(hw, 0x001B, 0x2080);
1952 /* Enable wh_fifo read clock in 10/100 modes */
1953 e1e_wphy(hw, 0x0014, 0x0045);
1954 /* Restart AN, Speed selection is 1000 */
1955 e1e_wphy(hw, 0x0000, 0x1340);
1956
1957 return 0;
1958 }
1959
1960 /* Internal function pointers */
1961
1962 /**
1963 * e1000_get_phy_cfg_done - Generic PHY configuration done
1964 * @hw: pointer to the HW structure
1965 *
1966 * Return success if silicon family did not implement a family specific
1967 * get_cfg_done function.
1968 **/
1969 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
1970 {
1971 if (hw->phy.ops.get_cfg_done)
1972 return hw->phy.ops.get_cfg_done(hw);
1973
1974 return 0;
1975 }
1976
1977 /**
1978 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1979 * @hw: pointer to the HW structure
1980 *
1981 * When the silicon family has not implemented a forced speed/duplex
1982 * function for the PHY, simply return 0.
1983 **/
1984 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1985 {
1986 if (hw->phy.ops.force_speed_duplex)
1987 return hw->phy.ops.force_speed_duplex(hw);
1988
1989 return 0;
1990 }
1991
1992 /**
1993 * e1000e_get_phy_type_from_id - Get PHY type from id
1994 * @phy_id: phy_id read from the phy
1995 *
1996 * Returns the phy type from the id.
1997 **/
1998 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
1999 {
2000 enum e1000_phy_type phy_type = e1000_phy_unknown;
2001
2002 switch (phy_id) {
2003 case M88E1000_I_PHY_ID:
2004 case M88E1000_E_PHY_ID:
2005 case M88E1111_I_PHY_ID:
2006 case M88E1011_I_PHY_ID:
2007 phy_type = e1000_phy_m88;
2008 break;
2009 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2010 phy_type = e1000_phy_igp_2;
2011 break;
2012 case GG82563_E_PHY_ID:
2013 phy_type = e1000_phy_gg82563;
2014 break;
2015 case IGP03E1000_E_PHY_ID:
2016 phy_type = e1000_phy_igp_3;
2017 break;
2018 case IFE_E_PHY_ID:
2019 case IFE_PLUS_E_PHY_ID:
2020 case IFE_C_E_PHY_ID:
2021 phy_type = e1000_phy_ife;
2022 break;
2023 case BME1000_E_PHY_ID:
2024 case BME1000_E_PHY_ID_R2:
2025 phy_type = e1000_phy_bm;
2026 break;
2027 case I82578_E_PHY_ID:
2028 phy_type = e1000_phy_82578;
2029 break;
2030 case I82577_E_PHY_ID:
2031 phy_type = e1000_phy_82577;
2032 break;
2033 default:
2034 phy_type = e1000_phy_unknown;
2035 break;
2036 }
2037 return phy_type;
2038 }
2039
2040 /**
2041 * e1000e_determine_phy_address - Determines PHY address.
2042 * @hw: pointer to the HW structure
2043 *
2044 * This uses a trial and error method to loop through possible PHY
2045 * addresses. It tests each by reading the PHY ID registers and
2046 * checking for a match.
2047 **/
2048 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2049 {
2050 s32 ret_val = -E1000_ERR_PHY_TYPE;
2051 u32 phy_addr= 0;
2052 u32 i = 0;
2053 enum e1000_phy_type phy_type = e1000_phy_unknown;
2054
2055 do {
2056 for (phy_addr = 0; phy_addr < 4; phy_addr++) {
2057 hw->phy.addr = phy_addr;
2058 e1000e_get_phy_id(hw);
2059 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2060
2061 /*
2062 * If phy_type is valid, break - we found our
2063 * PHY address
2064 */
2065 if (phy_type != e1000_phy_unknown) {
2066 ret_val = 0;
2067 break;
2068 }
2069 }
2070 i++;
2071 } while ((ret_val != 0) && (i < 100));
2072
2073 return ret_val;
2074 }
2075
2076 /**
2077 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2078 * @page: page to access
2079 *
2080 * Returns the phy address for the page requested.
2081 **/
2082 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2083 {
2084 u32 phy_addr = 2;
2085
2086 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2087 phy_addr = 1;
2088
2089 return phy_addr;
2090 }
2091
2092 /**
2093 * e1000e_write_phy_reg_bm - Write BM PHY register
2094 * @hw: pointer to the HW structure
2095 * @offset: register offset to write to
2096 * @data: data to write at register offset
2097 *
2098 * Acquires semaphore, if necessary, then writes the data to PHY register
2099 * at the offset. Release any acquired semaphores before exiting.
2100 **/
2101 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2102 {
2103 s32 ret_val;
2104 u32 page_select = 0;
2105 u32 page = offset >> IGP_PAGE_SHIFT;
2106 u32 page_shift = 0;
2107
2108 /* Page 800 works differently than the rest so it has its own func */
2109 if (page == BM_WUC_PAGE) {
2110 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2111 false);
2112 goto out;
2113 }
2114
2115 ret_val = hw->phy.ops.acquire_phy(hw);
2116 if (ret_val)
2117 goto out;
2118
2119 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2120
2121 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2122 /*
2123 * Page select is register 31 for phy address 1 and 22 for
2124 * phy address 2 and 3. Page select is shifted only for
2125 * phy address 1.
2126 */
2127 if (hw->phy.addr == 1) {
2128 page_shift = IGP_PAGE_SHIFT;
2129 page_select = IGP01E1000_PHY_PAGE_SELECT;
2130 } else {
2131 page_shift = 0;
2132 page_select = BM_PHY_PAGE_SELECT;
2133 }
2134
2135 /* Page is shifted left, PHY expects (page x 32) */
2136 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2137 (page << page_shift));
2138 if (ret_val) {
2139 hw->phy.ops.release_phy(hw);
2140 goto out;
2141 }
2142 }
2143
2144 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2145 data);
2146
2147 hw->phy.ops.release_phy(hw);
2148
2149 out:
2150 return ret_val;
2151 }
2152
2153 /**
2154 * e1000e_read_phy_reg_bm - Read BM PHY register
2155 * @hw: pointer to the HW structure
2156 * @offset: register offset to be read
2157 * @data: pointer to the read data
2158 *
2159 * Acquires semaphore, if necessary, then reads the PHY register at offset
2160 * and storing the retrieved information in data. Release any acquired
2161 * semaphores before exiting.
2162 **/
2163 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2164 {
2165 s32 ret_val;
2166 u32 page_select = 0;
2167 u32 page = offset >> IGP_PAGE_SHIFT;
2168 u32 page_shift = 0;
2169
2170 /* Page 800 works differently than the rest so it has its own func */
2171 if (page == BM_WUC_PAGE) {
2172 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2173 true);
2174 goto out;
2175 }
2176
2177 ret_val = hw->phy.ops.acquire_phy(hw);
2178 if (ret_val)
2179 goto out;
2180
2181 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2182
2183 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2184 /*
2185 * Page select is register 31 for phy address 1 and 22 for
2186 * phy address 2 and 3. Page select is shifted only for
2187 * phy address 1.
2188 */
2189 if (hw->phy.addr == 1) {
2190 page_shift = IGP_PAGE_SHIFT;
2191 page_select = IGP01E1000_PHY_PAGE_SELECT;
2192 } else {
2193 page_shift = 0;
2194 page_select = BM_PHY_PAGE_SELECT;
2195 }
2196
2197 /* Page is shifted left, PHY expects (page x 32) */
2198 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2199 (page << page_shift));
2200 if (ret_val) {
2201 hw->phy.ops.release_phy(hw);
2202 goto out;
2203 }
2204 }
2205
2206 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2207 data);
2208 hw->phy.ops.release_phy(hw);
2209
2210 out:
2211 return ret_val;
2212 }
2213
2214 /**
2215 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2216 * @hw: pointer to the HW structure
2217 * @offset: register offset to be read
2218 * @data: pointer to the read data
2219 *
2220 * Acquires semaphore, if necessary, then reads the PHY register at offset
2221 * and storing the retrieved information in data. Release any acquired
2222 * semaphores before exiting.
2223 **/
2224 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2225 {
2226 s32 ret_val;
2227 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2228
2229 /* Page 800 works differently than the rest so it has its own func */
2230 if (page == BM_WUC_PAGE) {
2231 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2232 true);
2233 return ret_val;
2234 }
2235
2236 ret_val = hw->phy.ops.acquire_phy(hw);
2237 if (ret_val)
2238 return ret_val;
2239
2240 hw->phy.addr = 1;
2241
2242 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2243
2244 /* Page is shifted left, PHY expects (page x 32) */
2245 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2246 page);
2247
2248 if (ret_val) {
2249 hw->phy.ops.release_phy(hw);
2250 return ret_val;
2251 }
2252 }
2253
2254 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2255 data);
2256 hw->phy.ops.release_phy(hw);
2257
2258 return ret_val;
2259 }
2260
2261 /**
2262 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2263 * @hw: pointer to the HW structure
2264 * @offset: register offset to write to
2265 * @data: data to write at register offset
2266 *
2267 * Acquires semaphore, if necessary, then writes the data to PHY register
2268 * at the offset. Release any acquired semaphores before exiting.
2269 **/
2270 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2271 {
2272 s32 ret_val;
2273 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2274
2275 /* Page 800 works differently than the rest so it has its own func */
2276 if (page == BM_WUC_PAGE) {
2277 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2278 false);
2279 return ret_val;
2280 }
2281
2282 ret_val = hw->phy.ops.acquire_phy(hw);
2283 if (ret_val)
2284 return ret_val;
2285
2286 hw->phy.addr = 1;
2287
2288 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2289 /* Page is shifted left, PHY expects (page x 32) */
2290 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2291 page);
2292
2293 if (ret_val) {
2294 hw->phy.ops.release_phy(hw);
2295 return ret_val;
2296 }
2297 }
2298
2299 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2300 data);
2301
2302 hw->phy.ops.release_phy(hw);
2303
2304 return ret_val;
2305 }
2306
2307 /**
2308 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2309 * @hw: pointer to the HW structure
2310 * @offset: register offset to be read or written
2311 * @data: pointer to the data to read or write
2312 * @read: determines if operation is read or write
2313 *
2314 * Acquires semaphore, if necessary, then reads the PHY register at offset
2315 * and storing the retrieved information in data. Release any acquired
2316 * semaphores before exiting. Note that procedure to read the wakeup
2317 * registers are different. It works as such:
2318 * 1) Set page 769, register 17, bit 2 = 1
2319 * 2) Set page to 800 for host (801 if we were manageability)
2320 * 3) Write the address using the address opcode (0x11)
2321 * 4) Read or write the data using the data opcode (0x12)
2322 * 5) Restore 769_17.2 to its original value
2323 **/
2324 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2325 u16 *data, bool read)
2326 {
2327 s32 ret_val;
2328 u16 reg = BM_PHY_REG_NUM(offset);
2329 u16 phy_reg = 0;
2330 u8 phy_acquired = 1;
2331
2332
2333 /* Gig must be disabled for MDIO accesses to page 800 */
2334 if ((hw->mac.type == e1000_pchlan) &&
2335 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2336 hw_dbg(hw, "Attempting to access page 800 while gig enabled\n");
2337
2338 ret_val = hw->phy.ops.acquire_phy(hw);
2339 if (ret_val) {
2340 phy_acquired = 0;
2341 goto out;
2342 }
2343
2344 /* All operations in this function are phy address 1 */
2345 hw->phy.addr = 1;
2346
2347 /* Set page 769 */
2348 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2349 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2350
2351 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2352 if (ret_val)
2353 goto out;
2354
2355 /* First clear bit 4 to avoid a power state change */
2356 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2357 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2358 if (ret_val)
2359 goto out;
2360
2361 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2362 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2363 phy_reg | BM_WUC_ENABLE_BIT);
2364 if (ret_val)
2365 goto out;
2366
2367 /* Select page 800 */
2368 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2369 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2370
2371 /* Write the page 800 offset value using opcode 0x11 */
2372 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2373 if (ret_val)
2374 goto out;
2375
2376 if (read) {
2377 /* Read the page 800 value using opcode 0x12 */
2378 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2379 data);
2380 } else {
2381 /* Read the page 800 value using opcode 0x12 */
2382 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2383 *data);
2384 }
2385
2386 if (ret_val)
2387 goto out;
2388
2389 /*
2390 * Restore 769_17.2 to its original value
2391 * Set page 769
2392 */
2393 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2394 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2395
2396 /* Clear 769_17.2 */
2397 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2398
2399 out:
2400 if (phy_acquired == 1)
2401 hw->phy.ops.release_phy(hw);
2402 return ret_val;
2403 }
2404
2405 /**
2406 * e1000e_commit_phy - Soft PHY reset
2407 * @hw: pointer to the HW structure
2408 *
2409 * Performs a soft PHY reset on those that apply. This is a function pointer
2410 * entry point called by drivers.
2411 **/
2412 s32 e1000e_commit_phy(struct e1000_hw *hw)
2413 {
2414 if (hw->phy.ops.commit_phy)
2415 return hw->phy.ops.commit_phy(hw);
2416
2417 return 0;
2418 }
2419
2420 /**
2421 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2422 * @hw: pointer to the HW structure
2423 * @active: boolean used to enable/disable lplu
2424 *
2425 * Success returns 0, Failure returns 1
2426 *
2427 * The low power link up (lplu) state is set to the power management level D0
2428 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2429 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2430 * is used during Dx states where the power conservation is most important.
2431 * During driver activity, SmartSpeed should be enabled so performance is
2432 * maintained. This is a function pointer entry point called by drivers.
2433 **/
2434 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2435 {
2436 if (hw->phy.ops.set_d0_lplu_state)
2437 return hw->phy.ops.set_d0_lplu_state(hw, active);
2438
2439 return 0;
2440 }
2441
2442 s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow)
2443 {
2444 s32 ret_val = 0;
2445 u16 data = 0;
2446
2447 ret_val = hw->phy.ops.acquire_phy(hw);
2448 if (ret_val)
2449 return ret_val;
2450
2451 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
2452 hw->phy.addr = 1;
2453 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2454 (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2455 if (ret_val) {
2456 hw->phy.ops.release_phy(hw);
2457 return ret_val;
2458 }
2459 ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1,
2460 (0x2180 | (slow << 10)));
2461
2462 /* dummy read when reverting to fast mode - throw away result */
2463 if (!slow)
2464 e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data);
2465
2466 hw->phy.ops.release_phy(hw);
2467
2468 return ret_val;
2469 }
2470
2471 /**
2472 * e1000_read_phy_reg_hv - Read HV PHY register
2473 * @hw: pointer to the HW structure
2474 * @offset: register offset to be read
2475 * @data: pointer to the read data
2476 *
2477 * Acquires semaphore, if necessary, then reads the PHY register at offset
2478 * and storing the retrieved information in data. Release any acquired
2479 * semaphore before exiting.
2480 **/
2481 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2482 {
2483 s32 ret_val;
2484 u16 page = BM_PHY_REG_PAGE(offset);
2485 u16 reg = BM_PHY_REG_NUM(offset);
2486 bool in_slow_mode = false;
2487
2488 /* Workaround failure in MDIO access while cable is disconnected */
2489 if ((hw->phy.type == e1000_phy_82577) &&
2490 !(er32(STATUS) & E1000_STATUS_LU)) {
2491 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
2492 if (ret_val)
2493 goto out;
2494
2495 in_slow_mode = true;
2496 }
2497
2498 /* Page 800 works differently than the rest so it has its own func */
2499 if (page == BM_WUC_PAGE) {
2500 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2501 data, true);
2502 goto out;
2503 }
2504
2505 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2506 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2507 data, true);
2508 goto out;
2509 }
2510
2511 ret_val = hw->phy.ops.acquire_phy(hw);
2512 if (ret_val)
2513 goto out;
2514
2515 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2516
2517 if (page == HV_INTC_FC_PAGE_START)
2518 page = 0;
2519
2520 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2521 if ((hw->phy.type != e1000_phy_82578) ||
2522 ((reg != I82578_ADDR_REG) &&
2523 (reg != I82578_ADDR_REG + 1))) {
2524 u32 phy_addr = hw->phy.addr;
2525
2526 hw->phy.addr = 1;
2527
2528 /* Page is shifted left, PHY expects (page x 32) */
2529 ret_val = e1000e_write_phy_reg_mdic(hw,
2530 IGP01E1000_PHY_PAGE_SELECT,
2531 (page << IGP_PAGE_SHIFT));
2532 if (ret_val) {
2533 hw->phy.ops.release_phy(hw);
2534 goto out;
2535 }
2536 hw->phy.addr = phy_addr;
2537 }
2538 }
2539
2540 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2541 data);
2542 hw->phy.ops.release_phy(hw);
2543
2544 out:
2545 /* Revert to MDIO fast mode, if applicable */
2546 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2547 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
2548
2549 return ret_val;
2550 }
2551
2552 /**
2553 * e1000_write_phy_reg_hv - Write HV PHY register
2554 * @hw: pointer to the HW structure
2555 * @offset: register offset to write to
2556 * @data: data to write at register offset
2557 *
2558 * Acquires semaphore, if necessary, then writes the data to PHY register
2559 * at the offset. Release any acquired semaphores before exiting.
2560 **/
2561 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2562 {
2563 s32 ret_val;
2564 u16 page = BM_PHY_REG_PAGE(offset);
2565 u16 reg = BM_PHY_REG_NUM(offset);
2566 bool in_slow_mode = false;
2567
2568 /* Workaround failure in MDIO access while cable is disconnected */
2569 if ((hw->phy.type == e1000_phy_82577) &&
2570 !(er32(STATUS) & E1000_STATUS_LU)) {
2571 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
2572 if (ret_val)
2573 goto out;
2574
2575 in_slow_mode = true;
2576 }
2577
2578 /* Page 800 works differently than the rest so it has its own func */
2579 if (page == BM_WUC_PAGE) {
2580 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2581 &data, false);
2582 goto out;
2583 }
2584
2585 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2586 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2587 &data, false);
2588 goto out;
2589 }
2590
2591 ret_val = hw->phy.ops.acquire_phy(hw);
2592 if (ret_val)
2593 goto out;
2594
2595 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2596
2597 if (page == HV_INTC_FC_PAGE_START)
2598 page = 0;
2599
2600 /*
2601 * Workaround MDIO accesses being disabled after entering IEEE Power
2602 * Down (whenever bit 11 of the PHY Control register is set)
2603 */
2604 if ((hw->phy.type == e1000_phy_82578) &&
2605 (hw->phy.revision >= 1) &&
2606 (hw->phy.addr == 2) &&
2607 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
2608 (data & (1 << 11))) {
2609 u16 data2 = 0x7EFF;
2610 hw->phy.ops.release_phy(hw);
2611 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
2612 &data2, false);
2613 if (ret_val)
2614 goto out;
2615
2616 ret_val = hw->phy.ops.acquire_phy(hw);
2617 if (ret_val)
2618 goto out;
2619 }
2620
2621 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2622 if ((hw->phy.type != e1000_phy_82578) ||
2623 ((reg != I82578_ADDR_REG) &&
2624 (reg != I82578_ADDR_REG + 1))) {
2625 u32 phy_addr = hw->phy.addr;
2626
2627 hw->phy.addr = 1;
2628
2629 /* Page is shifted left, PHY expects (page x 32) */
2630 ret_val = e1000e_write_phy_reg_mdic(hw,
2631 IGP01E1000_PHY_PAGE_SELECT,
2632 (page << IGP_PAGE_SHIFT));
2633 if (ret_val) {
2634 hw->phy.ops.release_phy(hw);
2635 goto out;
2636 }
2637 hw->phy.addr = phy_addr;
2638 }
2639 }
2640
2641 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2642 data);
2643 hw->phy.ops.release_phy(hw);
2644
2645 out:
2646 /* Revert to MDIO fast mode, if applicable */
2647 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2648 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
2649
2650 return ret_val;
2651 }
2652
2653 /**
2654 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
2655 * @page: page to be accessed
2656 **/
2657 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2658 {
2659 u32 phy_addr = 2;
2660
2661 if (page >= HV_INTC_FC_PAGE_START)
2662 phy_addr = 1;
2663
2664 return phy_addr;
2665 }
2666
2667 /**
2668 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2669 * @hw: pointer to the HW structure
2670 * @offset: register offset to be read or written
2671 * @data: pointer to the data to be read or written
2672 * @read: determines if operation is read or written
2673 *
2674 * Acquires semaphore, if necessary, then reads the PHY register at offset
2675 * and storing the retreived information in data. Release any acquired
2676 * semaphores before exiting. Note that the procedure to read these regs
2677 * uses the address port and data port to read/write.
2678 **/
2679 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2680 u16 *data, bool read)
2681 {
2682 s32 ret_val;
2683 u32 addr_reg = 0;
2684 u32 data_reg = 0;
2685 u8 phy_acquired = 1;
2686
2687 /* This takes care of the difference with desktop vs mobile phy */
2688 addr_reg = (hw->phy.type == e1000_phy_82578) ?
2689 I82578_ADDR_REG : I82577_ADDR_REG;
2690 data_reg = addr_reg + 1;
2691
2692 ret_val = hw->phy.ops.acquire_phy(hw);
2693 if (ret_val) {
2694 hw_dbg(hw, "Could not acquire PHY\n");
2695 phy_acquired = 0;
2696 goto out;
2697 }
2698
2699 /* All operations in this function are phy address 2 */
2700 hw->phy.addr = 2;
2701
2702 /* masking with 0x3F to remove the page from offset */
2703 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
2704 if (ret_val) {
2705 hw_dbg(hw, "Could not write PHY the HV address register\n");
2706 goto out;
2707 }
2708
2709 /* Read or write the data value next */
2710 if (read)
2711 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
2712 else
2713 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
2714
2715 if (ret_val) {
2716 hw_dbg(hw, "Could not read data value from HV data register\n");
2717 goto out;
2718 }
2719
2720 out:
2721 if (phy_acquired == 1)
2722 hw->phy.ops.release_phy(hw);
2723 return ret_val;
2724 }
2725
2726 /**
2727 * e1000_link_stall_workaround_hv - Si workaround
2728 * @hw: pointer to the HW structure
2729 *
2730 * This function works around a Si bug where the link partner can get
2731 * a link up indication before the PHY does. If small packets are sent
2732 * by the link partner they can be placed in the packet buffer without
2733 * being properly accounted for by the PHY and will stall preventing
2734 * further packets from being received. The workaround is to clear the
2735 * packet buffer after the PHY detects link up.
2736 **/
2737 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
2738 {
2739 s32 ret_val = 0;
2740 u16 data;
2741
2742 if (hw->phy.type != e1000_phy_82578)
2743 goto out;
2744
2745 /* Do not apply workaround if in PHY loopback bit 14 set */
2746 hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &data);
2747 if (data & PHY_CONTROL_LB)
2748 goto out;
2749
2750 /* check if link is up and at 1Gbps */
2751 ret_val = hw->phy.ops.read_phy_reg(hw, BM_CS_STATUS, &data);
2752 if (ret_val)
2753 goto out;
2754
2755 data &= BM_CS_STATUS_LINK_UP |
2756 BM_CS_STATUS_RESOLVED |
2757 BM_CS_STATUS_SPEED_MASK;
2758
2759 if (data != (BM_CS_STATUS_LINK_UP |
2760 BM_CS_STATUS_RESOLVED |
2761 BM_CS_STATUS_SPEED_1000))
2762 goto out;
2763
2764 mdelay(200);
2765
2766 /* flush the packets in the fifo buffer */
2767 ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL,
2768 HV_MUX_DATA_CTRL_GEN_TO_MAC |
2769 HV_MUX_DATA_CTRL_FORCE_SPEED);
2770 if (ret_val)
2771 goto out;
2772
2773 ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL,
2774 HV_MUX_DATA_CTRL_GEN_TO_MAC);
2775
2776 out:
2777 return ret_val;
2778 }
2779
2780 /**
2781 * e1000_check_polarity_82577 - Checks the polarity.
2782 * @hw: pointer to the HW structure
2783 *
2784 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2785 *
2786 * Polarity is determined based on the PHY specific status register.
2787 **/
2788 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
2789 {
2790 struct e1000_phy_info *phy = &hw->phy;
2791 s32 ret_val;
2792 u16 data;
2793
2794 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data);
2795
2796 if (!ret_val)
2797 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
2798 ? e1000_rev_polarity_reversed
2799 : e1000_rev_polarity_normal;
2800
2801 return ret_val;
2802 }
2803
2804 /**
2805 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
2806 * @hw: pointer to the HW structure
2807 *
2808 * Calls the PHY setup function to force speed and duplex. Clears the
2809 * auto-crossover to force MDI manually. Waits for link and returns
2810 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2811 **/
2812 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2813 {
2814 struct e1000_phy_info *phy = &hw->phy;
2815 s32 ret_val;
2816 u16 phy_data;
2817 bool link;
2818
2819 ret_val = phy->ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
2820 if (ret_val)
2821 goto out;
2822
2823 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
2824
2825 ret_val = phy->ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
2826 if (ret_val)
2827 goto out;
2828
2829 /*
2830 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
2831 * forced whenever speed and duplex are forced.
2832 */
2833 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_CTRL_2, &phy_data);
2834 if (ret_val)
2835 goto out;
2836
2837 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
2838 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
2839
2840 ret_val = phy->ops.write_phy_reg(hw, I82577_PHY_CTRL_2, phy_data);
2841 if (ret_val)
2842 goto out;
2843
2844 hw_dbg(hw, "I82577_PHY_CTRL_2: %X\n", phy_data);
2845
2846 udelay(1);
2847
2848 if (phy->autoneg_wait_to_complete) {
2849 hw_dbg(hw, "Waiting for forced speed/duplex link on 82577 phy\n");
2850
2851 ret_val = e1000e_phy_has_link_generic(hw,
2852 PHY_FORCE_LIMIT,
2853 100000,
2854 &link);
2855 if (ret_val)
2856 goto out;
2857
2858 if (!link)
2859 hw_dbg(hw, "Link taking longer than expected.\n");
2860
2861 /* Try once more */
2862 ret_val = e1000e_phy_has_link_generic(hw,
2863 PHY_FORCE_LIMIT,
2864 100000,
2865 &link);
2866 if (ret_val)
2867 goto out;
2868 }
2869
2870 out:
2871 return ret_val;
2872 }
2873
2874 /**
2875 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
2876 * @hw: pointer to the HW structure
2877 *
2878 * Read PHY status to determine if link is up. If link is up, then
2879 * set/determine 10base-T extended distance and polarity correction. Read
2880 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2881 * determine on the cable length, local and remote receiver.
2882 **/
2883 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
2884 {
2885 struct e1000_phy_info *phy = &hw->phy;
2886 s32 ret_val;
2887 u16 data;
2888 bool link;
2889
2890 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2891 if (ret_val)
2892 goto out;
2893
2894 if (!link) {
2895 hw_dbg(hw, "Phy info is only valid if link is up\n");
2896 ret_val = -E1000_ERR_CONFIG;
2897 goto out;
2898 }
2899
2900 phy->polarity_correction = true;
2901
2902 ret_val = e1000_check_polarity_82577(hw);
2903 if (ret_val)
2904 goto out;
2905
2906 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data);
2907 if (ret_val)
2908 goto out;
2909
2910 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
2911
2912 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
2913 I82577_PHY_STATUS2_SPEED_1000MBPS) {
2914 ret_val = hw->phy.ops.get_cable_length(hw);
2915 if (ret_val)
2916 goto out;
2917
2918 ret_val = phy->ops.read_phy_reg(hw, PHY_1000T_STATUS, &data);
2919 if (ret_val)
2920 goto out;
2921
2922 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2923 ? e1000_1000t_rx_status_ok
2924 : e1000_1000t_rx_status_not_ok;
2925
2926 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2927 ? e1000_1000t_rx_status_ok
2928 : e1000_1000t_rx_status_not_ok;
2929 } else {
2930 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2931 phy->local_rx = e1000_1000t_rx_status_undefined;
2932 phy->remote_rx = e1000_1000t_rx_status_undefined;
2933 }
2934
2935 out:
2936 return ret_val;
2937 }
2938
2939 /**
2940 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
2941 * @hw: pointer to the HW structure
2942 *
2943 * Reads the diagnostic status register and verifies result is valid before
2944 * placing it in the phy_cable_length field.
2945 **/
2946 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
2947 {
2948 struct e1000_phy_info *phy = &hw->phy;
2949 s32 ret_val;
2950 u16 phy_data, length;
2951
2952 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
2953 if (ret_val)
2954 goto out;
2955
2956 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
2957 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
2958
2959 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2960 ret_val = E1000_ERR_PHY;
2961
2962 phy->cable_length = length;
2963
2964 out:
2965 return ret_val;
2966 }
Linux with added FPC-III support