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debugfs: Modified default dir of debugfs for debugging UHCI.
[linux/fpc-iii.git] / drivers / net / ixgbe / ixgbe_ethtool.c
blob026e94a9984954d1b2815aaacca9aadf7f854584
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for ixgbe */
29
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/vmalloc.h>
36 #include <linux/uaccess.h>
37
38 #include "ixgbe.h"
39
40
41 #define IXGBE_ALL_RAR_ENTRIES 16
42
43 struct ixgbe_stats {
44 char stat_string[ETH_GSTRING_LEN];
45 int sizeof_stat;
46 int stat_offset;
47 };
48
49 #define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \
50 offsetof(struct ixgbe_adapter, m)
51 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
52 {"rx_packets", IXGBE_STAT(net_stats.rx_packets)},
53 {"tx_packets", IXGBE_STAT(net_stats.tx_packets)},
54 {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)},
55 {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)},
56 {"lsc_int", IXGBE_STAT(lsc_int)},
57 {"tx_busy", IXGBE_STAT(tx_busy)},
58 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
59 {"rx_errors", IXGBE_STAT(net_stats.rx_errors)},
60 {"tx_errors", IXGBE_STAT(net_stats.tx_errors)},
61 {"rx_dropped", IXGBE_STAT(net_stats.rx_dropped)},
62 {"tx_dropped", IXGBE_STAT(net_stats.tx_dropped)},
63 {"multicast", IXGBE_STAT(net_stats.multicast)},
64 {"broadcast", IXGBE_STAT(stats.bprc)},
65 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
66 {"collisions", IXGBE_STAT(net_stats.collisions)},
67 {"rx_over_errors", IXGBE_STAT(net_stats.rx_over_errors)},
68 {"rx_crc_errors", IXGBE_STAT(net_stats.rx_crc_errors)},
69 {"rx_frame_errors", IXGBE_STAT(net_stats.rx_frame_errors)},
70 {"hw_rsc_count", IXGBE_STAT(rsc_count)},
71 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
72 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
73 {"rx_fifo_errors", IXGBE_STAT(net_stats.rx_fifo_errors)},
74 {"rx_missed_errors", IXGBE_STAT(net_stats.rx_missed_errors)},
75 {"tx_aborted_errors", IXGBE_STAT(net_stats.tx_aborted_errors)},
76 {"tx_carrier_errors", IXGBE_STAT(net_stats.tx_carrier_errors)},
77 {"tx_fifo_errors", IXGBE_STAT(net_stats.tx_fifo_errors)},
78 {"tx_heartbeat_errors", IXGBE_STAT(net_stats.tx_heartbeat_errors)},
79 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
80 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
81 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
82 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
83 {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
84 {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
85 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
86 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
87 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
88 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
89 {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
90 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
91 {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
92 {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
93 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
94 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
95 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
96 #ifdef IXGBE_FCOE
97 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
98 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
99 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
100 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
101 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
102 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
103 #endif /* IXGBE_FCOE */
104 };
105
106 #define IXGBE_QUEUE_STATS_LEN \
107 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
108 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
109 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
110 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
111 #define IXGBE_PB_STATS_LEN ( \
112 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
113 IXGBE_FLAG_DCB_ENABLED) ? \
114 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
115 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
116 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
117 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
118 / sizeof(u64) : 0)
119 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
120 IXGBE_PB_STATS_LEN + \
121 IXGBE_QUEUE_STATS_LEN)
122
123 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
124 "Register test (offline)", "Eeprom test (offline)",
125 "Interrupt test (offline)", "Loopback test (offline)",
126 "Link test (on/offline)"
127 };
128 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
129
130 static int ixgbe_get_settings(struct net_device *netdev,
131 struct ethtool_cmd *ecmd)
132 {
133 struct ixgbe_adapter *adapter = netdev_priv(netdev);
134 struct ixgbe_hw *hw = &adapter->hw;
135 u32 link_speed = 0;
136 bool link_up;
137
138 ecmd->supported = SUPPORTED_10000baseT_Full;
139 ecmd->autoneg = AUTONEG_ENABLE;
140 ecmd->transceiver = XCVR_EXTERNAL;
141 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
142 (hw->phy.multispeed_fiber)) {
143 ecmd->supported |= (SUPPORTED_1000baseT_Full |
144 SUPPORTED_Autoneg);
145
146 ecmd->advertising = ADVERTISED_Autoneg;
147 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
148 ecmd->advertising |= ADVERTISED_10000baseT_Full;
149 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
150 ecmd->advertising |= ADVERTISED_1000baseT_Full;
151 /*
152 * It's possible that phy.autoneg_advertised may not be
153 * set yet. If so display what the default would be -
154 * both 1G and 10G supported.
155 */
156 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
157 ADVERTISED_10000baseT_Full)))
158 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
159 ADVERTISED_1000baseT_Full);
160
161 if (hw->phy.media_type == ixgbe_media_type_copper) {
162 ecmd->supported |= SUPPORTED_TP;
163 ecmd->advertising |= ADVERTISED_TP;
164 ecmd->port = PORT_TP;
165 } else {
166 ecmd->supported |= SUPPORTED_FIBRE;
167 ecmd->advertising |= ADVERTISED_FIBRE;
168 ecmd->port = PORT_FIBRE;
169 }
170 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
171 /* Set as FIBRE until SERDES defined in kernel */
172 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
173 ecmd->supported = (SUPPORTED_1000baseT_Full |
174 SUPPORTED_FIBRE);
175 ecmd->advertising = (ADVERTISED_1000baseT_Full |
176 ADVERTISED_FIBRE);
177 ecmd->port = PORT_FIBRE;
178 ecmd->autoneg = AUTONEG_DISABLE;
179 } else {
180 ecmd->supported |= (SUPPORTED_1000baseT_Full |
181 SUPPORTED_FIBRE);
182 ecmd->advertising = (ADVERTISED_10000baseT_Full |
183 ADVERTISED_1000baseT_Full |
184 ADVERTISED_FIBRE);
185 ecmd->port = PORT_FIBRE;
186 }
187 } else {
188 ecmd->supported |= SUPPORTED_FIBRE;
189 ecmd->advertising = (ADVERTISED_10000baseT_Full |
190 ADVERTISED_FIBRE);
191 ecmd->port = PORT_FIBRE;
192 ecmd->autoneg = AUTONEG_DISABLE;
193 }
194
195 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
196 if (link_up) {
197 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
198 SPEED_10000 : SPEED_1000;
199 ecmd->duplex = DUPLEX_FULL;
200 } else {
201 ecmd->speed = -1;
202 ecmd->duplex = -1;
203 }
204
205 return 0;
206 }
207
208 static int ixgbe_set_settings(struct net_device *netdev,
209 struct ethtool_cmd *ecmd)
210 {
211 struct ixgbe_adapter *adapter = netdev_priv(netdev);
212 struct ixgbe_hw *hw = &adapter->hw;
213 u32 advertised, old;
214 s32 err = 0;
215
216 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
217 (hw->phy.multispeed_fiber)) {
218 /* 10000/copper and 1000/copper must autoneg
219 * this function does not support any duplex forcing, but can
220 * limit the advertising of the adapter to only 10000 or 1000 */
221 if (ecmd->autoneg == AUTONEG_DISABLE)
222 return -EINVAL;
223
224 old = hw->phy.autoneg_advertised;
225 advertised = 0;
226 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
227 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
228
229 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
230 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
231
232 if (old == advertised)
233 return err;
234 /* this sets the link speed and restarts auto-neg */
235 hw->mac.autotry_restart = true;
236 err = hw->mac.ops.setup_link(hw, advertised, true, true);
237 if (err) {
238 DPRINTK(PROBE, INFO,
239 "setup link failed with code %d\n", err);
240 hw->mac.ops.setup_link(hw, old, true, true);
241 }
242 } else {
243 /* in this case we currently only support 10Gb/FULL */
244 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
245 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
246 (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
247 return -EINVAL;
248 }
249
250 return err;
251 }
252
253 static void ixgbe_get_pauseparam(struct net_device *netdev,
254 struct ethtool_pauseparam *pause)
255 {
256 struct ixgbe_adapter *adapter = netdev_priv(netdev);
257 struct ixgbe_hw *hw = &adapter->hw;
258
259 /*
260 * Flow Control Autoneg isn't on if
261 * - we didn't ask for it OR
262 * - it failed, we know this by tx & rx being off
263 */
264 if (hw->fc.disable_fc_autoneg ||
265 (hw->fc.current_mode == ixgbe_fc_none))
266 pause->autoneg = 0;
267 else
268 pause->autoneg = 1;
269
270 #ifdef CONFIG_DCB
271 if (hw->fc.current_mode == ixgbe_fc_pfc) {
272 pause->rx_pause = 0;
273 pause->tx_pause = 0;
274 }
275
276 #endif
277 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
278 pause->rx_pause = 1;
279 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
280 pause->tx_pause = 1;
281 } else if (hw->fc.current_mode == ixgbe_fc_full) {
282 pause->rx_pause = 1;
283 pause->tx_pause = 1;
284 }
285 }
286
287 static int ixgbe_set_pauseparam(struct net_device *netdev,
288 struct ethtool_pauseparam *pause)
289 {
290 struct ixgbe_adapter *adapter = netdev_priv(netdev);
291 struct ixgbe_hw *hw = &adapter->hw;
292 struct ixgbe_fc_info fc;
293
294 #ifdef CONFIG_DCB
295 if (adapter->dcb_cfg.pfc_mode_enable ||
296 ((hw->mac.type == ixgbe_mac_82598EB) &&
297 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
298 return -EINVAL;
299
300 #endif
301
302 fc = hw->fc;
303
304 if (pause->autoneg != AUTONEG_ENABLE)
305 fc.disable_fc_autoneg = true;
306 else
307 fc.disable_fc_autoneg = false;
308
309 if (pause->rx_pause && pause->tx_pause)
310 fc.requested_mode = ixgbe_fc_full;
311 else if (pause->rx_pause && !pause->tx_pause)
312 fc.requested_mode = ixgbe_fc_rx_pause;
313 else if (!pause->rx_pause && pause->tx_pause)
314 fc.requested_mode = ixgbe_fc_tx_pause;
315 else if (!pause->rx_pause && !pause->tx_pause)
316 fc.requested_mode = ixgbe_fc_none;
317 else
318 return -EINVAL;
319
320 #ifdef CONFIG_DCB
321 adapter->last_lfc_mode = fc.requested_mode;
322 #endif
323
324 /* if the thing changed then we'll update and use new autoneg */
325 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
326 hw->fc = fc;
327 if (netif_running(netdev))
328 ixgbe_reinit_locked(adapter);
329 else
330 ixgbe_reset(adapter);
331 }
332
333 return 0;
334 }
335
336 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
337 {
338 struct ixgbe_adapter *adapter = netdev_priv(netdev);
339 return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
340 }
341
342 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
343 {
344 struct ixgbe_adapter *adapter = netdev_priv(netdev);
345 if (data)
346 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
347 else
348 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
349
350 if (netif_running(netdev))
351 ixgbe_reinit_locked(adapter);
352 else
353 ixgbe_reset(adapter);
354
355 return 0;
356 }
357
358 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
359 {
360 return (netdev->features & NETIF_F_IP_CSUM) != 0;
361 }
362
363 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
364 {
365 struct ixgbe_adapter *adapter = netdev_priv(netdev);
366
367 if (data) {
368 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
369 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
370 netdev->features |= NETIF_F_SCTP_CSUM;
371 } else {
372 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
373 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
374 netdev->features &= ~NETIF_F_SCTP_CSUM;
375 }
376
377 return 0;
378 }
379
380 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
381 {
382 if (data) {
383 netdev->features |= NETIF_F_TSO;
384 netdev->features |= NETIF_F_TSO6;
385 } else {
386 netif_tx_stop_all_queues(netdev);
387 netdev->features &= ~NETIF_F_TSO;
388 netdev->features &= ~NETIF_F_TSO6;
389 netif_tx_start_all_queues(netdev);
390 }
391 return 0;
392 }
393
394 static u32 ixgbe_get_msglevel(struct net_device *netdev)
395 {
396 struct ixgbe_adapter *adapter = netdev_priv(netdev);
397 return adapter->msg_enable;
398 }
399
400 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
401 {
402 struct ixgbe_adapter *adapter = netdev_priv(netdev);
403 adapter->msg_enable = data;
404 }
405
406 static int ixgbe_get_regs_len(struct net_device *netdev)
407 {
408 #define IXGBE_REGS_LEN 1128
409 return IXGBE_REGS_LEN * sizeof(u32);
410 }
411
412 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
413
414 static void ixgbe_get_regs(struct net_device *netdev,
415 struct ethtool_regs *regs, void *p)
416 {
417 struct ixgbe_adapter *adapter = netdev_priv(netdev);
418 struct ixgbe_hw *hw = &adapter->hw;
419 u32 *regs_buff = p;
420 u8 i;
421
422 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
423
424 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
425
426 /* General Registers */
427 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
428 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
429 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
430 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
431 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
432 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
433 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
434 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
435
436 /* NVM Register */
437 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
438 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
439 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
440 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
441 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
442 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
443 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
444 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
445 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
446 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
447
448 /* Interrupt */
449 /* don't read EICR because it can clear interrupt causes, instead
450 * read EICS which is a shadow but doesn't clear EICR */
451 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
452 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
453 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
454 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
455 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
456 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
457 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
458 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
459 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
460 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
461 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
462 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
463
464 /* Flow Control */
465 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
466 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
467 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
468 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
469 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
470 for (i = 0; i < 8; i++)
471 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
472 for (i = 0; i < 8; i++)
473 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
474 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
475 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
476
477 /* Receive DMA */
478 for (i = 0; i < 64; i++)
479 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
480 for (i = 0; i < 64; i++)
481 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
482 for (i = 0; i < 64; i++)
483 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
484 for (i = 0; i < 64; i++)
485 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
486 for (i = 0; i < 64; i++)
487 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
488 for (i = 0; i < 64; i++)
489 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
490 for (i = 0; i < 16; i++)
491 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
492 for (i = 0; i < 16; i++)
493 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
494 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
495 for (i = 0; i < 8; i++)
496 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
497 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
498 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
499
500 /* Receive */
501 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
502 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
503 for (i = 0; i < 16; i++)
504 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
505 for (i = 0; i < 16; i++)
506 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
507 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
508 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
509 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
510 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
511 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
512 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
513 for (i = 0; i < 8; i++)
514 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
515 for (i = 0; i < 8; i++)
516 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
517 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
518
519 /* Transmit */
520 for (i = 0; i < 32; i++)
521 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
522 for (i = 0; i < 32; i++)
523 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
524 for (i = 0; i < 32; i++)
525 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
526 for (i = 0; i < 32; i++)
527 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
528 for (i = 0; i < 32; i++)
529 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
530 for (i = 0; i < 32; i++)
531 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
532 for (i = 0; i < 32; i++)
533 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
534 for (i = 0; i < 32; i++)
535 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
536 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
537 for (i = 0; i < 16; i++)
538 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
539 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
540 for (i = 0; i < 8; i++)
541 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
542 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
543
544 /* Wake Up */
545 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
546 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
547 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
548 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
549 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
550 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
551 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
552 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
553 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
554
555 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
556 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
557 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
558 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
559 for (i = 0; i < 8; i++)
560 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
561 for (i = 0; i < 8; i++)
562 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
563 for (i = 0; i < 8; i++)
564 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
565 for (i = 0; i < 8; i++)
566 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
567 for (i = 0; i < 8; i++)
568 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
569 for (i = 0; i < 8; i++)
570 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
571
572 /* Statistics */
573 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
574 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
575 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
576 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
577 for (i = 0; i < 8; i++)
578 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
579 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
580 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
581 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
582 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
583 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
584 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
585 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
586 for (i = 0; i < 8; i++)
587 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
588 for (i = 0; i < 8; i++)
589 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
590 for (i = 0; i < 8; i++)
591 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
592 for (i = 0; i < 8; i++)
593 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
594 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
595 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
596 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
597 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
598 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
599 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
600 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
601 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
602 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
603 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
604 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
605 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
606 for (i = 0; i < 8; i++)
607 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
608 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
609 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
610 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
611 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
612 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
613 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
614 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
615 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
616 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
617 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
618 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
619 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
620 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
621 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
622 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
623 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
624 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
625 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
626 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
627 for (i = 0; i < 16; i++)
628 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
629 for (i = 0; i < 16; i++)
630 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
631 for (i = 0; i < 16; i++)
632 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
633 for (i = 0; i < 16; i++)
634 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
635
636 /* MAC */
637 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
638 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
639 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
640 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
641 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
642 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
643 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
644 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
645 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
646 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
647 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
648 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
649 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
650 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
651 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
652 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
653 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
654 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
655 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
656 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
657 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
658 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
659 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
660 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
661 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
662 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
663 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
664 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
665 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
666 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
667 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
668 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
669 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
670
671 /* Diagnostic */
672 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
673 for (i = 0; i < 8; i++)
674 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
675 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
676 for (i = 0; i < 4; i++)
677 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
678 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
679 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
680 for (i = 0; i < 8; i++)
681 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
682 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
683 for (i = 0; i < 4; i++)
684 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
685 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
686 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
687 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
688 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
689 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
690 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
691 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
692 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
693 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
694 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
695 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
696 for (i = 0; i < 8; i++)
697 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
698 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
699 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
700 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
701 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
702 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
703 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
704 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
705 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
706 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
707 }
708
709 static int ixgbe_get_eeprom_len(struct net_device *netdev)
710 {
711 struct ixgbe_adapter *adapter = netdev_priv(netdev);
712 return adapter->hw.eeprom.word_size * 2;
713 }
714
715 static int ixgbe_get_eeprom(struct net_device *netdev,
716 struct ethtool_eeprom *eeprom, u8 *bytes)
717 {
718 struct ixgbe_adapter *adapter = netdev_priv(netdev);
719 struct ixgbe_hw *hw = &adapter->hw;
720 u16 *eeprom_buff;
721 int first_word, last_word, eeprom_len;
722 int ret_val = 0;
723 u16 i;
724
725 if (eeprom->len == 0)
726 return -EINVAL;
727
728 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
729
730 first_word = eeprom->offset >> 1;
731 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
732 eeprom_len = last_word - first_word + 1;
733
734 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
735 if (!eeprom_buff)
736 return -ENOMEM;
737
738 for (i = 0; i < eeprom_len; i++) {
739 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
740 &eeprom_buff[i])))
741 break;
742 }
743
744 /* Device's eeprom is always little-endian, word addressable */
745 for (i = 0; i < eeprom_len; i++)
746 le16_to_cpus(&eeprom_buff[i]);
747
748 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
749 kfree(eeprom_buff);
750
751 return ret_val;
752 }
753
754 static void ixgbe_get_drvinfo(struct net_device *netdev,
755 struct ethtool_drvinfo *drvinfo)
756 {
757 struct ixgbe_adapter *adapter = netdev_priv(netdev);
758 char firmware_version[32];
759
760 strncpy(drvinfo->driver, ixgbe_driver_name, 32);
761 strncpy(drvinfo->version, ixgbe_driver_version, 32);
762
763 sprintf(firmware_version, "%d.%d-%d",
764 (adapter->eeprom_version & 0xF000) >> 12,
765 (adapter->eeprom_version & 0x0FF0) >> 4,
766 adapter->eeprom_version & 0x000F);
767
768 strncpy(drvinfo->fw_version, firmware_version, 32);
769 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
770 drvinfo->n_stats = IXGBE_STATS_LEN;
771 drvinfo->testinfo_len = IXGBE_TEST_LEN;
772 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
773 }
774
775 static void ixgbe_get_ringparam(struct net_device *netdev,
776 struct ethtool_ringparam *ring)
777 {
778 struct ixgbe_adapter *adapter = netdev_priv(netdev);
779 struct ixgbe_ring *tx_ring = adapter->tx_ring;
780 struct ixgbe_ring *rx_ring = adapter->rx_ring;
781
782 ring->rx_max_pending = IXGBE_MAX_RXD;
783 ring->tx_max_pending = IXGBE_MAX_TXD;
784 ring->rx_mini_max_pending = 0;
785 ring->rx_jumbo_max_pending = 0;
786 ring->rx_pending = rx_ring->count;
787 ring->tx_pending = tx_ring->count;
788 ring->rx_mini_pending = 0;
789 ring->rx_jumbo_pending = 0;
790 }
791
792 static int ixgbe_set_ringparam(struct net_device *netdev,
793 struct ethtool_ringparam *ring)
794 {
795 struct ixgbe_adapter *adapter = netdev_priv(netdev);
796 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
797 int i, err;
798 u32 new_rx_count, new_tx_count;
799 bool need_update = false;
800
801 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
802 return -EINVAL;
803
804 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
805 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
806 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
807
808 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
809 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
810 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
811
812 if ((new_tx_count == adapter->tx_ring->count) &&
813 (new_rx_count == adapter->rx_ring->count)) {
814 /* nothing to do */
815 return 0;
816 }
817
818 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
819 msleep(1);
820
821 temp_tx_ring = kcalloc(adapter->num_tx_queues,
822 sizeof(struct ixgbe_ring), GFP_KERNEL);
823 if (!temp_tx_ring) {
824 err = -ENOMEM;
825 goto err_setup;
826 }
827
828 if (new_tx_count != adapter->tx_ring_count) {
829 memcpy(temp_tx_ring, adapter->tx_ring,
830 adapter->num_tx_queues * sizeof(struct ixgbe_ring));
831 for (i = 0; i < adapter->num_tx_queues; i++) {
832 temp_tx_ring[i].count = new_tx_count;
833 err = ixgbe_setup_tx_resources(adapter,
834 &temp_tx_ring[i]);
835 if (err) {
836 while (i) {
837 i--;
838 ixgbe_free_tx_resources(adapter,
839 &temp_tx_ring[i]);
840 }
841 goto err_setup;
842 }
843 }
844 need_update = true;
845 }
846
847 temp_rx_ring = kcalloc(adapter->num_rx_queues,
848 sizeof(struct ixgbe_ring), GFP_KERNEL);
849 if ((!temp_rx_ring) && (need_update)) {
850 for (i = 0; i < adapter->num_tx_queues; i++)
851 ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
852 kfree(temp_tx_ring);
853 err = -ENOMEM;
854 goto err_setup;
855 }
856
857 if (new_rx_count != adapter->rx_ring_count) {
858 memcpy(temp_rx_ring, adapter->rx_ring,
859 adapter->num_rx_queues * sizeof(struct ixgbe_ring));
860 for (i = 0; i < adapter->num_rx_queues; i++) {
861 temp_rx_ring[i].count = new_rx_count;
862 err = ixgbe_setup_rx_resources(adapter,
863 &temp_rx_ring[i]);
864 if (err) {
865 while (i) {
866 i--;
867 ixgbe_free_rx_resources(adapter,
868 &temp_rx_ring[i]);
869 }
870 goto err_setup;
871 }
872 }
873 need_update = true;
874 }
875
876 /* if rings need to be updated, here's the place to do it in one shot */
877 if (need_update) {
878 if (netif_running(netdev))
879 ixgbe_down(adapter);
880
881 /* tx */
882 if (new_tx_count != adapter->tx_ring_count) {
883 kfree(adapter->tx_ring);
884 adapter->tx_ring = temp_tx_ring;
885 temp_tx_ring = NULL;
886 adapter->tx_ring_count = new_tx_count;
887 }
888
889 /* rx */
890 if (new_rx_count != adapter->rx_ring_count) {
891 kfree(adapter->rx_ring);
892 adapter->rx_ring = temp_rx_ring;
893 temp_rx_ring = NULL;
894 adapter->rx_ring_count = new_rx_count;
895 }
896 }
897
898 /* success! */
899 err = 0;
900 if (netif_running(netdev))
901 ixgbe_up(adapter);
902
903 err_setup:
904 clear_bit(__IXGBE_RESETTING, &adapter->state);
905 return err;
906 }
907
908 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
909 {
910 switch (sset) {
911 case ETH_SS_TEST:
912 return IXGBE_TEST_LEN;
913 case ETH_SS_STATS:
914 return IXGBE_STATS_LEN;
915 default:
916 return -EOPNOTSUPP;
917 }
918 }
919
920 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
921 struct ethtool_stats *stats, u64 *data)
922 {
923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
924 u64 *queue_stat;
925 int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
926 int j, k;
927 int i;
928
929 ixgbe_update_stats(adapter);
930 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
931 char *p = (char *)adapter + ixgbe_gstrings_stats[i].stat_offset;
932 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
933 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
934 }
935 for (j = 0; j < adapter->num_tx_queues; j++) {
936 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
937 for (k = 0; k < stat_count; k++)
938 data[i + k] = queue_stat[k];
939 i += k;
940 }
941 for (j = 0; j < adapter->num_rx_queues; j++) {
942 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
943 for (k = 0; k < stat_count; k++)
944 data[i + k] = queue_stat[k];
945 i += k;
946 }
947 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
948 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
949 data[i++] = adapter->stats.pxontxc[j];
950 data[i++] = adapter->stats.pxofftxc[j];
951 }
952 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
953 data[i++] = adapter->stats.pxonrxc[j];
954 data[i++] = adapter->stats.pxoffrxc[j];
955 }
956 }
957 }
958
959 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
960 u8 *data)
961 {
962 struct ixgbe_adapter *adapter = netdev_priv(netdev);
963 char *p = (char *)data;
964 int i;
965
966 switch (stringset) {
967 case ETH_SS_TEST:
968 memcpy(data, *ixgbe_gstrings_test,
969 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
970 break;
971 case ETH_SS_STATS:
972 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
973 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
974 ETH_GSTRING_LEN);
975 p += ETH_GSTRING_LEN;
976 }
977 for (i = 0; i < adapter->num_tx_queues; i++) {
978 sprintf(p, "tx_queue_%u_packets", i);
979 p += ETH_GSTRING_LEN;
980 sprintf(p, "tx_queue_%u_bytes", i);
981 p += ETH_GSTRING_LEN;
982 }
983 for (i = 0; i < adapter->num_rx_queues; i++) {
984 sprintf(p, "rx_queue_%u_packets", i);
985 p += ETH_GSTRING_LEN;
986 sprintf(p, "rx_queue_%u_bytes", i);
987 p += ETH_GSTRING_LEN;
988 }
989 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
990 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
991 sprintf(p, "tx_pb_%u_pxon", i);
992 p += ETH_GSTRING_LEN;
993 sprintf(p, "tx_pb_%u_pxoff", i);
994 p += ETH_GSTRING_LEN;
995 }
996 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
997 sprintf(p, "rx_pb_%u_pxon", i);
998 p += ETH_GSTRING_LEN;
999 sprintf(p, "rx_pb_%u_pxoff", i);
1000 p += ETH_GSTRING_LEN;
1001 }
1002 }
1003 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1004 break;
1005 }
1006 }
1007
1008 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1009 {
1010 struct ixgbe_hw *hw = &adapter->hw;
1011 bool link_up;
1012 u32 link_speed = 0;
1013 *data = 0;
1014
1015 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1016 if (link_up)
1017 return *data;
1018 else
1019 *data = 1;
1020 return *data;
1021 }
1022
1023 /* ethtool register test data */
1024 struct ixgbe_reg_test {
1025 u16 reg;
1026 u8 array_len;
1027 u8 test_type;
1028 u32 mask;
1029 u32 write;
1030 };
1031
1032 /* In the hardware, registers are laid out either singly, in arrays
1033 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1034 * most tests take place on arrays or single registers (handled
1035 * as a single-element array) and special-case the tables.
1036 * Table tests are always pattern tests.
1037 *
1038 * We also make provision for some required setup steps by specifying
1039 * registers to be written without any read-back testing.
1040 */
1041
1042 #define PATTERN_TEST 1
1043 #define SET_READ_TEST 2
1044 #define WRITE_NO_TEST 3
1045 #define TABLE32_TEST 4
1046 #define TABLE64_TEST_LO 5
1047 #define TABLE64_TEST_HI 6
1048
1049 /* default 82599 register test */
1050 static struct ixgbe_reg_test reg_test_82599[] = {
1051 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1052 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1053 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1054 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1055 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1056 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1057 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1058 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1059 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1060 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1061 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1062 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1063 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1064 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1065 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1066 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1067 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1068 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1069 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1070 { 0, 0, 0, 0 }
1071 };
1072
1073 /* default 82598 register test */
1074 static struct ixgbe_reg_test reg_test_82598[] = {
1075 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1076 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1077 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1078 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1079 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1080 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1081 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1082 /* Enable all four RX queues before testing. */
1083 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1084 /* RDH is read-only for 82598, only test RDT. */
1085 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1086 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1087 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1088 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1089 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1090 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1091 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1092 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1093 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1094 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1095 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1096 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1097 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1098 { 0, 0, 0, 0 }
1099 };
1100
1101 #define REG_PATTERN_TEST(R, M, W) \
1102 { \
1103 u32 pat, val, before; \
1104 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1105 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
1106 before = readl(adapter->hw.hw_addr + R); \
1107 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
1108 val = readl(adapter->hw.hw_addr + R); \
1109 if (val != (_test[pat] & W & M)) { \
1110 DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1111 "0x%08X expected 0x%08X\n", \
1112 R, val, (_test[pat] & W & M)); \
1113 *data = R; \
1114 writel(before, adapter->hw.hw_addr + R); \
1115 return 1; \
1116 } \
1117 writel(before, adapter->hw.hw_addr + R); \
1118 } \
1119 }
1120
1121 #define REG_SET_AND_CHECK(R, M, W) \
1122 { \
1123 u32 val, before; \
1124 before = readl(adapter->hw.hw_addr + R); \
1125 writel((W & M), (adapter->hw.hw_addr + R)); \
1126 val = readl(adapter->hw.hw_addr + R); \
1127 if ((W & M) != (val & M)) { \
1128 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1129 "expected 0x%08X\n", R, (val & M), (W & M)); \
1130 *data = R; \
1131 writel(before, (adapter->hw.hw_addr + R)); \
1132 return 1; \
1133 } \
1134 writel(before, (adapter->hw.hw_addr + R)); \
1135 }
1136
1137 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1138 {
1139 struct ixgbe_reg_test *test;
1140 u32 value, before, after;
1141 u32 i, toggle;
1142
1143 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1144 toggle = 0x7FFFF30F;
1145 test = reg_test_82599;
1146 } else {
1147 toggle = 0x7FFFF3FF;
1148 test = reg_test_82598;
1149 }
1150
1151 /*
1152 * Because the status register is such a special case,
1153 * we handle it separately from the rest of the register
1154 * tests. Some bits are read-only, some toggle, and some
1155 * are writeable on newer MACs.
1156 */
1157 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1158 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1159 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1160 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1161 if (value != after) {
1162 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1163 "0x%08X expected: 0x%08X\n", after, value);
1164 *data = 1;
1165 return 1;
1166 }
1167 /* restore previous status */
1168 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1169
1170 /*
1171 * Perform the remainder of the register test, looping through
1172 * the test table until we either fail or reach the null entry.
1173 */
1174 while (test->reg) {
1175 for (i = 0; i < test->array_len; i++) {
1176 switch (test->test_type) {
1177 case PATTERN_TEST:
1178 REG_PATTERN_TEST(test->reg + (i * 0x40),
1179 test->mask,
1180 test->write);
1181 break;
1182 case SET_READ_TEST:
1183 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1184 test->mask,
1185 test->write);
1186 break;
1187 case WRITE_NO_TEST:
1188 writel(test->write,
1189 (adapter->hw.hw_addr + test->reg)
1190 + (i * 0x40));
1191 break;
1192 case TABLE32_TEST:
1193 REG_PATTERN_TEST(test->reg + (i * 4),
1194 test->mask,
1195 test->write);
1196 break;
1197 case TABLE64_TEST_LO:
1198 REG_PATTERN_TEST(test->reg + (i * 8),
1199 test->mask,
1200 test->write);
1201 break;
1202 case TABLE64_TEST_HI:
1203 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1204 test->mask,
1205 test->write);
1206 break;
1207 }
1208 }
1209 test++;
1210 }
1211
1212 *data = 0;
1213 return 0;
1214 }
1215
1216 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1217 {
1218 struct ixgbe_hw *hw = &adapter->hw;
1219 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1220 *data = 1;
1221 else
1222 *data = 0;
1223 return *data;
1224 }
1225
1226 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1227 {
1228 struct net_device *netdev = (struct net_device *) data;
1229 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1230
1231 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1232
1233 return IRQ_HANDLED;
1234 }
1235
1236 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1237 {
1238 struct net_device *netdev = adapter->netdev;
1239 u32 mask, i = 0, shared_int = true;
1240 u32 irq = adapter->pdev->irq;
1241
1242 *data = 0;
1243
1244 /* Hook up test interrupt handler just for this test */
1245 if (adapter->msix_entries) {
1246 /* NOTE: we don't test MSI-X interrupts here, yet */
1247 return 0;
1248 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1249 shared_int = false;
1250 if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,
1251 netdev)) {
1252 *data = 1;
1253 return -1;
1254 }
1255 } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,
1256 netdev->name, netdev)) {
1257 shared_int = false;
1258 } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,
1259 netdev->name, netdev)) {
1260 *data = 1;
1261 return -1;
1262 }
1263 DPRINTK(HW, INFO, "testing %s interrupt\n",
1264 (shared_int ? "shared" : "unshared"));
1265
1266 /* Disable all the interrupts */
1267 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1268 msleep(10);
1269
1270 /* Test each interrupt */
1271 for (; i < 10; i++) {
1272 /* Interrupt to test */
1273 mask = 1 << i;
1274
1275 if (!shared_int) {
1276 /*
1277 * Disable the interrupts to be reported in
1278 * the cause register and then force the same
1279 * interrupt and see if one gets posted. If
1280 * an interrupt was posted to the bus, the
1281 * test failed.
1282 */
1283 adapter->test_icr = 0;
1284 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1285 ~mask & 0x00007FFF);
1286 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1287 ~mask & 0x00007FFF);
1288 msleep(10);
1289
1290 if (adapter->test_icr & mask) {
1291 *data = 3;
1292 break;
1293 }
1294 }
1295
1296 /*
1297 * Enable the interrupt to be reported in the cause
1298 * register and then force the same interrupt and see
1299 * if one gets posted. If an interrupt was not posted
1300 * to the bus, the test failed.
1301 */
1302 adapter->test_icr = 0;
1303 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1304 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1305 msleep(10);
1306
1307 if (!(adapter->test_icr &mask)) {
1308 *data = 4;
1309 break;
1310 }
1311
1312 if (!shared_int) {
1313 /*
1314 * Disable the other interrupts to be reported in
1315 * the cause register and then force the other
1316 * interrupts and see if any get posted. If
1317 * an interrupt was posted to the bus, the
1318 * test failed.
1319 */
1320 adapter->test_icr = 0;
1321 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1322 ~mask & 0x00007FFF);
1323 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1324 ~mask & 0x00007FFF);
1325 msleep(10);
1326
1327 if (adapter->test_icr) {
1328 *data = 5;
1329 break;
1330 }
1331 }
1332 }
1333
1334 /* Disable all the interrupts */
1335 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1336 msleep(10);
1337
1338 /* Unhook test interrupt handler */
1339 free_irq(irq, netdev);
1340
1341 return *data;
1342 }
1343
1344 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1345 {
1346 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1347 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1348 struct ixgbe_hw *hw = &adapter->hw;
1349 struct pci_dev *pdev = adapter->pdev;
1350 u32 reg_ctl;
1351 int i;
1352
1353 /* shut down the DMA engines now so they can be reinitialized later */
1354
1355 /* first Rx */
1356 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1357 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1358 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1359 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1360 reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1361 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1362
1363 /* now Tx */
1364 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1365 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1366 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1367 if (hw->mac.type == ixgbe_mac_82599EB) {
1368 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1369 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1370 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1371 }
1372
1373 ixgbe_reset(adapter);
1374
1375 if (tx_ring->desc && tx_ring->tx_buffer_info) {
1376 for (i = 0; i < tx_ring->count; i++) {
1377 struct ixgbe_tx_buffer *buf =
1378 &(tx_ring->tx_buffer_info[i]);
1379 if (buf->dma)
1380 pci_unmap_single(pdev, buf->dma, buf->length,
1381 PCI_DMA_TODEVICE);
1382 if (buf->skb)
1383 dev_kfree_skb(buf->skb);
1384 }
1385 }
1386
1387 if (rx_ring->desc && rx_ring->rx_buffer_info) {
1388 for (i = 0; i < rx_ring->count; i++) {
1389 struct ixgbe_rx_buffer *buf =
1390 &(rx_ring->rx_buffer_info[i]);
1391 if (buf->dma)
1392 pci_unmap_single(pdev, buf->dma,
1393 IXGBE_RXBUFFER_2048,
1394 PCI_DMA_FROMDEVICE);
1395 if (buf->skb)
1396 dev_kfree_skb(buf->skb);
1397 }
1398 }
1399
1400 if (tx_ring->desc) {
1401 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1402 tx_ring->dma);
1403 tx_ring->desc = NULL;
1404 }
1405 if (rx_ring->desc) {
1406 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1407 rx_ring->dma);
1408 rx_ring->desc = NULL;
1409 }
1410
1411 kfree(tx_ring->tx_buffer_info);
1412 tx_ring->tx_buffer_info = NULL;
1413 kfree(rx_ring->rx_buffer_info);
1414 rx_ring->rx_buffer_info = NULL;
1415
1416 return;
1417 }
1418
1419 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1420 {
1421 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1422 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1423 struct pci_dev *pdev = adapter->pdev;
1424 u32 rctl, reg_data;
1425 int i, ret_val;
1426
1427 /* Setup Tx descriptor ring and Tx buffers */
1428
1429 if (!tx_ring->count)
1430 tx_ring->count = IXGBE_DEFAULT_TXD;
1431
1432 tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1433 sizeof(struct ixgbe_tx_buffer),
1434 GFP_KERNEL);
1435 if (!(tx_ring->tx_buffer_info)) {
1436 ret_val = 1;
1437 goto err_nomem;
1438 }
1439
1440 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
1441 tx_ring->size = ALIGN(tx_ring->size, 4096);
1442 if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1443 &tx_ring->dma))) {
1444 ret_val = 2;
1445 goto err_nomem;
1446 }
1447 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1448
1449 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1450 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1452 ((u64) tx_ring->dma >> 32));
1453 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1454 tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
1455 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1456 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1457
1458 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1459 reg_data |= IXGBE_HLREG0_TXPADEN;
1460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1461
1462 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1463 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1464 reg_data |= IXGBE_DMATXCTL_TE;
1465 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1466 }
1467 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1468 reg_data |= IXGBE_TXDCTL_ENABLE;
1469 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1470
1471 for (i = 0; i < tx_ring->count; i++) {
1472 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
1473 struct sk_buff *skb;
1474 unsigned int size = 1024;
1475
1476 skb = alloc_skb(size, GFP_KERNEL);
1477 if (!skb) {
1478 ret_val = 3;
1479 goto err_nomem;
1480 }
1481 skb_put(skb, size);
1482 tx_ring->tx_buffer_info[i].skb = skb;
1483 tx_ring->tx_buffer_info[i].length = skb->len;
1484 tx_ring->tx_buffer_info[i].dma =
1485 pci_map_single(pdev, skb->data, skb->len,
1486 PCI_DMA_TODEVICE);
1487 desc->read.buffer_addr =
1488 cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1489 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1490 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1491 IXGBE_TXD_CMD_IFCS |
1492 IXGBE_TXD_CMD_RS);
1493 desc->read.olinfo_status = 0;
1494 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1495 desc->read.olinfo_status |=
1496 (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1497
1498 }
1499
1500 /* Setup Rx Descriptor ring and Rx buffers */
1501
1502 if (!rx_ring->count)
1503 rx_ring->count = IXGBE_DEFAULT_RXD;
1504
1505 rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1506 sizeof(struct ixgbe_rx_buffer),
1507 GFP_KERNEL);
1508 if (!(rx_ring->rx_buffer_info)) {
1509 ret_val = 4;
1510 goto err_nomem;
1511 }
1512
1513 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
1514 rx_ring->size = ALIGN(rx_ring->size, 4096);
1515 if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1516 &rx_ring->dma))) {
1517 ret_val = 5;
1518 goto err_nomem;
1519 }
1520 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1521
1522 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1523 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1525 ((u64)rx_ring->dma & 0xFFFFFFFF));
1526 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1527 ((u64) rx_ring->dma >> 32));
1528 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1529 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1530 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1531
1532 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1533 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1535
1536 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1537 reg_data &= ~IXGBE_HLREG0_LPBK;
1538 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1539
1540 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1541 #define IXGBE_RDRXCTL_RDMTS_MASK 0x00000003 /* Receive Descriptor Minimum
1542 Threshold Size mask */
1543 reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1545
1546 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1547 #define IXGBE_MCSTCTRL_MO_MASK 0x00000003 /* Multicast Offset mask */
1548 reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1549 reg_data |= adapter->hw.mac.mc_filter_type;
1550 IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1551
1552 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1553 reg_data |= IXGBE_RXDCTL_ENABLE;
1554 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1555 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1556 int j = adapter->rx_ring[0].reg_idx;
1557 u32 k;
1558 for (k = 0; k < 10; k++) {
1559 if (IXGBE_READ_REG(&adapter->hw,
1560 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1561 break;
1562 else
1563 msleep(1);
1564 }
1565 }
1566
1567 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1569
1570 for (i = 0; i < rx_ring->count; i++) {
1571 union ixgbe_adv_rx_desc *rx_desc =
1572 IXGBE_RX_DESC_ADV(*rx_ring, i);
1573 struct sk_buff *skb;
1574
1575 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1576 if (!skb) {
1577 ret_val = 6;
1578 goto err_nomem;
1579 }
1580 skb_reserve(skb, NET_IP_ALIGN);
1581 rx_ring->rx_buffer_info[i].skb = skb;
1582 rx_ring->rx_buffer_info[i].dma =
1583 pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1584 PCI_DMA_FROMDEVICE);
1585 rx_desc->read.pkt_addr =
1586 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1587 memset(skb->data, 0x00, skb->len);
1588 }
1589
1590 return 0;
1591
1592 err_nomem:
1593 ixgbe_free_desc_rings(adapter);
1594 return ret_val;
1595 }
1596
1597 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1598 {
1599 struct ixgbe_hw *hw = &adapter->hw;
1600 u32 reg_data;
1601
1602 /* right now we only support MAC loopback in the driver */
1603
1604 /* Setup MAC loopback */
1605 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1606 reg_data |= IXGBE_HLREG0_LPBK;
1607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1608
1609 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1610 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1611 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1613
1614 /* Disable Atlas Tx lanes; re-enabled in reset path */
1615 if (hw->mac.type == ixgbe_mac_82598EB) {
1616 u8 atlas;
1617
1618 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1619 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1620 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1621
1622 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1623 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1624 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1625
1626 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1627 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1628 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1629
1630 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1631 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1632 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1633 }
1634
1635 return 0;
1636 }
1637
1638 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1639 {
1640 u32 reg_data;
1641
1642 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1643 reg_data &= ~IXGBE_HLREG0_LPBK;
1644 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1645 }
1646
1647 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1648 unsigned int frame_size)
1649 {
1650 memset(skb->data, 0xFF, frame_size);
1651 frame_size &= ~1;
1652 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1653 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1654 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1655 }
1656
1657 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1658 unsigned int frame_size)
1659 {
1660 frame_size &= ~1;
1661 if (*(skb->data + 3) == 0xFF) {
1662 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1663 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1664 return 0;
1665 }
1666 }
1667 return 13;
1668 }
1669
1670 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1671 {
1672 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1673 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1674 struct pci_dev *pdev = adapter->pdev;
1675 int i, j, k, l, lc, good_cnt, ret_val = 0;
1676 unsigned long time;
1677
1678 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1679
1680 /*
1681 * Calculate the loop count based on the largest descriptor ring
1682 * The idea is to wrap the largest ring a number of times using 64
1683 * send/receive pairs during each loop
1684 */
1685
1686 if (rx_ring->count <= tx_ring->count)
1687 lc = ((tx_ring->count / 64) * 2) + 1;
1688 else
1689 lc = ((rx_ring->count / 64) * 2) + 1;
1690
1691 k = l = 0;
1692 for (j = 0; j <= lc; j++) {
1693 for (i = 0; i < 64; i++) {
1694 ixgbe_create_lbtest_frame(
1695 tx_ring->tx_buffer_info[k].skb,
1696 1024);
1697 pci_dma_sync_single_for_device(pdev,
1698 tx_ring->tx_buffer_info[k].dma,
1699 tx_ring->tx_buffer_info[k].length,
1700 PCI_DMA_TODEVICE);
1701 if (unlikely(++k == tx_ring->count))
1702 k = 0;
1703 }
1704 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1705 msleep(200);
1706 /* set the start time for the receive */
1707 time = jiffies;
1708 good_cnt = 0;
1709 do {
1710 /* receive the sent packets */
1711 pci_dma_sync_single_for_cpu(pdev,
1712 rx_ring->rx_buffer_info[l].dma,
1713 IXGBE_RXBUFFER_2048,
1714 PCI_DMA_FROMDEVICE);
1715 ret_val = ixgbe_check_lbtest_frame(
1716 rx_ring->rx_buffer_info[l].skb, 1024);
1717 if (!ret_val)
1718 good_cnt++;
1719 if (++l == rx_ring->count)
1720 l = 0;
1721 /*
1722 * time + 20 msecs (200 msecs on 2.4) is more than
1723 * enough time to complete the receives, if it's
1724 * exceeded, break and error off
1725 */
1726 } while (good_cnt < 64 && jiffies < (time + 20));
1727 if (good_cnt != 64) {
1728 /* ret_val is the same as mis-compare */
1729 ret_val = 13;
1730 break;
1731 }
1732 if (jiffies >= (time + 20)) {
1733 /* Error code for time out error */
1734 ret_val = 14;
1735 break;
1736 }
1737 }
1738
1739 return ret_val;
1740 }
1741
1742 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1743 {
1744 *data = ixgbe_setup_desc_rings(adapter);
1745 if (*data)
1746 goto out;
1747 *data = ixgbe_setup_loopback_test(adapter);
1748 if (*data)
1749 goto err_loopback;
1750 *data = ixgbe_run_loopback_test(adapter);
1751 ixgbe_loopback_cleanup(adapter);
1752
1753 err_loopback:
1754 ixgbe_free_desc_rings(adapter);
1755 out:
1756 return *data;
1757 }
1758
1759 static void ixgbe_diag_test(struct net_device *netdev,
1760 struct ethtool_test *eth_test, u64 *data)
1761 {
1762 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1763 bool if_running = netif_running(netdev);
1764
1765 set_bit(__IXGBE_TESTING, &adapter->state);
1766 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1767 /* Offline tests */
1768
1769 DPRINTK(HW, INFO, "offline testing starting\n");
1770
1771 /* Link test performed before hardware reset so autoneg doesn't
1772 * interfere with test result */
1773 if (ixgbe_link_test(adapter, &data[4]))
1774 eth_test->flags |= ETH_TEST_FL_FAILED;
1775
1776 if (if_running)
1777 /* indicate we're in test mode */
1778 dev_close(netdev);
1779 else
1780 ixgbe_reset(adapter);
1781
1782 DPRINTK(HW, INFO, "register testing starting\n");
1783 if (ixgbe_reg_test(adapter, &data[0]))
1784 eth_test->flags |= ETH_TEST_FL_FAILED;
1785
1786 ixgbe_reset(adapter);
1787 DPRINTK(HW, INFO, "eeprom testing starting\n");
1788 if (ixgbe_eeprom_test(adapter, &data[1]))
1789 eth_test->flags |= ETH_TEST_FL_FAILED;
1790
1791 ixgbe_reset(adapter);
1792 DPRINTK(HW, INFO, "interrupt testing starting\n");
1793 if (ixgbe_intr_test(adapter, &data[2]))
1794 eth_test->flags |= ETH_TEST_FL_FAILED;
1795
1796 ixgbe_reset(adapter);
1797 DPRINTK(HW, INFO, "loopback testing starting\n");
1798 if (ixgbe_loopback_test(adapter, &data[3]))
1799 eth_test->flags |= ETH_TEST_FL_FAILED;
1800
1801 ixgbe_reset(adapter);
1802
1803 clear_bit(__IXGBE_TESTING, &adapter->state);
1804 if (if_running)
1805 dev_open(netdev);
1806 } else {
1807 DPRINTK(HW, INFO, "online testing starting\n");
1808 /* Online tests */
1809 if (ixgbe_link_test(adapter, &data[4]))
1810 eth_test->flags |= ETH_TEST_FL_FAILED;
1811
1812 /* Online tests aren't run; pass by default */
1813 data[0] = 0;
1814 data[1] = 0;
1815 data[2] = 0;
1816 data[3] = 0;
1817
1818 clear_bit(__IXGBE_TESTING, &adapter->state);
1819 }
1820 msleep_interruptible(4 * 1000);
1821 }
1822
1823 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1824 struct ethtool_wolinfo *wol)
1825 {
1826 struct ixgbe_hw *hw = &adapter->hw;
1827 int retval = 1;
1828
1829 switch(hw->device_id) {
1830 case IXGBE_DEV_ID_82599_KX4:
1831 retval = 0;
1832 break;
1833 default:
1834 wol->supported = 0;
1835 }
1836
1837 return retval;
1838 }
1839
1840 static void ixgbe_get_wol(struct net_device *netdev,
1841 struct ethtool_wolinfo *wol)
1842 {
1843 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1844
1845 wol->supported = WAKE_UCAST | WAKE_MCAST |
1846 WAKE_BCAST | WAKE_MAGIC;
1847 wol->wolopts = 0;
1848
1849 if (ixgbe_wol_exclusion(adapter, wol) ||
1850 !device_can_wakeup(&adapter->pdev->dev))
1851 return;
1852
1853 if (adapter->wol & IXGBE_WUFC_EX)
1854 wol->wolopts |= WAKE_UCAST;
1855 if (adapter->wol & IXGBE_WUFC_MC)
1856 wol->wolopts |= WAKE_MCAST;
1857 if (adapter->wol & IXGBE_WUFC_BC)
1858 wol->wolopts |= WAKE_BCAST;
1859 if (adapter->wol & IXGBE_WUFC_MAG)
1860 wol->wolopts |= WAKE_MAGIC;
1861
1862 return;
1863 }
1864
1865 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1866 {
1867 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1868
1869 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1870 return -EOPNOTSUPP;
1871
1872 if (ixgbe_wol_exclusion(adapter, wol))
1873 return wol->wolopts ? -EOPNOTSUPP : 0;
1874
1875 adapter->wol = 0;
1876
1877 if (wol->wolopts & WAKE_UCAST)
1878 adapter->wol |= IXGBE_WUFC_EX;
1879 if (wol->wolopts & WAKE_MCAST)
1880 adapter->wol |= IXGBE_WUFC_MC;
1881 if (wol->wolopts & WAKE_BCAST)
1882 adapter->wol |= IXGBE_WUFC_BC;
1883 if (wol->wolopts & WAKE_MAGIC)
1884 adapter->wol |= IXGBE_WUFC_MAG;
1885
1886 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1887
1888 return 0;
1889 }
1890
1891 static int ixgbe_nway_reset(struct net_device *netdev)
1892 {
1893 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1894
1895 if (netif_running(netdev))
1896 ixgbe_reinit_locked(adapter);
1897
1898 return 0;
1899 }
1900
1901 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1902 {
1903 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1904 struct ixgbe_hw *hw = &adapter->hw;
1905 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1906 u32 i;
1907
1908 if (!data || data > 300)
1909 data = 300;
1910
1911 for (i = 0; i < (data * 1000); i += 400) {
1912 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1913 msleep_interruptible(200);
1914 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
1915 msleep_interruptible(200);
1916 }
1917
1918 /* Restore LED settings */
1919 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1920
1921 return 0;
1922 }
1923
1924 static int ixgbe_get_coalesce(struct net_device *netdev,
1925 struct ethtool_coalesce *ec)
1926 {
1927 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1928
1929 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
1930
1931 /* only valid if in constant ITR mode */
1932 switch (adapter->itr_setting) {
1933 case 0:
1934 /* throttling disabled */
1935 ec->rx_coalesce_usecs = 0;
1936 break;
1937 case 1:
1938 /* dynamic ITR mode */
1939 ec->rx_coalesce_usecs = 1;
1940 break;
1941 default:
1942 /* fixed interrupt rate mode */
1943 ec->rx_coalesce_usecs = 1000000/adapter->eitr_param;
1944 break;
1945 }
1946 return 0;
1947 }
1948
1949 static int ixgbe_set_coalesce(struct net_device *netdev,
1950 struct ethtool_coalesce *ec)
1951 {
1952 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1953 struct ixgbe_q_vector *q_vector;
1954 int i;
1955
1956 if (ec->tx_max_coalesced_frames_irq)
1957 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
1958
1959 if (ec->rx_coalesce_usecs > 1) {
1960 /* check the limits */
1961 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
1962 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
1963 return -EINVAL;
1964
1965 /* store the value in ints/second */
1966 adapter->eitr_param = 1000000/ec->rx_coalesce_usecs;
1967
1968 /* static value of interrupt rate */
1969 adapter->itr_setting = adapter->eitr_param;
1970 /* clear the lower bit as its used for dynamic state */
1971 adapter->itr_setting &= ~1;
1972 } else if (ec->rx_coalesce_usecs == 1) {
1973 /* 1 means dynamic mode */
1974 adapter->eitr_param = 20000;
1975 adapter->itr_setting = 1;
1976 } else {
1977 /*
1978 * any other value means disable eitr, which is best
1979 * served by setting the interrupt rate very high
1980 */
1981 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
1982 adapter->eitr_param = IXGBE_MAX_RSC_INT_RATE;
1983 else
1984 adapter->eitr_param = IXGBE_MAX_INT_RATE;
1985 adapter->itr_setting = 0;
1986 }
1987
1988 /* MSI/MSIx Interrupt Mode */
1989 if (adapter->flags &
1990 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
1991 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1992 for (i = 0; i < num_vectors; i++) {
1993 q_vector = adapter->q_vector[i];
1994 if (q_vector->txr_count && !q_vector->rxr_count)
1995 /* tx vector gets half the rate */
1996 q_vector->eitr = (adapter->eitr_param >> 1);
1997 else
1998 /* rx only or mixed */
1999 q_vector->eitr = adapter->eitr_param;
2000 ixgbe_write_eitr(q_vector);
2001 }
2002 /* Legacy Interrupt Mode */
2003 } else {
2004 q_vector = adapter->q_vector[0];
2005 q_vector->eitr = adapter->eitr_param;
2006 ixgbe_write_eitr(q_vector);
2007 }
2008
2009 return 0;
2010 }
2011
2012 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2013 {
2014 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2015
2016 ethtool_op_set_flags(netdev, data);
2017
2018 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2019 return 0;
2020
2021 /* if state changes we need to update adapter->flags and reset */
2022 if ((!!(data & ETH_FLAG_LRO)) !=
2023 (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2024 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2025 if (netif_running(netdev))
2026 ixgbe_reinit_locked(adapter);
2027 else
2028 ixgbe_reset(adapter);
2029 }
2030 return 0;
2031
2032 }
2033
2034 static const struct ethtool_ops ixgbe_ethtool_ops = {
2035 .get_settings = ixgbe_get_settings,
2036 .set_settings = ixgbe_set_settings,
2037 .get_drvinfo = ixgbe_get_drvinfo,
2038 .get_regs_len = ixgbe_get_regs_len,
2039 .get_regs = ixgbe_get_regs,
2040 .get_wol = ixgbe_get_wol,
2041 .set_wol = ixgbe_set_wol,
2042 .nway_reset = ixgbe_nway_reset,
2043 .get_link = ethtool_op_get_link,
2044 .get_eeprom_len = ixgbe_get_eeprom_len,
2045 .get_eeprom = ixgbe_get_eeprom,
2046 .get_ringparam = ixgbe_get_ringparam,
2047 .set_ringparam = ixgbe_set_ringparam,
2048 .get_pauseparam = ixgbe_get_pauseparam,
2049 .set_pauseparam = ixgbe_set_pauseparam,
2050 .get_rx_csum = ixgbe_get_rx_csum,
2051 .set_rx_csum = ixgbe_set_rx_csum,
2052 .get_tx_csum = ixgbe_get_tx_csum,
2053 .set_tx_csum = ixgbe_set_tx_csum,
2054 .get_sg = ethtool_op_get_sg,
2055 .set_sg = ethtool_op_set_sg,
2056 .get_msglevel = ixgbe_get_msglevel,
2057 .set_msglevel = ixgbe_set_msglevel,
2058 .get_tso = ethtool_op_get_tso,
2059 .set_tso = ixgbe_set_tso,
2060 .self_test = ixgbe_diag_test,
2061 .get_strings = ixgbe_get_strings,
2062 .phys_id = ixgbe_phys_id,
2063 .get_sset_count = ixgbe_get_sset_count,
2064 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2065 .get_coalesce = ixgbe_get_coalesce,
2066 .set_coalesce = ixgbe_set_coalesce,
2067 .get_flags = ethtool_op_get_flags,
2068 .set_flags = ixgbe_set_flags,
2069 };
2070
2071 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2072 {
2073 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2074 }
Linux with added FPC-III support