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debugfs: Modified default dir of debugfs for debugging UHCI.
[linux/fpc-iii.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
blob6a13bfbc9d988aaaacc98442c4c2e02547c0e400
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39
40 #include "iwl-eeprom.h"
41 #include "iwl-dev.h"
42 #include "iwl-core.h"
43 #include "iwl-io.h"
44 #include "iwl-helpers.h"
45 #include "iwl-calib.h"
46 #include "iwl-sta.h"
47
48 static int iwl4965_send_tx_power(struct iwl_priv *priv);
49 static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
50
51 /* Highest firmware API version supported */
52 #define IWL4965_UCODE_API_MAX 2
53
54 /* Lowest firmware API version supported */
55 #define IWL4965_UCODE_API_MIN 2
56
57 #define IWL4965_FW_PRE "iwlwifi-4965-"
58 #define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode"
59 #define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api)
60
61
62 /* module parameters */
63 static struct iwl_mod_params iwl4965_mod_params = {
64 .num_of_queues = IWL49_NUM_QUEUES,
65 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
66 .amsdu_size_8K = 1,
67 .restart_fw = 1,
68 /* the rest are 0 by default */
69 };
70
71 /* check contents of special bootstrap uCode SRAM */
72 static int iwl4965_verify_bsm(struct iwl_priv *priv)
73 {
74 __le32 *image = priv->ucode_boot.v_addr;
75 u32 len = priv->ucode_boot.len;
76 u32 reg;
77 u32 val;
78
79 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
80
81 /* verify BSM SRAM contents */
82 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
83 for (reg = BSM_SRAM_LOWER_BOUND;
84 reg < BSM_SRAM_LOWER_BOUND + len;
85 reg += sizeof(u32), image++) {
86 val = iwl_read_prph(priv, reg);
87 if (val != le32_to_cpu(*image)) {
88 IWL_ERR(priv, "BSM uCode verification failed at "
89 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
90 BSM_SRAM_LOWER_BOUND,
91 reg - BSM_SRAM_LOWER_BOUND, len,
92 val, le32_to_cpu(*image));
93 return -EIO;
94 }
95 }
96
97 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
98
99 return 0;
100 }
101
102 /**
103 * iwl4965_load_bsm - Load bootstrap instructions
104 *
105 * BSM operation:
106 *
107 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
108 * in special SRAM that does not power down during RFKILL. When powering back
109 * up after power-saving sleeps (or during initial uCode load), the BSM loads
110 * the bootstrap program into the on-board processor, and starts it.
111 *
112 * The bootstrap program loads (via DMA) instructions and data for a new
113 * program from host DRAM locations indicated by the host driver in the
114 * BSM_DRAM_* registers. Once the new program is loaded, it starts
115 * automatically.
116 *
117 * When initializing the NIC, the host driver points the BSM to the
118 * "initialize" uCode image. This uCode sets up some internal data, then
119 * notifies host via "initialize alive" that it is complete.
120 *
121 * The host then replaces the BSM_DRAM_* pointer values to point to the
122 * normal runtime uCode instructions and a backup uCode data cache buffer
123 * (filled initially with starting data values for the on-board processor),
124 * then triggers the "initialize" uCode to load and launch the runtime uCode,
125 * which begins normal operation.
126 *
127 * When doing a power-save shutdown, runtime uCode saves data SRAM into
128 * the backup data cache in DRAM before SRAM is powered down.
129 *
130 * When powering back up, the BSM loads the bootstrap program. This reloads
131 * the runtime uCode instructions and the backup data cache into SRAM,
132 * and re-launches the runtime uCode from where it left off.
133 */
134 static int iwl4965_load_bsm(struct iwl_priv *priv)
135 {
136 __le32 *image = priv->ucode_boot.v_addr;
137 u32 len = priv->ucode_boot.len;
138 dma_addr_t pinst;
139 dma_addr_t pdata;
140 u32 inst_len;
141 u32 data_len;
142 int i;
143 u32 done;
144 u32 reg_offset;
145 int ret;
146
147 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
148
149 priv->ucode_type = UCODE_RT;
150
151 /* make sure bootstrap program is no larger than BSM's SRAM size */
152 if (len > IWL49_MAX_BSM_SIZE)
153 return -EINVAL;
154
155 /* Tell bootstrap uCode where to find the "Initialize" uCode
156 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
157 * NOTE: iwl_init_alive_start() will replace these values,
158 * after the "initialize" uCode has run, to point to
159 * runtime/protocol instructions and backup data cache.
160 */
161 pinst = priv->ucode_init.p_addr >> 4;
162 pdata = priv->ucode_init_data.p_addr >> 4;
163 inst_len = priv->ucode_init.len;
164 data_len = priv->ucode_init_data.len;
165
166 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
167 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
168 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
169 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
170
171 /* Fill BSM memory with bootstrap instructions */
172 for (reg_offset = BSM_SRAM_LOWER_BOUND;
173 reg_offset < BSM_SRAM_LOWER_BOUND + len;
174 reg_offset += sizeof(u32), image++)
175 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
176
177 ret = iwl4965_verify_bsm(priv);
178 if (ret)
179 return ret;
180
181 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
182 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
183 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
184 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
185
186 /* Load bootstrap code into instruction SRAM now,
187 * to prepare to load "initialize" uCode */
188 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
189
190 /* Wait for load of bootstrap uCode to finish */
191 for (i = 0; i < 100; i++) {
192 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
193 if (!(done & BSM_WR_CTRL_REG_BIT_START))
194 break;
195 udelay(10);
196 }
197 if (i < 100)
198 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
199 else {
200 IWL_ERR(priv, "BSM write did not complete!\n");
201 return -EIO;
202 }
203
204 /* Enable future boot loads whenever power management unit triggers it
205 * (e.g. when powering back up after power-save shutdown) */
206 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
207
208
209 return 0;
210 }
211
212 /**
213 * iwl4965_set_ucode_ptrs - Set uCode address location
214 *
215 * Tell initialization uCode where to find runtime uCode.
216 *
217 * BSM registers initially contain pointers to initialization uCode.
218 * We need to replace them to load runtime uCode inst and data,
219 * and to save runtime data when powering down.
220 */
221 static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
222 {
223 dma_addr_t pinst;
224 dma_addr_t pdata;
225 int ret = 0;
226
227 /* bits 35:4 for 4965 */
228 pinst = priv->ucode_code.p_addr >> 4;
229 pdata = priv->ucode_data_backup.p_addr >> 4;
230
231 /* Tell bootstrap uCode where to find image to load */
232 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
233 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
234 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
235 priv->ucode_data.len);
236
237 /* Inst byte count must be last to set up, bit 31 signals uCode
238 * that all new ptr/size info is in place */
239 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
240 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
241 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
242
243 return ret;
244 }
245
246 /**
247 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
248 *
249 * Called after REPLY_ALIVE notification received from "initialize" uCode.
250 *
251 * The 4965 "initialize" ALIVE reply contains calibration data for:
252 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
253 * (3945 does not contain this data).
254 *
255 * Tell "initialize" uCode to go ahead and load the runtime uCode.
256 */
257 static void iwl4965_init_alive_start(struct iwl_priv *priv)
258 {
259 /* Check alive response for "valid" sign from uCode */
260 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
261 /* We had an error bringing up the hardware, so take it
262 * all the way back down so we can try again */
263 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
264 goto restart;
265 }
266
267 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
268 * This is a paranoid check, because we would not have gotten the
269 * "initialize" alive if code weren't properly loaded. */
270 if (iwl_verify_ucode(priv)) {
271 /* Runtime instruction load was bad;
272 * take it all the way back down so we can try again */
273 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
274 goto restart;
275 }
276
277 /* Calculate temperature */
278 priv->temperature = iwl4965_hw_get_temperature(priv);
279
280 /* Send pointers to protocol/runtime uCode image ... init code will
281 * load and launch runtime uCode, which will send us another "Alive"
282 * notification. */
283 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
284 if (iwl4965_set_ucode_ptrs(priv)) {
285 /* Runtime instruction load won't happen;
286 * take it all the way back down so we can try again */
287 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
288 goto restart;
289 }
290 return;
291
292 restart:
293 queue_work(priv->workqueue, &priv->restart);
294 }
295
296 static bool is_ht40_channel(__le32 rxon_flags)
297 {
298 int chan_mod = le32_to_cpu(rxon_flags & RXON_FLG_CHANNEL_MODE_MSK)
299 >> RXON_FLG_CHANNEL_MODE_POS;
300 return ((chan_mod == CHANNEL_MODE_PURE_40) ||
301 (chan_mod == CHANNEL_MODE_MIXED));
302 }
303
304 /*
305 * EEPROM handlers
306 */
307 static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
308 {
309 return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
310 }
311
312 /*
313 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
314 * must be called under priv->lock and mac access
315 */
316 static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
317 {
318 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
319 }
320
321 static int iwl4965_apm_init(struct iwl_priv *priv)
322 {
323 int ret = 0;
324
325 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
326 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
327
328 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
329 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
330 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
331
332 /* set "initialization complete" bit to move adapter
333 * D0U* --> D0A* state */
334 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
335
336 /* wait for clock stabilization */
337 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
338 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
339 if (ret < 0) {
340 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
341 goto out;
342 }
343
344 /* enable DMA */
345 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
346 APMG_CLK_VAL_BSM_CLK_RQT);
347
348 udelay(20);
349
350 /* disable L1-Active */
351 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
352 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
353
354 out:
355 return ret;
356 }
357
358
359 static void iwl4965_nic_config(struct iwl_priv *priv)
360 {
361 unsigned long flags;
362 u16 radio_cfg;
363 u16 lctl;
364
365 spin_lock_irqsave(&priv->lock, flags);
366
367 lctl = iwl_pcie_link_ctl(priv);
368
369 /* HW bug W/A - negligible power consumption */
370 /* L1-ASPM is enabled by BIOS */
371 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
372 /* L1-ASPM enabled: disable L0S */
373 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
374 else
375 /* L1-ASPM disabled: enable L0S */
376 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
377
378 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
379
380 /* write radio config values to register */
381 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
382 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
383 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
384 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
385 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
386
387 /* set CSR_HW_CONFIG_REG for uCode use */
388 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
389 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
390 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
391
392 priv->calib_info = (struct iwl_eeprom_calib_info *)
393 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
394
395 spin_unlock_irqrestore(&priv->lock, flags);
396 }
397
398 static int iwl4965_apm_stop_master(struct iwl_priv *priv)
399 {
400 unsigned long flags;
401
402 spin_lock_irqsave(&priv->lock, flags);
403
404 /* set stop master bit */
405 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
406
407 iwl_poll_direct_bit(priv, CSR_RESET,
408 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
409
410 spin_unlock_irqrestore(&priv->lock, flags);
411 IWL_DEBUG_INFO(priv, "stop master\n");
412
413 return 0;
414 }
415
416 static void iwl4965_apm_stop(struct iwl_priv *priv)
417 {
418 unsigned long flags;
419
420 iwl4965_apm_stop_master(priv);
421
422 spin_lock_irqsave(&priv->lock, flags);
423
424 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
425
426 udelay(10);
427 /* clear "init complete" move adapter D0A* --> D0U state */
428 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
429 spin_unlock_irqrestore(&priv->lock, flags);
430 }
431
432 static int iwl4965_apm_reset(struct iwl_priv *priv)
433 {
434 int ret = 0;
435
436 iwl4965_apm_stop_master(priv);
437
438
439 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
440
441 udelay(10);
442
443 /* FIXME: put here L1A -L0S w/a */
444
445 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
446
447 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
448 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
449 if (ret < 0)
450 goto out;
451
452 udelay(10);
453
454 /* Enable DMA and BSM Clock */
455 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
456 APMG_CLK_VAL_BSM_CLK_RQT);
457
458 udelay(10);
459
460 /* disable L1A */
461 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
462 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
463
464 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
465 wake_up_interruptible(&priv->wait_command_queue);
466
467 out:
468 return ret;
469 }
470
471 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
472 * Called after every association, but this runs only once!
473 * ... once chain noise is calibrated the first time, it's good forever. */
474 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
475 {
476 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
477
478 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
479 struct iwl_calib_diff_gain_cmd cmd;
480
481 memset(&cmd, 0, sizeof(cmd));
482 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
483 cmd.diff_gain_a = 0;
484 cmd.diff_gain_b = 0;
485 cmd.diff_gain_c = 0;
486 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
487 sizeof(cmd), &cmd))
488 IWL_ERR(priv,
489 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
490 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
491 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
492 }
493 }
494
495 static void iwl4965_gain_computation(struct iwl_priv *priv,
496 u32 *average_noise,
497 u16 min_average_noise_antenna_i,
498 u32 min_average_noise)
499 {
500 int i, ret;
501 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
502
503 data->delta_gain_code[min_average_noise_antenna_i] = 0;
504
505 for (i = 0; i < NUM_RX_CHAINS; i++) {
506 s32 delta_g = 0;
507
508 if (!(data->disconn_array[i]) &&
509 (data->delta_gain_code[i] ==
510 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
511 delta_g = average_noise[i] - min_average_noise;
512 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
513 data->delta_gain_code[i] =
514 min(data->delta_gain_code[i],
515 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
516
517 data->delta_gain_code[i] =
518 (data->delta_gain_code[i] | (1 << 2));
519 } else {
520 data->delta_gain_code[i] = 0;
521 }
522 }
523 IWL_DEBUG_CALIB(priv, "delta_gain_codes: a %d b %d c %d\n",
524 data->delta_gain_code[0],
525 data->delta_gain_code[1],
526 data->delta_gain_code[2]);
527
528 /* Differential gain gets sent to uCode only once */
529 if (!data->radio_write) {
530 struct iwl_calib_diff_gain_cmd cmd;
531 data->radio_write = 1;
532
533 memset(&cmd, 0, sizeof(cmd));
534 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
535 cmd.diff_gain_a = data->delta_gain_code[0];
536 cmd.diff_gain_b = data->delta_gain_code[1];
537 cmd.diff_gain_c = data->delta_gain_code[2];
538 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
539 sizeof(cmd), &cmd);
540 if (ret)
541 IWL_DEBUG_CALIB(priv, "fail sending cmd "
542 "REPLY_PHY_CALIBRATION_CMD \n");
543
544 /* TODO we might want recalculate
545 * rx_chain in rxon cmd */
546
547 /* Mark so we run this algo only once! */
548 data->state = IWL_CHAIN_NOISE_CALIBRATED;
549 }
550 data->chain_noise_a = 0;
551 data->chain_noise_b = 0;
552 data->chain_noise_c = 0;
553 data->chain_signal_a = 0;
554 data->chain_signal_b = 0;
555 data->chain_signal_c = 0;
556 data->beacon_count = 0;
557 }
558
559 static void iwl4965_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
560 __le32 *tx_flags)
561 {
562 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
563 *tx_flags |= TX_CMD_FLG_RTS_MSK;
564 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
565 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
566 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
567 *tx_flags |= TX_CMD_FLG_CTS_MSK;
568 }
569 }
570
571 static void iwl4965_bg_txpower_work(struct work_struct *work)
572 {
573 struct iwl_priv *priv = container_of(work, struct iwl_priv,
574 txpower_work);
575
576 /* If a scan happened to start before we got here
577 * then just return; the statistics notification will
578 * kick off another scheduled work to compensate for
579 * any temperature delta we missed here. */
580 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
581 test_bit(STATUS_SCANNING, &priv->status))
582 return;
583
584 mutex_lock(&priv->mutex);
585
586 /* Regardless of if we are associated, we must reconfigure the
587 * TX power since frames can be sent on non-radar channels while
588 * not associated */
589 iwl4965_send_tx_power(priv);
590
591 /* Update last_temperature to keep is_calib_needed from running
592 * when it isn't needed... */
593 priv->last_temperature = priv->temperature;
594
595 mutex_unlock(&priv->mutex);
596 }
597
598 /*
599 * Acquire priv->lock before calling this function !
600 */
601 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
602 {
603 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
604 (index & 0xff) | (txq_id << 8));
605 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
606 }
607
608 /**
609 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
610 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
611 * @scd_retry: (1) Indicates queue will be used in aggregation mode
612 *
613 * NOTE: Acquire priv->lock before calling this function !
614 */
615 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
616 struct iwl_tx_queue *txq,
617 int tx_fifo_id, int scd_retry)
618 {
619 int txq_id = txq->q.id;
620
621 /* Find out whether to activate Tx queue */
622 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
623
624 /* Set up and activate */
625 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
626 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
627 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
628 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
629 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
630 IWL49_SCD_QUEUE_STTS_REG_MSK);
631
632 txq->sched_retry = scd_retry;
633
634 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
635 active ? "Activate" : "Deactivate",
636 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
637 }
638
639 static const u16 default_queue_to_tx_fifo[] = {
640 IWL_TX_FIFO_AC3,
641 IWL_TX_FIFO_AC2,
642 IWL_TX_FIFO_AC1,
643 IWL_TX_FIFO_AC0,
644 IWL49_CMD_FIFO_NUM,
645 IWL_TX_FIFO_HCCA_1,
646 IWL_TX_FIFO_HCCA_2
647 };
648
649 static int iwl4965_alive_notify(struct iwl_priv *priv)
650 {
651 u32 a;
652 unsigned long flags;
653 int i, chan;
654 u32 reg_val;
655
656 spin_lock_irqsave(&priv->lock, flags);
657
658 /* Clear 4965's internal Tx Scheduler data base */
659 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
660 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
661 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
662 iwl_write_targ_mem(priv, a, 0);
663 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
664 iwl_write_targ_mem(priv, a, 0);
665 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
666 iwl_write_targ_mem(priv, a, 0);
667
668 /* Tel 4965 where to find Tx byte count tables */
669 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
670 priv->scd_bc_tbls.dma >> 10);
671
672 /* Enable DMA channel */
673 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
674 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
675 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
676 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
677
678 /* Update FH chicken bits */
679 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
680 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
681 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
682
683 /* Disable chain mode for all queues */
684 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
685
686 /* Initialize each Tx queue (including the command queue) */
687 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
688
689 /* TFD circular buffer read/write indexes */
690 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
691 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
692
693 /* Max Tx Window size for Scheduler-ACK mode */
694 iwl_write_targ_mem(priv, priv->scd_base_addr +
695 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
696 (SCD_WIN_SIZE <<
697 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
698 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
699
700 /* Frame limit */
701 iwl_write_targ_mem(priv, priv->scd_base_addr +
702 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
703 sizeof(u32),
704 (SCD_FRAME_LIMIT <<
705 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
706 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
707
708 }
709 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
710 (1 << priv->hw_params.max_txq_num) - 1);
711
712 /* Activate all Tx DMA/FIFO channels */
713 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
714
715 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
716
717 /* Map each Tx/cmd queue to its corresponding fifo */
718 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
719 int ac = default_queue_to_tx_fifo[i];
720 iwl_txq_ctx_activate(priv, i);
721 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
722 }
723
724 spin_unlock_irqrestore(&priv->lock, flags);
725
726 return 0;
727 }
728
729 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
730 .min_nrg_cck = 97,
731 .max_nrg_cck = 0, /* not used, set to 0 */
732
733 .auto_corr_min_ofdm = 85,
734 .auto_corr_min_ofdm_mrc = 170,
735 .auto_corr_min_ofdm_x1 = 105,
736 .auto_corr_min_ofdm_mrc_x1 = 220,
737
738 .auto_corr_max_ofdm = 120,
739 .auto_corr_max_ofdm_mrc = 210,
740 .auto_corr_max_ofdm_x1 = 140,
741 .auto_corr_max_ofdm_mrc_x1 = 270,
742
743 .auto_corr_min_cck = 125,
744 .auto_corr_max_cck = 200,
745 .auto_corr_min_cck_mrc = 200,
746 .auto_corr_max_cck_mrc = 400,
747
748 .nrg_th_cck = 100,
749 .nrg_th_ofdm = 100,
750 };
751
752 static void iwl4965_set_ct_threshold(struct iwl_priv *priv)
753 {
754 /* want Kelvin */
755 priv->hw_params.ct_kill_threshold =
756 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
757 }
758
759 /**
760 * iwl4965_hw_set_hw_params
761 *
762 * Called when initializing driver
763 */
764 static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
765 {
766
767 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
768 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
769 IWL_ERR(priv,
770 "invalid queues_num, should be between %d and %d\n",
771 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
772 return -EINVAL;
773 }
774
775 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
776 priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
777 priv->hw_params.scd_bc_tbls_size =
778 IWL49_NUM_QUEUES * sizeof(struct iwl4965_scd_bc_tbl);
779 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
780 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
781 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
782 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
783 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
784 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
785 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
786
787 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
788
789 priv->hw_params.tx_chains_num = 2;
790 priv->hw_params.rx_chains_num = 2;
791 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
792 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
793 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
794 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
795
796 priv->hw_params.sens = &iwl4965_sensitivity;
797
798 return 0;
799 }
800
801 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
802 {
803 s32 sign = 1;
804
805 if (num < 0) {
806 sign = -sign;
807 num = -num;
808 }
809 if (denom < 0) {
810 sign = -sign;
811 denom = -denom;
812 }
813 *res = 1;
814 *res = ((num * 2 + denom) / (denom * 2)) * sign;
815
816 return 1;
817 }
818
819 /**
820 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
821 *
822 * Determines power supply voltage compensation for txpower calculations.
823 * Returns number of 1/2-dB steps to subtract from gain table index,
824 * to compensate for difference between power supply voltage during
825 * factory measurements, vs. current power supply voltage.
826 *
827 * Voltage indication is higher for lower voltage.
828 * Lower voltage requires more gain (lower gain table index).
829 */
830 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
831 s32 current_voltage)
832 {
833 s32 comp = 0;
834
835 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
836 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
837 return 0;
838
839 iwl4965_math_div_round(current_voltage - eeprom_voltage,
840 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
841
842 if (current_voltage > eeprom_voltage)
843 comp *= 2;
844 if ((comp < -2) || (comp > 2))
845 comp = 0;
846
847 return comp;
848 }
849
850 static s32 iwl4965_get_tx_atten_grp(u16 channel)
851 {
852 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
853 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
854 return CALIB_CH_GROUP_5;
855
856 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
857 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
858 return CALIB_CH_GROUP_1;
859
860 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
861 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
862 return CALIB_CH_GROUP_2;
863
864 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
865 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
866 return CALIB_CH_GROUP_3;
867
868 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
869 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
870 return CALIB_CH_GROUP_4;
871
872 return -1;
873 }
874
875 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
876 {
877 s32 b = -1;
878
879 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
880 if (priv->calib_info->band_info[b].ch_from == 0)
881 continue;
882
883 if ((channel >= priv->calib_info->band_info[b].ch_from)
884 && (channel <= priv->calib_info->band_info[b].ch_to))
885 break;
886 }
887
888 return b;
889 }
890
891 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
892 {
893 s32 val;
894
895 if (x2 == x1)
896 return y1;
897 else {
898 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
899 return val + y2;
900 }
901 }
902
903 /**
904 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
905 *
906 * Interpolates factory measurements from the two sample channels within a
907 * sub-band, to apply to channel of interest. Interpolation is proportional to
908 * differences in channel frequencies, which is proportional to differences
909 * in channel number.
910 */
911 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
912 struct iwl_eeprom_calib_ch_info *chan_info)
913 {
914 s32 s = -1;
915 u32 c;
916 u32 m;
917 const struct iwl_eeprom_calib_measure *m1;
918 const struct iwl_eeprom_calib_measure *m2;
919 struct iwl_eeprom_calib_measure *omeas;
920 u32 ch_i1;
921 u32 ch_i2;
922
923 s = iwl4965_get_sub_band(priv, channel);
924 if (s >= EEPROM_TX_POWER_BANDS) {
925 IWL_ERR(priv, "Tx Power can not find channel %d\n", channel);
926 return -1;
927 }
928
929 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
930 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
931 chan_info->ch_num = (u8) channel;
932
933 IWL_DEBUG_TXPOWER(priv, "channel %d subband %d factory cal ch %d & %d\n",
934 channel, s, ch_i1, ch_i2);
935
936 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
937 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
938 m1 = &(priv->calib_info->band_info[s].ch1.
939 measurements[c][m]);
940 m2 = &(priv->calib_info->band_info[s].ch2.
941 measurements[c][m]);
942 omeas = &(chan_info->measurements[c][m]);
943
944 omeas->actual_pow =
945 (u8) iwl4965_interpolate_value(channel, ch_i1,
946 m1->actual_pow,
947 ch_i2,
948 m2->actual_pow);
949 omeas->gain_idx =
950 (u8) iwl4965_interpolate_value(channel, ch_i1,
951 m1->gain_idx, ch_i2,
952 m2->gain_idx);
953 omeas->temperature =
954 (u8) iwl4965_interpolate_value(channel, ch_i1,
955 m1->temperature,
956 ch_i2,
957 m2->temperature);
958 omeas->pa_det =
959 (s8) iwl4965_interpolate_value(channel, ch_i1,
960 m1->pa_det, ch_i2,
961 m2->pa_det);
962
963 IWL_DEBUG_TXPOWER(priv,
964 "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
965 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
966 IWL_DEBUG_TXPOWER(priv,
967 "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
968 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
969 IWL_DEBUG_TXPOWER(priv,
970 "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
971 m1->pa_det, m2->pa_det, omeas->pa_det);
972 IWL_DEBUG_TXPOWER(priv,
973 "chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
974 m1->temperature, m2->temperature,
975 omeas->temperature);
976 }
977 }
978
979 return 0;
980 }
981
982 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
983 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
984 static s32 back_off_table[] = {
985 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
986 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
987 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
988 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
989 10 /* CCK */
990 };
991
992 /* Thermal compensation values for txpower for various frequency ranges ...
993 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
994 static struct iwl4965_txpower_comp_entry {
995 s32 degrees_per_05db_a;
996 s32 degrees_per_05db_a_denom;
997 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
998 {9, 2}, /* group 0 5.2, ch 34-43 */
999 {4, 1}, /* group 1 5.2, ch 44-70 */
1000 {4, 1}, /* group 2 5.2, ch 71-124 */
1001 {4, 1}, /* group 3 5.2, ch 125-200 */
1002 {3, 1} /* group 4 2.4, ch all */
1003 };
1004
1005 static s32 get_min_power_index(s32 rate_power_index, u32 band)
1006 {
1007 if (!band) {
1008 if ((rate_power_index & 7) <= 4)
1009 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1010 }
1011 return MIN_TX_GAIN_INDEX;
1012 }
1013
1014 struct gain_entry {
1015 u8 dsp;
1016 u8 radio;
1017 };
1018
1019 static const struct gain_entry gain_table[2][108] = {
1020 /* 5.2GHz power gain index table */
1021 {
1022 {123, 0x3F}, /* highest txpower */
1023 {117, 0x3F},
1024 {110, 0x3F},
1025 {104, 0x3F},
1026 {98, 0x3F},
1027 {110, 0x3E},
1028 {104, 0x3E},
1029 {98, 0x3E},
1030 {110, 0x3D},
1031 {104, 0x3D},
1032 {98, 0x3D},
1033 {110, 0x3C},
1034 {104, 0x3C},
1035 {98, 0x3C},
1036 {110, 0x3B},
1037 {104, 0x3B},
1038 {98, 0x3B},
1039 {110, 0x3A},
1040 {104, 0x3A},
1041 {98, 0x3A},
1042 {110, 0x39},
1043 {104, 0x39},
1044 {98, 0x39},
1045 {110, 0x38},
1046 {104, 0x38},
1047 {98, 0x38},
1048 {110, 0x37},
1049 {104, 0x37},
1050 {98, 0x37},
1051 {110, 0x36},
1052 {104, 0x36},
1053 {98, 0x36},
1054 {110, 0x35},
1055 {104, 0x35},
1056 {98, 0x35},
1057 {110, 0x34},
1058 {104, 0x34},
1059 {98, 0x34},
1060 {110, 0x33},
1061 {104, 0x33},
1062 {98, 0x33},
1063 {110, 0x32},
1064 {104, 0x32},
1065 {98, 0x32},
1066 {110, 0x31},
1067 {104, 0x31},
1068 {98, 0x31},
1069 {110, 0x30},
1070 {104, 0x30},
1071 {98, 0x30},
1072 {110, 0x25},
1073 {104, 0x25},
1074 {98, 0x25},
1075 {110, 0x24},
1076 {104, 0x24},
1077 {98, 0x24},
1078 {110, 0x23},
1079 {104, 0x23},
1080 {98, 0x23},
1081 {110, 0x22},
1082 {104, 0x18},
1083 {98, 0x18},
1084 {110, 0x17},
1085 {104, 0x17},
1086 {98, 0x17},
1087 {110, 0x16},
1088 {104, 0x16},
1089 {98, 0x16},
1090 {110, 0x15},
1091 {104, 0x15},
1092 {98, 0x15},
1093 {110, 0x14},
1094 {104, 0x14},
1095 {98, 0x14},
1096 {110, 0x13},
1097 {104, 0x13},
1098 {98, 0x13},
1099 {110, 0x12},
1100 {104, 0x08},
1101 {98, 0x08},
1102 {110, 0x07},
1103 {104, 0x07},
1104 {98, 0x07},
1105 {110, 0x06},
1106 {104, 0x06},
1107 {98, 0x06},
1108 {110, 0x05},
1109 {104, 0x05},
1110 {98, 0x05},
1111 {110, 0x04},
1112 {104, 0x04},
1113 {98, 0x04},
1114 {110, 0x03},
1115 {104, 0x03},
1116 {98, 0x03},
1117 {110, 0x02},
1118 {104, 0x02},
1119 {98, 0x02},
1120 {110, 0x01},
1121 {104, 0x01},
1122 {98, 0x01},
1123 {110, 0x00},
1124 {104, 0x00},
1125 {98, 0x00},
1126 {93, 0x00},
1127 {88, 0x00},
1128 {83, 0x00},
1129 {78, 0x00},
1130 },
1131 /* 2.4GHz power gain index table */
1132 {
1133 {110, 0x3f}, /* highest txpower */
1134 {104, 0x3f},
1135 {98, 0x3f},
1136 {110, 0x3e},
1137 {104, 0x3e},
1138 {98, 0x3e},
1139 {110, 0x3d},
1140 {104, 0x3d},
1141 {98, 0x3d},
1142 {110, 0x3c},
1143 {104, 0x3c},
1144 {98, 0x3c},
1145 {110, 0x3b},
1146 {104, 0x3b},
1147 {98, 0x3b},
1148 {110, 0x3a},
1149 {104, 0x3a},
1150 {98, 0x3a},
1151 {110, 0x39},
1152 {104, 0x39},
1153 {98, 0x39},
1154 {110, 0x38},
1155 {104, 0x38},
1156 {98, 0x38},
1157 {110, 0x37},
1158 {104, 0x37},
1159 {98, 0x37},
1160 {110, 0x36},
1161 {104, 0x36},
1162 {98, 0x36},
1163 {110, 0x35},
1164 {104, 0x35},
1165 {98, 0x35},
1166 {110, 0x34},
1167 {104, 0x34},
1168 {98, 0x34},
1169 {110, 0x33},
1170 {104, 0x33},
1171 {98, 0x33},
1172 {110, 0x32},
1173 {104, 0x32},
1174 {98, 0x32},
1175 {110, 0x31},
1176 {104, 0x31},
1177 {98, 0x31},
1178 {110, 0x30},
1179 {104, 0x30},
1180 {98, 0x30},
1181 {110, 0x6},
1182 {104, 0x6},
1183 {98, 0x6},
1184 {110, 0x5},
1185 {104, 0x5},
1186 {98, 0x5},
1187 {110, 0x4},
1188 {104, 0x4},
1189 {98, 0x4},
1190 {110, 0x3},
1191 {104, 0x3},
1192 {98, 0x3},
1193 {110, 0x2},
1194 {104, 0x2},
1195 {98, 0x2},
1196 {110, 0x1},
1197 {104, 0x1},
1198 {98, 0x1},
1199 {110, 0x0},
1200 {104, 0x0},
1201 {98, 0x0},
1202 {97, 0},
1203 {96, 0},
1204 {95, 0},
1205 {94, 0},
1206 {93, 0},
1207 {92, 0},
1208 {91, 0},
1209 {90, 0},
1210 {89, 0},
1211 {88, 0},
1212 {87, 0},
1213 {86, 0},
1214 {85, 0},
1215 {84, 0},
1216 {83, 0},
1217 {82, 0},
1218 {81, 0},
1219 {80, 0},
1220 {79, 0},
1221 {78, 0},
1222 {77, 0},
1223 {76, 0},
1224 {75, 0},
1225 {74, 0},
1226 {73, 0},
1227 {72, 0},
1228 {71, 0},
1229 {70, 0},
1230 {69, 0},
1231 {68, 0},
1232 {67, 0},
1233 {66, 0},
1234 {65, 0},
1235 {64, 0},
1236 {63, 0},
1237 {62, 0},
1238 {61, 0},
1239 {60, 0},
1240 {59, 0},
1241 }
1242 };
1243
1244 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1245 u8 is_ht40, u8 ctrl_chan_high,
1246 struct iwl4965_tx_power_db *tx_power_tbl)
1247 {
1248 u8 saturation_power;
1249 s32 target_power;
1250 s32 user_target_power;
1251 s32 power_limit;
1252 s32 current_temp;
1253 s32 reg_limit;
1254 s32 current_regulatory;
1255 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1256 int i;
1257 int c;
1258 const struct iwl_channel_info *ch_info = NULL;
1259 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1260 const struct iwl_eeprom_calib_measure *measurement;
1261 s16 voltage;
1262 s32 init_voltage;
1263 s32 voltage_compensation;
1264 s32 degrees_per_05db_num;
1265 s32 degrees_per_05db_denom;
1266 s32 factory_temp;
1267 s32 temperature_comp[2];
1268 s32 factory_gain_index[2];
1269 s32 factory_actual_pwr[2];
1270 s32 power_index;
1271
1272 /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units
1273 * are used for indexing into txpower table) */
1274 user_target_power = 2 * priv->tx_power_user_lmt;
1275
1276 /* Get current (RXON) channel, band, width */
1277 IWL_DEBUG_TXPOWER(priv, "chan %d band %d is_ht40 %d\n", channel, band,
1278 is_ht40);
1279
1280 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1281
1282 if (!is_channel_valid(ch_info))
1283 return -EINVAL;
1284
1285 /* get txatten group, used to select 1) thermal txpower adjustment
1286 * and 2) mimo txpower balance between Tx chains. */
1287 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1288 if (txatten_grp < 0) {
1289 IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
1290 channel);
1291 return -EINVAL;
1292 }
1293
1294 IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
1295 channel, txatten_grp);
1296
1297 if (is_ht40) {
1298 if (ctrl_chan_high)
1299 channel -= 2;
1300 else
1301 channel += 2;
1302 }
1303
1304 /* hardware txpower limits ...
1305 * saturation (clipping distortion) txpowers are in half-dBm */
1306 if (band)
1307 saturation_power = priv->calib_info->saturation_power24;
1308 else
1309 saturation_power = priv->calib_info->saturation_power52;
1310
1311 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1312 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1313 if (band)
1314 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1315 else
1316 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1317 }
1318
1319 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1320 * max_power_avg values are in dBm, convert * 2 */
1321 if (is_ht40)
1322 reg_limit = ch_info->ht40_max_power_avg * 2;
1323 else
1324 reg_limit = ch_info->max_power_avg * 2;
1325
1326 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1327 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1328 if (band)
1329 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1330 else
1331 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1332 }
1333
1334 /* Interpolate txpower calibration values for this channel,
1335 * based on factory calibration tests on spaced channels. */
1336 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1337
1338 /* calculate tx gain adjustment based on power supply voltage */
1339 voltage = priv->calib_info->voltage;
1340 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1341 voltage_compensation =
1342 iwl4965_get_voltage_compensation(voltage, init_voltage);
1343
1344 IWL_DEBUG_TXPOWER(priv, "curr volt %d eeprom volt %d volt comp %d\n",
1345 init_voltage,
1346 voltage, voltage_compensation);
1347
1348 /* get current temperature (Celsius) */
1349 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1350 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1351 current_temp = KELVIN_TO_CELSIUS(current_temp);
1352
1353 /* select thermal txpower adjustment params, based on channel group
1354 * (same frequency group used for mimo txatten adjustment) */
1355 degrees_per_05db_num =
1356 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1357 degrees_per_05db_denom =
1358 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1359
1360 /* get per-chain txpower values from factory measurements */
1361 for (c = 0; c < 2; c++) {
1362 measurement = &ch_eeprom_info.measurements[c][1];
1363
1364 /* txgain adjustment (in half-dB steps) based on difference
1365 * between factory and current temperature */
1366 factory_temp = measurement->temperature;
1367 iwl4965_math_div_round((current_temp - factory_temp) *
1368 degrees_per_05db_denom,
1369 degrees_per_05db_num,
1370 &temperature_comp[c]);
1371
1372 factory_gain_index[c] = measurement->gain_idx;
1373 factory_actual_pwr[c] = measurement->actual_pow;
1374
1375 IWL_DEBUG_TXPOWER(priv, "chain = %d\n", c);
1376 IWL_DEBUG_TXPOWER(priv, "fctry tmp %d, "
1377 "curr tmp %d, comp %d steps\n",
1378 factory_temp, current_temp,
1379 temperature_comp[c]);
1380
1381 IWL_DEBUG_TXPOWER(priv, "fctry idx %d, fctry pwr %d\n",
1382 factory_gain_index[c],
1383 factory_actual_pwr[c]);
1384 }
1385
1386 /* for each of 33 bit-rates (including 1 for CCK) */
1387 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1388 u8 is_mimo_rate;
1389 union iwl4965_tx_power_dual_stream tx_power;
1390
1391 /* for mimo, reduce each chain's txpower by half
1392 * (3dB, 6 steps), so total output power is regulatory
1393 * compliant. */
1394 if (i & 0x8) {
1395 current_regulatory = reg_limit -
1396 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1397 is_mimo_rate = 1;
1398 } else {
1399 current_regulatory = reg_limit;
1400 is_mimo_rate = 0;
1401 }
1402
1403 /* find txpower limit, either hardware or regulatory */
1404 power_limit = saturation_power - back_off_table[i];
1405 if (power_limit > current_regulatory)
1406 power_limit = current_regulatory;
1407
1408 /* reduce user's txpower request if necessary
1409 * for this rate on this channel */
1410 target_power = user_target_power;
1411 if (target_power > power_limit)
1412 target_power = power_limit;
1413
1414 IWL_DEBUG_TXPOWER(priv, "rate %d sat %d reg %d usr %d tgt %d\n",
1415 i, saturation_power - back_off_table[i],
1416 current_regulatory, user_target_power,
1417 target_power);
1418
1419 /* for each of 2 Tx chains (radio transmitters) */
1420 for (c = 0; c < 2; c++) {
1421 s32 atten_value;
1422
1423 if (is_mimo_rate)
1424 atten_value =
1425 (s32)le32_to_cpu(priv->card_alive_init.
1426 tx_atten[txatten_grp][c]);
1427 else
1428 atten_value = 0;
1429
1430 /* calculate index; higher index means lower txpower */
1431 power_index = (u8) (factory_gain_index[c] -
1432 (target_power -
1433 factory_actual_pwr[c]) -
1434 temperature_comp[c] -
1435 voltage_compensation +
1436 atten_value);
1437
1438 /* IWL_DEBUG_TXPOWER(priv, "calculated txpower index %d\n",
1439 power_index); */
1440
1441 if (power_index < get_min_power_index(i, band))
1442 power_index = get_min_power_index(i, band);
1443
1444 /* adjust 5 GHz index to support negative indexes */
1445 if (!band)
1446 power_index += 9;
1447
1448 /* CCK, rate 32, reduce txpower for CCK */
1449 if (i == POWER_TABLE_CCK_ENTRY)
1450 power_index +=
1451 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1452
1453 /* stay within the table! */
1454 if (power_index > 107) {
1455 IWL_WARN(priv, "txpower index %d > 107\n",
1456 power_index);
1457 power_index = 107;
1458 }
1459 if (power_index < 0) {
1460 IWL_WARN(priv, "txpower index %d < 0\n",
1461 power_index);
1462 power_index = 0;
1463 }
1464
1465 /* fill txpower command for this rate/chain */
1466 tx_power.s.radio_tx_gain[c] =
1467 gain_table[band][power_index].radio;
1468 tx_power.s.dsp_predis_atten[c] =
1469 gain_table[band][power_index].dsp;
1470
1471 IWL_DEBUG_TXPOWER(priv, "chain %d mimo %d index %d "
1472 "gain 0x%02x dsp %d\n",
1473 c, atten_value, power_index,
1474 tx_power.s.radio_tx_gain[c],
1475 tx_power.s.dsp_predis_atten[c]);
1476 } /* for each chain */
1477
1478 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1479
1480 } /* for each rate */
1481
1482 return 0;
1483 }
1484
1485 /**
1486 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
1487 *
1488 * Uses the active RXON for channel, band, and characteristics (ht40, high)
1489 * The power limit is taken from priv->tx_power_user_lmt.
1490 */
1491 static int iwl4965_send_tx_power(struct iwl_priv *priv)
1492 {
1493 struct iwl4965_txpowertable_cmd cmd = { 0 };
1494 int ret;
1495 u8 band = 0;
1496 bool is_ht40 = false;
1497 u8 ctrl_chan_high = 0;
1498
1499 if (test_bit(STATUS_SCANNING, &priv->status)) {
1500 /* If this gets hit a lot, switch it to a BUG() and catch
1501 * the stack trace to find out who is calling this during
1502 * a scan. */
1503 IWL_WARN(priv, "TX Power requested while scanning!\n");
1504 return -EAGAIN;
1505 }
1506
1507 band = priv->band == IEEE80211_BAND_2GHZ;
1508
1509 is_ht40 = is_ht40_channel(priv->active_rxon.flags);
1510
1511 if (is_ht40 &&
1512 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1513 ctrl_chan_high = 1;
1514
1515 cmd.band = band;
1516 cmd.channel = priv->active_rxon.channel;
1517
1518 ret = iwl4965_fill_txpower_tbl(priv, band,
1519 le16_to_cpu(priv->active_rxon.channel),
1520 is_ht40, ctrl_chan_high, &cmd.tx_power);
1521 if (ret)
1522 goto out;
1523
1524 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1525
1526 out:
1527 return ret;
1528 }
1529
1530 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1531 {
1532 int ret = 0;
1533 struct iwl4965_rxon_assoc_cmd rxon_assoc;
1534 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1535 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1536
1537 if ((rxon1->flags == rxon2->flags) &&
1538 (rxon1->filter_flags == rxon2->filter_flags) &&
1539 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1540 (rxon1->ofdm_ht_single_stream_basic_rates ==
1541 rxon2->ofdm_ht_single_stream_basic_rates) &&
1542 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1543 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1544 (rxon1->rx_chain == rxon2->rx_chain) &&
1545 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1546 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1547 return 0;
1548 }
1549
1550 rxon_assoc.flags = priv->staging_rxon.flags;
1551 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1552 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1553 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1554 rxon_assoc.reserved = 0;
1555 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1556 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1557 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1558 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1559 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1560
1561 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1562 sizeof(rxon_assoc), &rxon_assoc, NULL);
1563 if (ret)
1564 return ret;
1565
1566 return ret;
1567 }
1568
1569 #ifdef IEEE80211_CONF_CHANNEL_SWITCH
1570 static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1571 {
1572 int rc;
1573 u8 band = 0;
1574 bool is_ht40 = false;
1575 u8 ctrl_chan_high = 0;
1576 struct iwl4965_channel_switch_cmd cmd = { 0 };
1577 const struct iwl_channel_info *ch_info;
1578
1579 band = priv->band == IEEE80211_BAND_2GHZ;
1580
1581 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1582
1583 is_ht40 = is_ht40_channel(priv->staging_rxon.flags);
1584
1585 if (is_ht40 &&
1586 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1587 ctrl_chan_high = 1;
1588
1589 cmd.band = band;
1590 cmd.expect_beacon = 0;
1591 cmd.channel = cpu_to_le16(channel);
1592 cmd.rxon_flags = priv->active_rxon.flags;
1593 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1594 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1595 if (ch_info)
1596 cmd.expect_beacon = is_channel_radar(ch_info);
1597 else
1598 cmd.expect_beacon = 1;
1599
1600 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_ht40,
1601 ctrl_chan_high, &cmd.tx_power);
1602 if (rc) {
1603 IWL_DEBUG_11H(priv, "error:%d fill txpower_tbl\n", rc);
1604 return rc;
1605 }
1606
1607 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
1608 return rc;
1609 }
1610 #endif
1611
1612 /**
1613 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
1614 */
1615 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
1616 struct iwl_tx_queue *txq,
1617 u16 byte_cnt)
1618 {
1619 struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
1620 int txq_id = txq->q.id;
1621 int write_ptr = txq->q.write_ptr;
1622 int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1623 __le16 bc_ent;
1624
1625 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
1626
1627 bc_ent = cpu_to_le16(len & 0xFFF);
1628 /* Set up byte count within first 256 entries */
1629 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
1630
1631 /* If within first 64 entries, duplicate at end */
1632 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
1633 scd_bc_tbl[txq_id].
1634 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
1635 }
1636
1637 /**
1638 * sign_extend - Sign extend a value using specified bit as sign-bit
1639 *
1640 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1641 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1642 *
1643 * @param oper value to sign extend
1644 * @param index 0 based bit index (0<=index<32) to sign bit
1645 */
1646 static s32 sign_extend(u32 oper, int index)
1647 {
1648 u8 shift = 31 - index;
1649
1650 return (s32)(oper << shift) >> shift;
1651 }
1652
1653 /**
1654 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
1655 * @statistics: Provides the temperature reading from the uCode
1656 *
1657 * A return of <0 indicates bogus data in the statistics
1658 */
1659 static int iwl4965_hw_get_temperature(struct iwl_priv *priv)
1660 {
1661 s32 temperature;
1662 s32 vt;
1663 s32 R1, R2, R3;
1664 u32 R4;
1665
1666 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1667 (priv->statistics.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)) {
1668 IWL_DEBUG_TEMP(priv, "Running HT40 temperature calibration\n");
1669 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1670 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1671 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1672 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1673 } else {
1674 IWL_DEBUG_TEMP(priv, "Running temperature calibration\n");
1675 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1676 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1677 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1678 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1679 }
1680
1681 /*
1682 * Temperature is only 23 bits, so sign extend out to 32.
1683 *
1684 * NOTE If we haven't received a statistics notification yet
1685 * with an updated temperature, use R4 provided to us in the
1686 * "initialize" ALIVE response.
1687 */
1688 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1689 vt = sign_extend(R4, 23);
1690 else
1691 vt = sign_extend(
1692 le32_to_cpu(priv->statistics.general.temperature), 23);
1693
1694 IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
1695
1696 if (R3 == R1) {
1697 IWL_ERR(priv, "Calibration conflict R1 == R3\n");
1698 return -1;
1699 }
1700
1701 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1702 * Add offset to center the adjustment around 0 degrees Centigrade. */
1703 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1704 temperature /= (R3 - R1);
1705 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
1706
1707 IWL_DEBUG_TEMP(priv, "Calibrated temperature: %dK, %dC\n",
1708 temperature, KELVIN_TO_CELSIUS(temperature));
1709
1710 return temperature;
1711 }
1712
1713 /* Adjust Txpower only if temperature variance is greater than threshold. */
1714 #define IWL_TEMPERATURE_THRESHOLD 3
1715
1716 /**
1717 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1718 *
1719 * If the temperature changed has changed sufficiently, then a recalibration
1720 * is needed.
1721 *
1722 * Assumes caller will replace priv->last_temperature once calibration
1723 * executed.
1724 */
1725 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
1726 {
1727 int temp_diff;
1728
1729 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1730 IWL_DEBUG_TEMP(priv, "Temperature not updated -- no statistics.\n");
1731 return 0;
1732 }
1733
1734 temp_diff = priv->temperature - priv->last_temperature;
1735
1736 /* get absolute value */
1737 if (temp_diff < 0) {
1738 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d, \n", temp_diff);
1739 temp_diff = -temp_diff;
1740 } else if (temp_diff == 0)
1741 IWL_DEBUG_POWER(priv, "Same temp, \n");
1742 else
1743 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d, \n", temp_diff);
1744
1745 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1746 IWL_DEBUG_POWER(priv, "Thermal txpower calib not needed\n");
1747 return 0;
1748 }
1749
1750 IWL_DEBUG_POWER(priv, "Thermal txpower calib needed\n");
1751
1752 return 1;
1753 }
1754
1755 static void iwl4965_temperature_calib(struct iwl_priv *priv)
1756 {
1757 s32 temp;
1758
1759 temp = iwl4965_hw_get_temperature(priv);
1760 if (temp < 0)
1761 return;
1762
1763 if (priv->temperature != temp) {
1764 if (priv->temperature)
1765 IWL_DEBUG_TEMP(priv, "Temperature changed "
1766 "from %dC to %dC\n",
1767 KELVIN_TO_CELSIUS(priv->temperature),
1768 KELVIN_TO_CELSIUS(temp));
1769 else
1770 IWL_DEBUG_TEMP(priv, "Temperature "
1771 "initialized to %dC\n",
1772 KELVIN_TO_CELSIUS(temp));
1773 }
1774
1775 priv->temperature = temp;
1776 iwl_tt_handler(priv);
1777 set_bit(STATUS_TEMPERATURE, &priv->status);
1778
1779 if (!priv->disable_tx_power_cal &&
1780 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1781 iwl4965_is_temp_calib_needed(priv))
1782 queue_work(priv->workqueue, &priv->txpower_work);
1783 }
1784
1785 /**
1786 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1787 */
1788 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
1789 u16 txq_id)
1790 {
1791 /* Simply stop the queue, but don't change any configuration;
1792 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1793 iwl_write_prph(priv,
1794 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1795 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1796 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1797 }
1798
1799 /**
1800 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
1801 * priv->lock must be held by the caller
1802 */
1803 static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1804 u16 ssn_idx, u8 tx_fifo)
1805 {
1806 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1807 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1808 IWL_WARN(priv,
1809 "queue number out of range: %d, must be %d to %d\n",
1810 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1811 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
1812 return -EINVAL;
1813 }
1814
1815 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1816
1817 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1818
1819 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1820 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1821 /* supposes that ssn_idx is valid (!= 0xFFF) */
1822 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1823
1824 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1825 iwl_txq_ctx_deactivate(priv, txq_id);
1826 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1827
1828 return 0;
1829 }
1830
1831 /**
1832 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1833 */
1834 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
1835 u16 txq_id)
1836 {
1837 u32 tbl_dw_addr;
1838 u32 tbl_dw;
1839 u16 scd_q2ratid;
1840
1841 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1842
1843 tbl_dw_addr = priv->scd_base_addr +
1844 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1845
1846 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1847
1848 if (txq_id & 0x1)
1849 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1850 else
1851 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1852
1853 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1854
1855 return 0;
1856 }
1857
1858
1859 /**
1860 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1861 *
1862 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
1863 * i.e. it must be one of the higher queues used for aggregation
1864 */
1865 static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1866 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1867 {
1868 unsigned long flags;
1869 u16 ra_tid;
1870
1871 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1872 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1873 IWL_WARN(priv,
1874 "queue number out of range: %d, must be %d to %d\n",
1875 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1876 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
1877 return -EINVAL;
1878 }
1879
1880 ra_tid = BUILD_RAxTID(sta_id, tid);
1881
1882 /* Modify device's station table to Tx this TID */
1883 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1884
1885 spin_lock_irqsave(&priv->lock, flags);
1886
1887 /* Stop this Tx queue before configuring it */
1888 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1889
1890 /* Map receiver-address / traffic-ID to this queue */
1891 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1892
1893 /* Set this queue as a chain-building queue */
1894 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1895
1896 /* Place first TFD at index corresponding to start sequence number.
1897 * Assumes that ssn_idx is valid (!= 0xFFF) */
1898 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1899 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1900 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1901
1902 /* Set up Tx window size and frame limit for this queue */
1903 iwl_write_targ_mem(priv,
1904 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1905 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1906 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1907
1908 iwl_write_targ_mem(priv, priv->scd_base_addr +
1909 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1910 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1911 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1912
1913 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1914
1915 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1916 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1917
1918 spin_unlock_irqrestore(&priv->lock, flags);
1919
1920 return 0;
1921 }
1922
1923
1924 static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1925 {
1926 switch (cmd_id) {
1927 case REPLY_RXON:
1928 return (u16) sizeof(struct iwl4965_rxon_cmd);
1929 default:
1930 return len;
1931 }
1932 }
1933
1934 static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1935 {
1936 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1937 addsta->mode = cmd->mode;
1938 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1939 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1940 addsta->station_flags = cmd->station_flags;
1941 addsta->station_flags_msk = cmd->station_flags_msk;
1942 addsta->tid_disable_tx = cmd->tid_disable_tx;
1943 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1944 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1945 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1946 addsta->reserved1 = cpu_to_le16(0);
1947 addsta->reserved2 = cpu_to_le32(0);
1948
1949 return (u16)sizeof(struct iwl4965_addsta_cmd);
1950 }
1951
1952 static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
1953 {
1954 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
1955 }
1956
1957 /**
1958 * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
1959 */
1960 static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
1961 struct iwl_ht_agg *agg,
1962 struct iwl4965_tx_resp *tx_resp,
1963 int txq_id, u16 start_idx)
1964 {
1965 u16 status;
1966 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
1967 struct ieee80211_tx_info *info = NULL;
1968 struct ieee80211_hdr *hdr = NULL;
1969 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1970 int i, sh, idx;
1971 u16 seq;
1972 if (agg->wait_for_ba)
1973 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1974
1975 agg->frame_count = tx_resp->frame_count;
1976 agg->start_idx = start_idx;
1977 agg->rate_n_flags = rate_n_flags;
1978 agg->bitmap = 0;
1979
1980 /* num frames attempted by Tx command */
1981 if (agg->frame_count == 1) {
1982 /* Only one frame was attempted; no block-ack will arrive */
1983 status = le16_to_cpu(frame_status[0].status);
1984 idx = start_idx;
1985
1986 /* FIXME: code repetition */
1987 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1988 agg->frame_count, agg->start_idx, idx);
1989
1990 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1991 info->status.rates[0].count = tx_resp->failure_frame + 1;
1992 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1993 info->flags |= iwl_is_tx_success(status) ?
1994 IEEE80211_TX_STAT_ACK : 0;
1995 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1996 /* FIXME: code repetition end */
1997
1998 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1999 status & 0xff, tx_resp->failure_frame);
2000 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
2001
2002 agg->wait_for_ba = 0;
2003 } else {
2004 /* Two or more frames were attempted; expect block-ack */
2005 u64 bitmap = 0;
2006 int start = agg->start_idx;
2007
2008 /* Construct bit-map of pending frames within Tx window */
2009 for (i = 0; i < agg->frame_count; i++) {
2010 u16 sc;
2011 status = le16_to_cpu(frame_status[i].status);
2012 seq = le16_to_cpu(frame_status[i].sequence);
2013 idx = SEQ_TO_INDEX(seq);
2014 txq_id = SEQ_TO_QUEUE(seq);
2015
2016 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
2017 AGG_TX_STATE_ABORT_MSK))
2018 continue;
2019
2020 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
2021 agg->frame_count, txq_id, idx);
2022
2023 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
2024
2025 sc = le16_to_cpu(hdr->seq_ctrl);
2026 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2027 IWL_ERR(priv,
2028 "BUG_ON idx doesn't match seq control"
2029 " idx=%d, seq_idx=%d, seq=%d\n",
2030 idx, SEQ_TO_SN(sc), hdr->seq_ctrl);
2031 return -1;
2032 }
2033
2034 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
2035 i, idx, SEQ_TO_SN(sc));
2036
2037 sh = idx - start;
2038 if (sh > 64) {
2039 sh = (start - idx) + 0xff;
2040 bitmap = bitmap << sh;
2041 sh = 0;
2042 start = idx;
2043 } else if (sh < -64)
2044 sh = 0xff - (start - idx);
2045 else if (sh < 0) {
2046 sh = start - idx;
2047 start = idx;
2048 bitmap = bitmap << sh;
2049 sh = 0;
2050 }
2051 bitmap |= 1ULL << sh;
2052 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
2053 start, (unsigned long long)bitmap);
2054 }
2055
2056 agg->bitmap = bitmap;
2057 agg->start_idx = start;
2058 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
2059 agg->frame_count, agg->start_idx,
2060 (unsigned long long)agg->bitmap);
2061
2062 if (bitmap)
2063 agg->wait_for_ba = 1;
2064 }
2065 return 0;
2066 }
2067
2068 /**
2069 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
2070 */
2071 static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2072 struct iwl_rx_mem_buffer *rxb)
2073 {
2074 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2075 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2076 int txq_id = SEQ_TO_QUEUE(sequence);
2077 int index = SEQ_TO_INDEX(sequence);
2078 struct iwl_tx_queue *txq = &priv->txq[txq_id];
2079 struct ieee80211_hdr *hdr;
2080 struct ieee80211_tx_info *info;
2081 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2082 u32 status = le32_to_cpu(tx_resp->u.status);
2083 int tid = MAX_TID_COUNT;
2084 int sta_id;
2085 int freed;
2086 u8 *qc = NULL;
2087
2088 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
2089 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
2090 "is out of range [0-%d] %d %d\n", txq_id,
2091 index, txq->q.n_bd, txq->q.write_ptr,
2092 txq->q.read_ptr);
2093 return;
2094 }
2095
2096 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
2097 memset(&info->status, 0, sizeof(info->status));
2098
2099 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
2100 if (ieee80211_is_data_qos(hdr->frame_control)) {
2101 qc = ieee80211_get_qos_ctl(hdr);
2102 tid = qc[0] & 0xf;
2103 }
2104
2105 sta_id = iwl_get_ra_sta_id(priv, hdr);
2106 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2107 IWL_ERR(priv, "Station not known\n");
2108 return;
2109 }
2110
2111 if (txq->sched_retry) {
2112 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2113 struct iwl_ht_agg *agg = NULL;
2114
2115 WARN_ON(!qc);
2116
2117 agg = &priv->stations[sta_id].tid[tid].agg;
2118
2119 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
2120
2121 /* check if BAR is needed */
2122 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2123 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2124
2125 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2126 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2127 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
2128 "%d index %d\n", scd_ssn , index);
2129 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2130 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2131
2132 if (priv->mac80211_registered &&
2133 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2134 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
2135 if (agg->state == IWL_AGG_OFF)
2136 iwl_wake_queue(priv, txq_id);
2137 else
2138 iwl_wake_queue(priv, txq->swq_id);
2139 }
2140 }
2141 } else {
2142 info->status.rates[0].count = tx_resp->failure_frame + 1;
2143 info->flags |= iwl_is_tx_success(status) ?
2144 IEEE80211_TX_STAT_ACK : 0;
2145 iwl_hwrate_to_tx_control(priv,
2146 le32_to_cpu(tx_resp->rate_n_flags),
2147 info);
2148
2149 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) "
2150 "rate_n_flags 0x%x retries %d\n",
2151 txq_id,
2152 iwl_get_tx_fail_reason(status), status,
2153 le32_to_cpu(tx_resp->rate_n_flags),
2154 tx_resp->failure_frame);
2155
2156 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2157 if (qc && likely(sta_id != IWL_INVALID_STATION))
2158 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2159
2160 if (priv->mac80211_registered &&
2161 (iwl_queue_space(&txq->q) > txq->q.low_mark))
2162 iwl_wake_queue(priv, txq_id);
2163 }
2164
2165 if (qc && likely(sta_id != IWL_INVALID_STATION))
2166 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
2167
2168 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2169 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
2170 }
2171
2172 static int iwl4965_calc_rssi(struct iwl_priv *priv,
2173 struct iwl_rx_phy_res *rx_resp)
2174 {
2175 /* data from PHY/DSP regarding signal strength, etc.,
2176 * contents are always there, not configurable by host. */
2177 struct iwl4965_rx_non_cfg_phy *ncphy =
2178 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2179 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2180 >> IWL49_AGC_DB_POS;
2181
2182 u32 valid_antennae =
2183 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2184 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2185 u8 max_rssi = 0;
2186 u32 i;
2187
2188 /* Find max rssi among 3 possible receivers.
2189 * These values are measured by the digital signal processor (DSP).
2190 * They should stay fairly constant even as the signal strength varies,
2191 * if the radio's automatic gain control (AGC) is working right.
2192 * AGC value (see below) will provide the "interesting" info. */
2193 for (i = 0; i < 3; i++)
2194 if (valid_antennae & (1 << i))
2195 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2196
2197 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2198 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2199 max_rssi, agc);
2200
2201 /* dBm = max_rssi dB - agc dB - constant.
2202 * Higher AGC (higher radio gain) means lower signal. */
2203 return max_rssi - agc - IWL49_RSSI_OFFSET;
2204 }
2205
2206
2207 /* Set up 4965-specific Rx frame reply handlers */
2208 static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
2209 {
2210 /* Legacy Rx frames */
2211 priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
2212 /* Tx response */
2213 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
2214 }
2215
2216 static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
2217 {
2218 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
2219 }
2220
2221 static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
2222 {
2223 cancel_work_sync(&priv->txpower_work);
2224 }
2225
2226 #define IWL4965_UCODE_GET(item) \
2227 static u32 iwl4965_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2228 u32 api_ver) \
2229 { \
2230 return le32_to_cpu(ucode->u.v1.item); \
2231 }
2232
2233 static u32 iwl4965_ucode_get_header_size(u32 api_ver)
2234 {
2235 return UCODE_HEADER_SIZE(1);
2236 }
2237 static u32 iwl4965_ucode_get_build(const struct iwl_ucode_header *ucode,
2238 u32 api_ver)
2239 {
2240 return 0;
2241 }
2242 static u8 *iwl4965_ucode_get_data(const struct iwl_ucode_header *ucode,
2243 u32 api_ver)
2244 {
2245 return (u8 *) ucode->u.v1.data;
2246 }
2247
2248 IWL4965_UCODE_GET(inst_size);
2249 IWL4965_UCODE_GET(data_size);
2250 IWL4965_UCODE_GET(init_size);
2251 IWL4965_UCODE_GET(init_data_size);
2252 IWL4965_UCODE_GET(boot_size);
2253
2254 static struct iwl_hcmd_ops iwl4965_hcmd = {
2255 .rxon_assoc = iwl4965_send_rxon_assoc,
2256 .commit_rxon = iwl_commit_rxon,
2257 .set_rxon_chain = iwl_set_rxon_chain,
2258 };
2259
2260 static struct iwl_ucode_ops iwl4965_ucode = {
2261 .get_header_size = iwl4965_ucode_get_header_size,
2262 .get_build = iwl4965_ucode_get_build,
2263 .get_inst_size = iwl4965_ucode_get_inst_size,
2264 .get_data_size = iwl4965_ucode_get_data_size,
2265 .get_init_size = iwl4965_ucode_get_init_size,
2266 .get_init_data_size = iwl4965_ucode_get_init_data_size,
2267 .get_boot_size = iwl4965_ucode_get_boot_size,
2268 .get_data = iwl4965_ucode_get_data,
2269 };
2270 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
2271 .get_hcmd_size = iwl4965_get_hcmd_size,
2272 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
2273 .chain_noise_reset = iwl4965_chain_noise_reset,
2274 .gain_computation = iwl4965_gain_computation,
2275 .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag,
2276 .calc_rssi = iwl4965_calc_rssi,
2277 };
2278
2279 static struct iwl_lib_ops iwl4965_lib = {
2280 .set_hw_params = iwl4965_hw_set_hw_params,
2281 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
2282 .txq_set_sched = iwl4965_txq_set_sched,
2283 .txq_agg_enable = iwl4965_txq_agg_enable,
2284 .txq_agg_disable = iwl4965_txq_agg_disable,
2285 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
2286 .txq_free_tfd = iwl_hw_txq_free_tfd,
2287 .txq_init = iwl_hw_tx_queue_init,
2288 .rx_handler_setup = iwl4965_rx_handler_setup,
2289 .setup_deferred_work = iwl4965_setup_deferred_work,
2290 .cancel_deferred_work = iwl4965_cancel_deferred_work,
2291 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2292 .alive_notify = iwl4965_alive_notify,
2293 .init_alive_start = iwl4965_init_alive_start,
2294 .load_ucode = iwl4965_load_bsm,
2295 .apm_ops = {
2296 .init = iwl4965_apm_init,
2297 .reset = iwl4965_apm_reset,
2298 .stop = iwl4965_apm_stop,
2299 .config = iwl4965_nic_config,
2300 .set_pwr_src = iwl_set_pwr_src,
2301 },
2302 .eeprom_ops = {
2303 .regulatory_bands = {
2304 EEPROM_REGULATORY_BAND_1_CHANNELS,
2305 EEPROM_REGULATORY_BAND_2_CHANNELS,
2306 EEPROM_REGULATORY_BAND_3_CHANNELS,
2307 EEPROM_REGULATORY_BAND_4_CHANNELS,
2308 EEPROM_REGULATORY_BAND_5_CHANNELS,
2309 EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS,
2310 EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS
2311 },
2312 .verify_signature = iwlcore_eeprom_verify_signature,
2313 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2314 .release_semaphore = iwlcore_eeprom_release_semaphore,
2315 .calib_version = iwl4965_eeprom_calib_version,
2316 .query_addr = iwlcore_eeprom_query_addr,
2317 },
2318 .send_tx_power = iwl4965_send_tx_power,
2319 .update_chain_flags = iwl_update_chain_flags,
2320 .post_associate = iwl_post_associate,
2321 .config_ap = iwl_config_ap,
2322 .isr = iwl_isr_legacy,
2323 .temp_ops = {
2324 .temperature = iwl4965_temperature_calib,
2325 .set_ct_kill = iwl4965_set_ct_threshold,
2326 },
2327 };
2328
2329 static struct iwl_ops iwl4965_ops = {
2330 .ucode = &iwl4965_ucode,
2331 .lib = &iwl4965_lib,
2332 .hcmd = &iwl4965_hcmd,
2333 .utils = &iwl4965_hcmd_utils,
2334 };
2335
2336 struct iwl_cfg iwl4965_agn_cfg = {
2337 .name = "4965AGN",
2338 .fw_name_pre = IWL4965_FW_PRE,
2339 .ucode_api_max = IWL4965_UCODE_API_MAX,
2340 .ucode_api_min = IWL4965_UCODE_API_MIN,
2341 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
2342 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
2343 .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2344 .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
2345 .ops = &iwl4965_ops,
2346 .mod_params = &iwl4965_mod_params,
2347 .use_isr_legacy = true,
2348 .ht_greenfield_support = false,
2349 };
2350
2351 /* Module firmware */
2352 MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX));
2353
2354 module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
2355 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2356 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
2357 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
2358 module_param_named(
2359 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
2360 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2361
2362 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
2363 MODULE_PARM_DESC(queues_num, "number of hw queues.");
2364 /* 11n */
2365 module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, 0444);
2366 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
2367 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
2368 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
2369
2370 module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
2371 MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
Linux with added FPC-III support