drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "drmP.h"
  29 #include "vmwgfx_drv.h"
  30 #include "ttm/ttm_placement.h"
  31 #include "ttm/ttm_bo_driver.h"
  32 #include "ttm/ttm_object.h"
  33 #include "ttm/ttm_module.h"
  34
  35 #define VMWGFX_DRIVER_NAME "vmwgfx"
  36 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  37 #define VMWGFX_CHIP_SVGAII 0
  38 #define VMW_FB_RESERVATION 0
  39
  40 /**
  41  * Fully encoded drm commands. Might move to vmw_drm.h
  42  */
  43
  44 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  45         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  46                  struct drm_vmw_getparam_arg)
  47 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  48         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  49                 union drm_vmw_alloc_dmabuf_arg)
  50 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  51         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  52                 struct drm_vmw_unref_dmabuf_arg)
  53 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  54         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  55                  struct drm_vmw_cursor_bypass_arg)
  56
  57 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  58         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  59                  struct drm_vmw_control_stream_arg)
  60 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  61         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  62                  struct drm_vmw_stream_arg)
  63 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  64         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  65                  struct drm_vmw_stream_arg)
  66
  67 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  68         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  69                 struct drm_vmw_context_arg)
  70 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  71         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  72                 struct drm_vmw_context_arg)
  73 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  74         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  75                  union drm_vmw_surface_create_arg)
  76 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  77         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  78                  struct drm_vmw_surface_arg)
  79 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  80         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  81                  union drm_vmw_surface_reference_arg)
  82 #define DRM_IOCTL_VMW_EXECBUF                                   \
  83         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  84                 struct drm_vmw_execbuf_arg)
  85 #define DRM_IOCTL_VMW_FIFO_DEBUG                                \
  86         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FIFO_DEBUG,         \
  87                  struct drm_vmw_fifo_debug_arg)
  88 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
  89         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
  90                  struct drm_vmw_fence_wait_arg)
  91 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
  92         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,      \
  93                  struct drm_vmw_update_layout_arg)
  94
  95
  96 /**
  97  * The core DRM version of this macro doesn't account for
  98  * DRM_COMMAND_BASE.
  99  */
 100
 101 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 102   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
 103
 104 /**
 105  * Ioctl definitions.
 106  */
 107
 108 static struct drm_ioctl_desc vmw_ioctls[] = {
 109         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 110                       DRM_AUTH | DRM_UNLOCKED),
 111         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
 112                       DRM_AUTH | DRM_UNLOCKED),
 113         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
 114                       DRM_AUTH | DRM_UNLOCKED),
 115         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 116                       vmw_kms_cursor_bypass_ioctl,
 117                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 118
 119         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 120                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 121         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 122                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 123         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 124                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 125
 126         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 127                       DRM_AUTH | DRM_UNLOCKED),
 128         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 129                       DRM_AUTH | DRM_UNLOCKED),
 130         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 131                       DRM_AUTH | DRM_UNLOCKED),
 132         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 133                       DRM_AUTH | DRM_UNLOCKED),
 134         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 135                       DRM_AUTH | DRM_UNLOCKED),
 136         VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
 137                       DRM_AUTH | DRM_UNLOCKED),
 138         VMW_IOCTL_DEF(VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl,
 139                       DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED),
 140         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_wait_ioctl,
 141                       DRM_AUTH | DRM_UNLOCKED),
 142         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, vmw_kms_update_layout_ioctl,
 143                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED)
 144 };
 145
 146 static struct pci_device_id vmw_pci_id_list[] = {
 147         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 148         {0, 0, 0}
 149 };
 150 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
 151
 152 static int enable_fbdev;
 153
 154 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 155 static void vmw_master_init(struct vmw_master *);
 156 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 157                               void *ptr);
 158
 159 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 160 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 161
 162 static void vmw_print_capabilities(uint32_t capabilities)
 163 {
 164         DRM_INFO("Capabilities:\n");
 165         if (capabilities & SVGA_CAP_RECT_COPY)
 166                 DRM_INFO("  Rect copy.\n");
 167         if (capabilities & SVGA_CAP_CURSOR)
 168                 DRM_INFO("  Cursor.\n");
 169         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 170                 DRM_INFO("  Cursor bypass.\n");
 171         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 172                 DRM_INFO("  Cursor bypass 2.\n");
 173         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 174                 DRM_INFO("  8bit emulation.\n");
 175         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 176                 DRM_INFO("  Alpha cursor.\n");
 177         if (capabilities & SVGA_CAP_3D)
 178                 DRM_INFO("  3D.\n");
 179         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 180                 DRM_INFO("  Extended Fifo.\n");
 181         if (capabilities & SVGA_CAP_MULTIMON)
 182                 DRM_INFO("  Multimon.\n");
 183         if (capabilities & SVGA_CAP_PITCHLOCK)
 184                 DRM_INFO("  Pitchlock.\n");
 185         if (capabilities & SVGA_CAP_IRQMASK)
 186                 DRM_INFO("  Irq mask.\n");
 187         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 188                 DRM_INFO("  Display Topology.\n");
 189         if (capabilities & SVGA_CAP_GMR)
 190                 DRM_INFO("  GMR.\n");
 191         if (capabilities & SVGA_CAP_TRACES)
 192                 DRM_INFO("  Traces.\n");
 193 }
 194
 195 static int vmw_request_device(struct vmw_private *dev_priv)
 196 {
 197         int ret;
 198
 199         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 200         if (unlikely(ret != 0)) {
 201                 DRM_ERROR("Unable to initialize FIFO.\n");
 202                 return ret;
 203         }
 204
 205         return 0;
 206 }
 207
 208 static void vmw_release_device(struct vmw_private *dev_priv)
 209 {
 210         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 211 }
 212
 213 int vmw_3d_resource_inc(struct vmw_private *dev_priv)
 214 {
 215         int ret = 0;
 216
 217         mutex_lock(&dev_priv->release_mutex);
 218         if (unlikely(dev_priv->num_3d_resources++ == 0)) {
 219                 ret = vmw_request_device(dev_priv);
 220                 if (unlikely(ret != 0))
 221                         --dev_priv->num_3d_resources;
 222         }
 223         mutex_unlock(&dev_priv->release_mutex);
 224         return ret;
 225 }
 226
 227
 228 void vmw_3d_resource_dec(struct vmw_private *dev_priv)
 229 {
 230         int32_t n3d;
 231
 232         mutex_lock(&dev_priv->release_mutex);
 233         if (unlikely(--dev_priv->num_3d_resources == 0))
 234                 vmw_release_device(dev_priv);
 235         n3d = (int32_t) dev_priv->num_3d_resources;
 236         mutex_unlock(&dev_priv->release_mutex);
 237
 238         BUG_ON(n3d < 0);
 239 }
 240
 241 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 242 {
 243         struct vmw_private *dev_priv;
 244         int ret;
 245         uint32_t svga_id;
 246
 247         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 248         if (unlikely(dev_priv == NULL)) {
 249                 DRM_ERROR("Failed allocating a device private struct.\n");
 250                 return -ENOMEM;
 251         }
 252         memset(dev_priv, 0, sizeof(*dev_priv));
 253
 254         dev_priv->dev = dev;
 255         dev_priv->vmw_chipset = chipset;
 256         dev_priv->last_read_sequence = (uint32_t) -100;
 257         mutex_init(&dev_priv->hw_mutex);
 258         mutex_init(&dev_priv->cmdbuf_mutex);
 259         mutex_init(&dev_priv->release_mutex);
 260         rwlock_init(&dev_priv->resource_lock);
 261         idr_init(&dev_priv->context_idr);
 262         idr_init(&dev_priv->surface_idr);
 263         idr_init(&dev_priv->stream_idr);
 264         mutex_init(&dev_priv->init_mutex);
 265         init_waitqueue_head(&dev_priv->fence_queue);
 266         init_waitqueue_head(&dev_priv->fifo_queue);
 267         atomic_set(&dev_priv->fence_queue_waiters, 0);
 268         atomic_set(&dev_priv->fifo_queue_waiters, 0);
 269
 270         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 271         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 272         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 273
 274         dev_priv->enable_fb = enable_fbdev;
 275
 276         mutex_lock(&dev_priv->hw_mutex);
 277
 278         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 279         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 280         if (svga_id != SVGA_ID_2) {
 281                 ret = -ENOSYS;
 282                 DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id);
 283                 mutex_unlock(&dev_priv->hw_mutex);
 284                 goto out_err0;
 285         }
 286
 287         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 288
 289         if (dev_priv->capabilities & SVGA_CAP_GMR) {
 290                 dev_priv->max_gmr_descriptors =
 291                         vmw_read(dev_priv,
 292                                  SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
 293                 dev_priv->max_gmr_ids =
 294                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 295         }
 296
 297         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 298         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 299         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 300         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 301
 302         mutex_unlock(&dev_priv->hw_mutex);
 303
 304         vmw_print_capabilities(dev_priv->capabilities);
 305
 306         if (dev_priv->capabilities & SVGA_CAP_GMR) {
 307                 DRM_INFO("Max GMR ids is %u\n",
 308                          (unsigned)dev_priv->max_gmr_ids);
 309                 DRM_INFO("Max GMR descriptors is %u\n",
 310                          (unsigned)dev_priv->max_gmr_descriptors);
 311         }
 312         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 313                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 314         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 315                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 316
 317         ret = vmw_ttm_global_init(dev_priv);
 318         if (unlikely(ret != 0))
 319                 goto out_err0;
 320
 321
 322         vmw_master_init(&dev_priv->fbdev_master);
 323         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 324         dev_priv->active_master = &dev_priv->fbdev_master;
 325
 326
 327         ret = ttm_bo_device_init(&dev_priv->bdev,
 328                                  dev_priv->bo_global_ref.ref.object,
 329                                  &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
 330                                  false);
 331         if (unlikely(ret != 0)) {
 332                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 333                 goto out_err1;
 334         }
 335
 336         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 337                              (dev_priv->vram_size >> PAGE_SHIFT));
 338         if (unlikely(ret != 0)) {
 339                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 340                 goto out_err2;
 341         }
 342
 343         dev_priv->has_gmr = true;
 344         if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 345                            dev_priv->max_gmr_ids) != 0) {
 346                 DRM_INFO("No GMR memory available. "
 347                          "Graphics memory resources are very limited.\n");
 348                 dev_priv->has_gmr = false;
 349         }
 350
 351         dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
 352                                            dev_priv->mmio_size, DRM_MTRR_WC);
 353
 354         dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
 355                                          dev_priv->mmio_size);
 356
 357         if (unlikely(dev_priv->mmio_virt == NULL)) {
 358                 ret = -ENOMEM;
 359                 DRM_ERROR("Failed mapping MMIO.\n");
 360                 goto out_err3;
 361         }
 362
 363         /* Need mmio memory to check for fifo pitchlock cap. */
 364         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 365             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 366             !vmw_fifo_have_pitchlock(dev_priv)) {
 367                 ret = -ENOSYS;
 368                 DRM_ERROR("Hardware has no pitchlock\n");
 369                 goto out_err4;
 370         }
 371
 372         dev_priv->tdev = ttm_object_device_init
 373             (dev_priv->mem_global_ref.object, 12);
 374
 375         if (unlikely(dev_priv->tdev == NULL)) {
 376                 DRM_ERROR("Unable to initialize TTM object management.\n");
 377                 ret = -ENOMEM;
 378                 goto out_err4;
 379         }
 380
 381         dev->dev_private = dev_priv;
 382
 383         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 384         dev_priv->stealth = (ret != 0);
 385         if (dev_priv->stealth) {
 386                 /**
 387                  * Request at least the mmio PCI resource.
 388                  */
 389
 390                 DRM_INFO("It appears like vesafb is loaded. "
 391                          "Ignore above error if any.\n");
 392                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 393                 if (unlikely(ret != 0)) {
 394                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 395                         goto out_no_device;
 396                 }
 397         }
 398         ret = vmw_kms_init(dev_priv);
 399         if (unlikely(ret != 0))
 400                 goto out_no_kms;
 401         vmw_overlay_init(dev_priv);
 402         if (dev_priv->enable_fb) {
 403                 ret = vmw_3d_resource_inc(dev_priv);
 404                 if (unlikely(ret != 0))
 405                         goto out_no_fifo;
 406                 vmw_kms_save_vga(dev_priv);
 407                 vmw_fb_init(dev_priv);
 408                 DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ?
 409                          "Detected device 3D availability.\n" :
 410                          "Detected no device 3D availability.\n");
 411         } else {
 412                 DRM_INFO("Delayed 3D detection since we're not "
 413                          "running the device in SVGA mode yet.\n");
 414         }
 415
 416         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 417                 ret = drm_irq_install(dev);
 418                 if (unlikely(ret != 0)) {
 419                         DRM_ERROR("Failed installing irq: %d\n", ret);
 420                         goto out_no_irq;
 421                 }
 422         }
 423
 424         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 425         register_pm_notifier(&dev_priv->pm_nb);
 426
 427         return 0;
 428
 429 out_no_irq:
 430         if (dev_priv->enable_fb) {
 431                 vmw_fb_close(dev_priv);
 432                 vmw_kms_restore_vga(dev_priv);
 433                 vmw_3d_resource_dec(dev_priv);
 434         }
 435 out_no_fifo:
 436         vmw_overlay_close(dev_priv);
 437         vmw_kms_close(dev_priv);
 438 out_no_kms:
 439         if (dev_priv->stealth)
 440                 pci_release_region(dev->pdev, 2);
 441         else
 442                 pci_release_regions(dev->pdev);
 443 out_no_device:
 444         ttm_object_device_release(&dev_priv->tdev);
 445 out_err4:
 446         iounmap(dev_priv->mmio_virt);
 447 out_err3:
 448         drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
 449                      dev_priv->mmio_size, DRM_MTRR_WC);
 450         if (dev_priv->has_gmr)
 451                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 452         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 453 out_err2:
 454         (void)ttm_bo_device_release(&dev_priv->bdev);
 455 out_err1:
 456         vmw_ttm_global_release(dev_priv);
 457 out_err0:
 458         idr_destroy(&dev_priv->surface_idr);
 459         idr_destroy(&dev_priv->context_idr);
 460         idr_destroy(&dev_priv->stream_idr);
 461         kfree(dev_priv);
 462         return ret;
 463 }
 464
 465 static int vmw_driver_unload(struct drm_device *dev)
 466 {
 467         struct vmw_private *dev_priv = vmw_priv(dev);
 468
 469         unregister_pm_notifier(&dev_priv->pm_nb);
 470
 471         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 472                 drm_irq_uninstall(dev_priv->dev);
 473         if (dev_priv->enable_fb) {
 474                 vmw_fb_close(dev_priv);
 475                 vmw_kms_restore_vga(dev_priv);
 476                 vmw_3d_resource_dec(dev_priv);
 477         }
 478         vmw_kms_close(dev_priv);
 479         vmw_overlay_close(dev_priv);
 480         if (dev_priv->stealth)
 481                 pci_release_region(dev->pdev, 2);
 482         else
 483                 pci_release_regions(dev->pdev);
 484
 485         ttm_object_device_release(&dev_priv->tdev);
 486         iounmap(dev_priv->mmio_virt);
 487         drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
 488                      dev_priv->mmio_size, DRM_MTRR_WC);
 489         if (dev_priv->has_gmr)
 490                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 491         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 492         (void)ttm_bo_device_release(&dev_priv->bdev);
 493         vmw_ttm_global_release(dev_priv);
 494         idr_destroy(&dev_priv->surface_idr);
 495         idr_destroy(&dev_priv->context_idr);
 496         idr_destroy(&dev_priv->stream_idr);
 497
 498         kfree(dev_priv);
 499
 500         return 0;
 501 }
 502
 503 static void vmw_postclose(struct drm_device *dev,
 504                          struct drm_file *file_priv)
 505 {
 506         struct vmw_fpriv *vmw_fp;
 507
 508         vmw_fp = vmw_fpriv(file_priv);
 509         ttm_object_file_release(&vmw_fp->tfile);
 510         if (vmw_fp->locked_master)
 511                 drm_master_put(&vmw_fp->locked_master);
 512         kfree(vmw_fp);
 513 }
 514
 515 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 516 {
 517         struct vmw_private *dev_priv = vmw_priv(dev);
 518         struct vmw_fpriv *vmw_fp;
 519         int ret = -ENOMEM;
 520
 521         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
 522         if (unlikely(vmw_fp == NULL))
 523                 return ret;
 524
 525         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
 526         if (unlikely(vmw_fp->tfile == NULL))
 527                 goto out_no_tfile;
 528
 529         file_priv->driver_priv = vmw_fp;
 530
 531         if (unlikely(dev_priv->bdev.dev_mapping == NULL))
 532                 dev_priv->bdev.dev_mapping =
 533                         file_priv->filp->f_path.dentry->d_inode->i_mapping;
 534
 535         return 0;
 536
 537 out_no_tfile:
 538         kfree(vmw_fp);
 539         return ret;
 540 }
 541
 542 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
 543                                unsigned long arg)
 544 {
 545         struct drm_file *file_priv = filp->private_data;
 546         struct drm_device *dev = file_priv->minor->dev;
 547         unsigned int nr = DRM_IOCTL_NR(cmd);
 548
 549         /*
 550          * Do extra checking on driver private ioctls.
 551          */
 552
 553         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
 554             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
 555                 struct drm_ioctl_desc *ioctl =
 556                     &vmw_ioctls[nr - DRM_COMMAND_BASE];
 557
 558                 if (unlikely(ioctl->cmd_drv != cmd)) {
 559                         DRM_ERROR("Invalid command format, ioctl %d\n",
 560                                   nr - DRM_COMMAND_BASE);
 561                         return -EINVAL;
 562                 }
 563         }
 564
 565         return drm_ioctl(filp, cmd, arg);
 566 }
 567
 568 static int vmw_firstopen(struct drm_device *dev)
 569 {
 570         struct vmw_private *dev_priv = vmw_priv(dev);
 571         dev_priv->is_opened = true;
 572
 573         return 0;
 574 }
 575
 576 static void vmw_lastclose(struct drm_device *dev)
 577 {
 578         struct vmw_private *dev_priv = vmw_priv(dev);
 579         struct drm_crtc *crtc;
 580         struct drm_mode_set set;
 581         int ret;
 582
 583         /**
 584          * Do nothing on the lastclose call from drm_unload.
 585          */
 586
 587         if (!dev_priv->is_opened)
 588                 return;
 589
 590         dev_priv->is_opened = false;
 591         set.x = 0;
 592         set.y = 0;
 593         set.fb = NULL;
 594         set.mode = NULL;
 595         set.connectors = NULL;
 596         set.num_connectors = 0;
 597
 598         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 599                 set.crtc = crtc;
 600                 ret = crtc->funcs->set_config(&set);
 601                 WARN_ON(ret != 0);
 602         }
 603
 604 }
 605
 606 static void vmw_master_init(struct vmw_master *vmaster)
 607 {
 608         ttm_lock_init(&vmaster->lock);
 609         INIT_LIST_HEAD(&vmaster->fb_surf);
 610         mutex_init(&vmaster->fb_surf_mutex);
 611 }
 612
 613 static int vmw_master_create(struct drm_device *dev,
 614                              struct drm_master *master)
 615 {
 616         struct vmw_master *vmaster;
 617
 618         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
 619         if (unlikely(vmaster == NULL))
 620                 return -ENOMEM;
 621
 622         vmw_master_init(vmaster);
 623         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 624         master->driver_priv = vmaster;
 625
 626         return 0;
 627 }
 628
 629 static void vmw_master_destroy(struct drm_device *dev,
 630                                struct drm_master *master)
 631 {
 632         struct vmw_master *vmaster = vmw_master(master);
 633
 634         master->driver_priv = NULL;
 635         kfree(vmaster);
 636 }
 637
 638
 639 static int vmw_master_set(struct drm_device *dev,
 640                           struct drm_file *file_priv,
 641                           bool from_open)
 642 {
 643         struct vmw_private *dev_priv = vmw_priv(dev);
 644         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 645         struct vmw_master *active = dev_priv->active_master;
 646         struct vmw_master *vmaster = vmw_master(file_priv->master);
 647         int ret = 0;
 648
 649         if (!dev_priv->enable_fb) {
 650                 ret = vmw_3d_resource_inc(dev_priv);
 651                 if (unlikely(ret != 0))
 652                         return ret;
 653                 vmw_kms_save_vga(dev_priv);
 654                 mutex_lock(&dev_priv->hw_mutex);
 655                 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
 656                 mutex_unlock(&dev_priv->hw_mutex);
 657         }
 658
 659         if (active) {
 660                 BUG_ON(active != &dev_priv->fbdev_master);
 661                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
 662                 if (unlikely(ret != 0))
 663                         goto out_no_active_lock;
 664
 665                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
 666                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
 667                 if (unlikely(ret != 0)) {
 668                         DRM_ERROR("Unable to clean VRAM on "
 669                                   "master drop.\n");
 670                 }
 671
 672                 dev_priv->active_master = NULL;
 673         }
 674
 675         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
 676         if (!from_open) {
 677                 ttm_vt_unlock(&vmaster->lock);
 678                 BUG_ON(vmw_fp->locked_master != file_priv->master);
 679                 drm_master_put(&vmw_fp->locked_master);
 680         }
 681
 682         dev_priv->active_master = vmaster;
 683
 684         return 0;
 685
 686 out_no_active_lock:
 687         if (!dev_priv->enable_fb) {
 688                 mutex_lock(&dev_priv->hw_mutex);
 689                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
 690                 mutex_unlock(&dev_priv->hw_mutex);
 691                 vmw_kms_restore_vga(dev_priv);
 692                 vmw_3d_resource_dec(dev_priv);
 693         }
 694         return ret;
 695 }
 696
 697 static void vmw_master_drop(struct drm_device *dev,
 698                             struct drm_file *file_priv,
 699                             bool from_release)
 700 {
 701         struct vmw_private *dev_priv = vmw_priv(dev);
 702         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 703         struct vmw_master *vmaster = vmw_master(file_priv->master);
 704         int ret;
 705
 706         /**
 707          * Make sure the master doesn't disappear while we have
 708          * it locked.
 709          */
 710
 711         vmw_fp->locked_master = drm_master_get(file_priv->master);
 712         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
 713         vmw_kms_idle_workqueues(vmaster);
 714
 715         if (unlikely((ret != 0))) {
 716                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
 717                 drm_master_put(&vmw_fp->locked_master);
 718         }
 719
 720         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 721
 722         if (!dev_priv->enable_fb) {
 723                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
 724                 if (unlikely(ret != 0))
 725                         DRM_ERROR("Unable to clean VRAM on master drop.\n");
 726                 mutex_lock(&dev_priv->hw_mutex);
 727                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
 728                 mutex_unlock(&dev_priv->hw_mutex);
 729                 vmw_kms_restore_vga(dev_priv);
 730                 vmw_3d_resource_dec(dev_priv);
 731         }
 732
 733         dev_priv->active_master = &dev_priv->fbdev_master;
 734         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 735         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
 736
 737         if (dev_priv->enable_fb)
 738                 vmw_fb_on(dev_priv);
 739 }
 740
 741
 742 static void vmw_remove(struct pci_dev *pdev)
 743 {
 744         struct drm_device *dev = pci_get_drvdata(pdev);
 745
 746         drm_put_dev(dev);
 747 }
 748
 749 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 750                               void *ptr)
 751 {
 752         struct vmw_private *dev_priv =
 753                 container_of(nb, struct vmw_private, pm_nb);
 754         struct vmw_master *vmaster = dev_priv->active_master;
 755
 756         switch (val) {
 757         case PM_HIBERNATION_PREPARE:
 758         case PM_SUSPEND_PREPARE:
 759                 ttm_suspend_lock(&vmaster->lock);
 760
 761                 /**
 762                  * This empties VRAM and unbinds all GMR bindings.
 763                  * Buffer contents is moved to swappable memory.
 764                  */
 765                 ttm_bo_swapout_all(&dev_priv->bdev);
 766
 767                 break;
 768         case PM_POST_HIBERNATION:
 769         case PM_POST_SUSPEND:
 770         case PM_POST_RESTORE:
 771                 ttm_suspend_unlock(&vmaster->lock);
 772
 773                 break;
 774         case PM_RESTORE_PREPARE:
 775                 break;
 776         default:
 777                 break;
 778         }
 779         return 0;
 780 }
 781
 782 /**
 783  * These might not be needed with the virtual SVGA device.
 784  */
 785
 786 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 787 {
 788         struct drm_device *dev = pci_get_drvdata(pdev);
 789         struct vmw_private *dev_priv = vmw_priv(dev);
 790
 791         if (dev_priv->num_3d_resources != 0) {
 792                 DRM_INFO("Can't suspend or hibernate "
 793                          "while 3D resources are active.\n");
 794                 return -EBUSY;
 795         }
 796
 797         pci_save_state(pdev);
 798         pci_disable_device(pdev);
 799         pci_set_power_state(pdev, PCI_D3hot);
 800         return 0;
 801 }
 802
 803 static int vmw_pci_resume(struct pci_dev *pdev)
 804 {
 805         pci_set_power_state(pdev, PCI_D0);
 806         pci_restore_state(pdev);
 807         return pci_enable_device(pdev);
 808 }
 809
 810 static int vmw_pm_suspend(struct device *kdev)
 811 {
 812         struct pci_dev *pdev = to_pci_dev(kdev);
 813         struct pm_message dummy;
 814
 815         dummy.event = 0;
 816
 817         return vmw_pci_suspend(pdev, dummy);
 818 }
 819
 820 static int vmw_pm_resume(struct device *kdev)
 821 {
 822         struct pci_dev *pdev = to_pci_dev(kdev);
 823
 824         return vmw_pci_resume(pdev);
 825 }
 826
 827 static int vmw_pm_prepare(struct device *kdev)
 828 {
 829         struct pci_dev *pdev = to_pci_dev(kdev);
 830         struct drm_device *dev = pci_get_drvdata(pdev);
 831         struct vmw_private *dev_priv = vmw_priv(dev);
 832
 833         /**
 834          * Release 3d reference held by fbdev and potentially
 835          * stop fifo.
 836          */
 837         dev_priv->suspended = true;
 838         if (dev_priv->enable_fb)
 839                 vmw_3d_resource_dec(dev_priv);
 840
 841         if (dev_priv->num_3d_resources != 0) {
 842
 843                 DRM_INFO("Can't suspend or hibernate "
 844                          "while 3D resources are active.\n");
 845
 846                 if (dev_priv->enable_fb)
 847                         vmw_3d_resource_inc(dev_priv);
 848                 dev_priv->suspended = false;
 849                 return -EBUSY;
 850         }
 851
 852         return 0;
 853 }
 854
 855 static void vmw_pm_complete(struct device *kdev)
 856 {
 857         struct pci_dev *pdev = to_pci_dev(kdev);
 858         struct drm_device *dev = pci_get_drvdata(pdev);
 859         struct vmw_private *dev_priv = vmw_priv(dev);
 860
 861         /**
 862          * Reclaim 3d reference held by fbdev and potentially
 863          * start fifo.
 864          */
 865         if (dev_priv->enable_fb)
 866                 vmw_3d_resource_inc(dev_priv);
 867
 868         dev_priv->suspended = false;
 869 }
 870
 871 static const struct dev_pm_ops vmw_pm_ops = {
 872         .prepare = vmw_pm_prepare,
 873         .complete = vmw_pm_complete,
 874         .suspend = vmw_pm_suspend,
 875         .resume = vmw_pm_resume,
 876 };
 877
 878 static struct drm_driver driver = {
 879         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
 880         DRIVER_MODESET,
 881         .load = vmw_driver_load,
 882         .unload = vmw_driver_unload,
 883         .firstopen = vmw_firstopen,
 884         .lastclose = vmw_lastclose,
 885         .irq_preinstall = vmw_irq_preinstall,
 886         .irq_postinstall = vmw_irq_postinstall,
 887         .irq_uninstall = vmw_irq_uninstall,
 888         .irq_handler = vmw_irq_handler,
 889         .get_vblank_counter = vmw_get_vblank_counter,
 890         .reclaim_buffers_locked = NULL,
 891         .ioctls = vmw_ioctls,
 892         .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
 893         .dma_quiescent = NULL,  /*vmw_dma_quiescent, */
 894         .master_create = vmw_master_create,
 895         .master_destroy = vmw_master_destroy,
 896         .master_set = vmw_master_set,
 897         .master_drop = vmw_master_drop,
 898         .open = vmw_driver_open,
 899         .postclose = vmw_postclose,
 900         .fops = {
 901                  .owner = THIS_MODULE,
 902                  .open = drm_open,
 903                  .release = drm_release,
 904                  .unlocked_ioctl = vmw_unlocked_ioctl,
 905                  .mmap = vmw_mmap,
 906                  .poll = drm_poll,
 907                  .fasync = drm_fasync,
 908 #if defined(CONFIG_COMPAT)
 909                  .compat_ioctl = drm_compat_ioctl,
 910 #endif
 911                  .llseek = noop_llseek,
 912         },
 913         .name = VMWGFX_DRIVER_NAME,
 914         .desc = VMWGFX_DRIVER_DESC,
 915         .date = VMWGFX_DRIVER_DATE,
 916         .major = VMWGFX_DRIVER_MAJOR,
 917         .minor = VMWGFX_DRIVER_MINOR,
 918         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
 919 };
 920
 921 static struct pci_driver vmw_pci_driver = {
 922         .name = VMWGFX_DRIVER_NAME,
 923         .id_table = vmw_pci_id_list,
 924         .probe = vmw_probe,
 925         .remove = vmw_remove,
 926         .driver = {
 927                 .pm = &vmw_pm_ops
 928         }
 929 };
 930
 931 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 932 {
 933         return drm_get_pci_dev(pdev, ent, &driver);
 934 }
 935
 936 static int __init vmwgfx_init(void)
 937 {
 938         int ret;
 939         ret = drm_pci_init(&driver, &vmw_pci_driver);
 940         if (ret)
 941                 DRM_ERROR("Failed initializing DRM.\n");
 942         return ret;
 943 }
 944
 945 static void __exit vmwgfx_exit(void)
 946 {
 947         drm_pci_exit(&driver, &vmw_pci_driver);
 948 }
 949
 950 module_init(vmwgfx_init);
 951 module_exit(vmwgfx_exit);
 952
 953 MODULE_AUTHOR("VMware Inc. and others");
 954 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
 955 MODULE_LICENSE("GPL and additional rights");
 956 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
 957                __stringify(VMWGFX_DRIVER_MINOR) "."
 958                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
 959                "0");