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Linux 5.9.7
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
blobcf6e47adfde6fc3262555548d3e8e47fe80f3651
1 /*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30 #include <linux/ascii85.h>
31 #include <linux/nmi.h>
32 #include <linux/pagevec.h>
33 #include <linux/scatterlist.h>
34 #include <linux/utsname.h>
35 #include <linux/zlib.h>
36
37 #include <drm/drm_print.h>
38
39 #include "display/intel_atomic.h"
40 #include "display/intel_csr.h"
41 #include "display/intel_overlay.h"
42
43 #include "gem/i915_gem_context.h"
44 #include "gem/i915_gem_lmem.h"
45 #include "gt/intel_gt.h"
46 #include "gt/intel_gt_pm.h"
47
48 #include "i915_drv.h"
49 #include "i915_gpu_error.h"
50 #include "i915_memcpy.h"
51 #include "i915_scatterlist.h"
52
53 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
54 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
55
56 static void __sg_set_buf(struct scatterlist *sg,
57 void *addr, unsigned int len, loff_t it)
58 {
59 sg->page_link = (unsigned long)virt_to_page(addr);
60 sg->offset = offset_in_page(addr);
61 sg->length = len;
62 sg->dma_address = it;
63 }
64
65 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
66 {
67 if (!len)
68 return false;
69
70 if (e->bytes + len + 1 <= e->size)
71 return true;
72
73 if (e->bytes) {
74 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
75 e->iter += e->bytes;
76 e->buf = NULL;
77 e->bytes = 0;
78 }
79
80 if (e->cur == e->end) {
81 struct scatterlist *sgl;
82
83 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
84 if (!sgl) {
85 e->err = -ENOMEM;
86 return false;
87 }
88
89 if (e->cur) {
90 e->cur->offset = 0;
91 e->cur->length = 0;
92 e->cur->page_link =
93 (unsigned long)sgl | SG_CHAIN;
94 } else {
95 e->sgl = sgl;
96 }
97
98 e->cur = sgl;
99 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
100 }
101
102 e->size = ALIGN(len + 1, SZ_64K);
103 e->buf = kmalloc(e->size, ALLOW_FAIL);
104 if (!e->buf) {
105 e->size = PAGE_ALIGN(len + 1);
106 e->buf = kmalloc(e->size, GFP_KERNEL);
107 }
108 if (!e->buf) {
109 e->err = -ENOMEM;
110 return false;
111 }
112
113 return true;
114 }
115
116 __printf(2, 0)
117 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
118 const char *fmt, va_list args)
119 {
120 va_list ap;
121 int len;
122
123 if (e->err)
124 return;
125
126 va_copy(ap, args);
127 len = vsnprintf(NULL, 0, fmt, ap);
128 va_end(ap);
129 if (len <= 0) {
130 e->err = len;
131 return;
132 }
133
134 if (!__i915_error_grow(e, len))
135 return;
136
137 GEM_BUG_ON(e->bytes >= e->size);
138 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
139 if (len < 0) {
140 e->err = len;
141 return;
142 }
143 e->bytes += len;
144 }
145
146 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
147 {
148 unsigned len;
149
150 if (e->err || !str)
151 return;
152
153 len = strlen(str);
154 if (!__i915_error_grow(e, len))
155 return;
156
157 GEM_BUG_ON(e->bytes + len > e->size);
158 memcpy(e->buf + e->bytes, str, len);
159 e->bytes += len;
160 }
161
162 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
163 #define err_puts(e, s) i915_error_puts(e, s)
164
165 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
166 {
167 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
168 }
169
170 static inline struct drm_printer
171 i915_error_printer(struct drm_i915_error_state_buf *e)
172 {
173 struct drm_printer p = {
174 .printfn = __i915_printfn_error,
175 .arg = e,
176 };
177 return p;
178 }
179
180 /* single threaded page allocator with a reserved stash for emergencies */
181 static void pool_fini(struct pagevec *pv)
182 {
183 pagevec_release(pv);
184 }
185
186 static int pool_refill(struct pagevec *pv, gfp_t gfp)
187 {
188 while (pagevec_space(pv)) {
189 struct page *p;
190
191 p = alloc_page(gfp);
192 if (!p)
193 return -ENOMEM;
194
195 pagevec_add(pv, p);
196 }
197
198 return 0;
199 }
200
201 static int pool_init(struct pagevec *pv, gfp_t gfp)
202 {
203 int err;
204
205 pagevec_init(pv);
206
207 err = pool_refill(pv, gfp);
208 if (err)
209 pool_fini(pv);
210
211 return err;
212 }
213
214 static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
215 {
216 struct page *p;
217
218 p = alloc_page(gfp);
219 if (!p && pagevec_count(pv))
220 p = pv->pages[--pv->nr];
221
222 return p ? page_address(p) : NULL;
223 }
224
225 static void pool_free(struct pagevec *pv, void *addr)
226 {
227 struct page *p = virt_to_page(addr);
228
229 if (pagevec_space(pv))
230 pagevec_add(pv, p);
231 else
232 __free_page(p);
233 }
234
235 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
236
237 struct i915_vma_compress {
238 struct pagevec pool;
239 struct z_stream_s zstream;
240 void *tmp;
241 };
242
243 static bool compress_init(struct i915_vma_compress *c)
244 {
245 struct z_stream_s *zstream = &c->zstream;
246
247 if (pool_init(&c->pool, ALLOW_FAIL))
248 return false;
249
250 zstream->workspace =
251 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
252 ALLOW_FAIL);
253 if (!zstream->workspace) {
254 pool_fini(&c->pool);
255 return false;
256 }
257
258 c->tmp = NULL;
259 if (i915_has_memcpy_from_wc())
260 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
261
262 return true;
263 }
264
265 static bool compress_start(struct i915_vma_compress *c)
266 {
267 struct z_stream_s *zstream = &c->zstream;
268 void *workspace = zstream->workspace;
269
270 memset(zstream, 0, sizeof(*zstream));
271 zstream->workspace = workspace;
272
273 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
274 }
275
276 static void *compress_next_page(struct i915_vma_compress *c,
277 struct i915_vma_coredump *dst)
278 {
279 void *page;
280
281 if (dst->page_count >= dst->num_pages)
282 return ERR_PTR(-ENOSPC);
283
284 page = pool_alloc(&c->pool, ALLOW_FAIL);
285 if (!page)
286 return ERR_PTR(-ENOMEM);
287
288 return dst->pages[dst->page_count++] = page;
289 }
290
291 static int compress_page(struct i915_vma_compress *c,
292 void *src,
293 struct i915_vma_coredump *dst,
294 bool wc)
295 {
296 struct z_stream_s *zstream = &c->zstream;
297
298 zstream->next_in = src;
299 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
300 zstream->next_in = c->tmp;
301 zstream->avail_in = PAGE_SIZE;
302
303 do {
304 if (zstream->avail_out == 0) {
305 zstream->next_out = compress_next_page(c, dst);
306 if (IS_ERR(zstream->next_out))
307 return PTR_ERR(zstream->next_out);
308
309 zstream->avail_out = PAGE_SIZE;
310 }
311
312 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
313 return -EIO;
314
315 cond_resched();
316 } while (zstream->avail_in);
317
318 /* Fallback to uncompressed if we increase size? */
319 if (0 && zstream->total_out > zstream->total_in)
320 return -E2BIG;
321
322 return 0;
323 }
324
325 static int compress_flush(struct i915_vma_compress *c,
326 struct i915_vma_coredump *dst)
327 {
328 struct z_stream_s *zstream = &c->zstream;
329
330 do {
331 switch (zlib_deflate(zstream, Z_FINISH)) {
332 case Z_OK: /* more space requested */
333 zstream->next_out = compress_next_page(c, dst);
334 if (IS_ERR(zstream->next_out))
335 return PTR_ERR(zstream->next_out);
336
337 zstream->avail_out = PAGE_SIZE;
338 break;
339
340 case Z_STREAM_END:
341 goto end;
342
343 default: /* any error */
344 return -EIO;
345 }
346 } while (1);
347
348 end:
349 memset(zstream->next_out, 0, zstream->avail_out);
350 dst->unused = zstream->avail_out;
351 return 0;
352 }
353
354 static void compress_finish(struct i915_vma_compress *c)
355 {
356 zlib_deflateEnd(&c->zstream);
357 }
358
359 static void compress_fini(struct i915_vma_compress *c)
360 {
361 kfree(c->zstream.workspace);
362 if (c->tmp)
363 pool_free(&c->pool, c->tmp);
364 pool_fini(&c->pool);
365 }
366
367 static void err_compression_marker(struct drm_i915_error_state_buf *m)
368 {
369 err_puts(m, ":");
370 }
371
372 #else
373
374 struct i915_vma_compress {
375 struct pagevec pool;
376 };
377
378 static bool compress_init(struct i915_vma_compress *c)
379 {
380 return pool_init(&c->pool, ALLOW_FAIL) == 0;
381 }
382
383 static bool compress_start(struct i915_vma_compress *c)
384 {
385 return true;
386 }
387
388 static int compress_page(struct i915_vma_compress *c,
389 void *src,
390 struct i915_vma_coredump *dst,
391 bool wc)
392 {
393 void *ptr;
394
395 ptr = pool_alloc(&c->pool, ALLOW_FAIL);
396 if (!ptr)
397 return -ENOMEM;
398
399 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
400 memcpy(ptr, src, PAGE_SIZE);
401 dst->pages[dst->page_count++] = ptr;
402 cond_resched();
403
404 return 0;
405 }
406
407 static int compress_flush(struct i915_vma_compress *c,
408 struct i915_vma_coredump *dst)
409 {
410 return 0;
411 }
412
413 static void compress_finish(struct i915_vma_compress *c)
414 {
415 }
416
417 static void compress_fini(struct i915_vma_compress *c)
418 {
419 pool_fini(&c->pool);
420 }
421
422 static void err_compression_marker(struct drm_i915_error_state_buf *m)
423 {
424 err_puts(m, "~");
425 }
426
427 #endif
428
429 static void error_print_instdone(struct drm_i915_error_state_buf *m,
430 const struct intel_engine_coredump *ee)
431 {
432 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu;
433 int slice;
434 int subslice;
435
436 err_printf(m, " INSTDONE: 0x%08x\n",
437 ee->instdone.instdone);
438
439 if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3)
440 return;
441
442 err_printf(m, " SC_INSTDONE: 0x%08x\n",
443 ee->instdone.slice_common);
444
445 if (INTEL_GEN(m->i915) <= 6)
446 return;
447
448 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
449 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
450 slice, subslice,
451 ee->instdone.sampler[slice][subslice]);
452
453 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
454 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
455 slice, subslice,
456 ee->instdone.row[slice][subslice]);
457
458 if (INTEL_GEN(m->i915) < 12)
459 return;
460
461 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n",
462 ee->instdone.slice_common_extra[0]);
463 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n",
464 ee->instdone.slice_common_extra[1]);
465 }
466
467 static void error_print_request(struct drm_i915_error_state_buf *m,
468 const char *prefix,
469 const struct i915_request_coredump *erq)
470 {
471 if (!erq->seqno)
472 return;
473
474 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n",
475 prefix, erq->pid, erq->context, erq->seqno,
476 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
477 &erq->flags) ? "!" : "",
478 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
479 &erq->flags) ? "+" : "",
480 erq->sched_attr.priority,
481 erq->head, erq->tail);
482 }
483
484 static void error_print_context(struct drm_i915_error_state_buf *m,
485 const char *header,
486 const struct i915_gem_context_coredump *ctx)
487 {
488 const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns;
489
490 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n",
491 header, ctx->comm, ctx->pid, ctx->sched_attr.priority,
492 ctx->guilty, ctx->active,
493 ctx->total_runtime * period,
494 mul_u32_u32(ctx->avg_runtime, period));
495 }
496
497 static struct i915_vma_coredump *
498 __find_vma(struct i915_vma_coredump *vma, const char *name)
499 {
500 while (vma) {
501 if (strcmp(vma->name, name) == 0)
502 return vma;
503 vma = vma->next;
504 }
505
506 return NULL;
507 }
508
509 static struct i915_vma_coredump *
510 find_batch(const struct intel_engine_coredump *ee)
511 {
512 return __find_vma(ee->vma, "batch");
513 }
514
515 static void error_print_engine(struct drm_i915_error_state_buf *m,
516 const struct intel_engine_coredump *ee)
517 {
518 struct i915_vma_coredump *batch;
519 int n;
520
521 err_printf(m, "%s command stream:\n", ee->engine->name);
522 err_printf(m, " CCID: 0x%08x\n", ee->ccid);
523 err_printf(m, " START: 0x%08x\n", ee->start);
524 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
525 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",
526 ee->tail, ee->rq_post, ee->rq_tail);
527 err_printf(m, " CTL: 0x%08x\n", ee->ctl);
528 err_printf(m, " MODE: 0x%08x\n", ee->mode);
529 err_printf(m, " HWS: 0x%08x\n", ee->hws);
530 err_printf(m, " ACTHD: 0x%08x %08x\n",
531 (u32)(ee->acthd>>32), (u32)ee->acthd);
532 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
533 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
534 err_printf(m, " ESR: 0x%08x\n", ee->esr);
535
536 error_print_instdone(m, ee);
537
538 batch = find_batch(ee);
539 if (batch) {
540 u64 start = batch->gtt_offset;
541 u64 end = start + batch->gtt_size;
542
543 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",
544 upper_32_bits(start), lower_32_bits(start),
545 upper_32_bits(end), lower_32_bits(end));
546 }
547 if (INTEL_GEN(m->i915) >= 4) {
548 err_printf(m, " BBADDR: 0x%08x_%08x\n",
549 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
550 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
551 err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
552 }
553 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
554 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
555 lower_32_bits(ee->faddr));
556 if (INTEL_GEN(m->i915) >= 6) {
557 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
558 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
559 }
560 if (HAS_PPGTT(m->i915)) {
561 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
562
563 if (INTEL_GEN(m->i915) >= 8) {
564 int i;
565 for (i = 0; i < 4; i++)
566 err_printf(m, " PDP%d: 0x%016llx\n",
567 i, ee->vm_info.pdp[i]);
568 } else {
569 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
570 ee->vm_info.pp_dir_base);
571 }
572 }
573 err_printf(m, " engine reset count: %u\n", ee->reset_count);
574
575 for (n = 0; n < ee->num_ports; n++) {
576 err_printf(m, " ELSP[%d]:", n);
577 error_print_request(m, " ", &ee->execlist[n]);
578 }
579
580 error_print_context(m, " Active context: ", &ee->context);
581 }
582
583 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
584 {
585 va_list args;
586
587 va_start(args, f);
588 i915_error_vprintf(e, f, args);
589 va_end(args);
590 }
591
592 static void print_error_vma(struct drm_i915_error_state_buf *m,
593 const struct intel_engine_cs *engine,
594 const struct i915_vma_coredump *vma)
595 {
596 char out[ASCII85_BUFSZ];
597 int page;
598
599 if (!vma)
600 return;
601
602 err_printf(m, "%s --- %s = 0x%08x %08x\n",
603 engine ? engine->name : "global", vma->name,
604 upper_32_bits(vma->gtt_offset),
605 lower_32_bits(vma->gtt_offset));
606
607 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)
608 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);
609
610 err_compression_marker(m);
611 for (page = 0; page < vma->page_count; page++) {
612 int i, len;
613
614 len = PAGE_SIZE;
615 if (page == vma->page_count - 1)
616 len -= vma->unused;
617 len = ascii85_encode_len(len);
618
619 for (i = 0; i < len; i++)
620 err_puts(m, ascii85_encode(vma->pages[page][i], out));
621 }
622 err_puts(m, "\n");
623 }
624
625 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
626 struct i915_gpu_coredump *error)
627 {
628 struct drm_printer p = i915_error_printer(m);
629
630 intel_device_info_print_static(&error->device_info, &p);
631 intel_device_info_print_runtime(&error->runtime_info, &p);
632 intel_driver_caps_print(&error->driver_caps, &p);
633 }
634
635 static void err_print_params(struct drm_i915_error_state_buf *m,
636 const struct i915_params *params)
637 {
638 struct drm_printer p = i915_error_printer(m);
639
640 i915_params_dump(params, &p);
641 }
642
643 static void err_print_pciid(struct drm_i915_error_state_buf *m,
644 struct drm_i915_private *i915)
645 {
646 struct pci_dev *pdev = i915->drm.pdev;
647
648 err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
649 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
650 err_printf(m, "PCI Subsystem: %04x:%04x\n",
651 pdev->subsystem_vendor,
652 pdev->subsystem_device);
653 }
654
655 static void err_print_uc(struct drm_i915_error_state_buf *m,
656 const struct intel_uc_coredump *error_uc)
657 {
658 struct drm_printer p = i915_error_printer(m);
659
660 intel_uc_fw_dump(&error_uc->guc_fw, &p);
661 intel_uc_fw_dump(&error_uc->huc_fw, &p);
662 print_error_vma(m, NULL, error_uc->guc_log);
663 }
664
665 static void err_free_sgl(struct scatterlist *sgl)
666 {
667 while (sgl) {
668 struct scatterlist *sg;
669
670 for (sg = sgl; !sg_is_chain(sg); sg++) {
671 kfree(sg_virt(sg));
672 if (sg_is_last(sg))
673 break;
674 }
675
676 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
677 free_page((unsigned long)sgl);
678 sgl = sg;
679 }
680 }
681
682 static void err_print_gt_info(struct drm_i915_error_state_buf *m,
683 struct intel_gt_coredump *gt)
684 {
685 struct drm_printer p = i915_error_printer(m);
686
687 intel_gt_info_print(&gt->info, &p);
688 intel_sseu_print_topology(&gt->info.sseu, &p);
689 }
690
691 static void err_print_gt(struct drm_i915_error_state_buf *m,
692 struct intel_gt_coredump *gt)
693 {
694 const struct intel_engine_coredump *ee;
695 int i;
696
697 err_printf(m, "GT awake: %s\n", yesno(gt->awake));
698 err_printf(m, "EIR: 0x%08x\n", gt->eir);
699 err_printf(m, "IER: 0x%08x\n", gt->ier);
700 for (i = 0; i < gt->ngtier; i++)
701 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
702 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
703 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
704 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
705
706 for (i = 0; i < gt->nfence; i++)
707 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]);
708
709 if (IS_GEN_RANGE(m->i915, 6, 11)) {
710 err_printf(m, "ERROR: 0x%08x\n", gt->error);
711 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
712 }
713
714 if (INTEL_GEN(m->i915) >= 8)
715 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
716 gt->fault_data1, gt->fault_data0);
717
718 if (IS_GEN(m->i915, 7))
719 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
720
721 if (IS_GEN_RANGE(m->i915, 8, 11))
722 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
723
724 if (IS_GEN(m->i915, 12))
725 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
726
727 if (INTEL_GEN(m->i915) >= 12) {
728 int i;
729
730 for (i = 0; i < GEN12_SFC_DONE_MAX; i++)
731 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i,
732 gt->sfc_done[i]);
733
734 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done);
735 }
736
737 for (ee = gt->engine; ee; ee = ee->next) {
738 const struct i915_vma_coredump *vma;
739
740 error_print_engine(m, ee);
741 for (vma = ee->vma; vma; vma = vma->next)
742 print_error_vma(m, ee->engine, vma);
743 }
744
745 if (gt->uc)
746 err_print_uc(m, gt->uc);
747
748 err_print_gt_info(m, gt);
749 }
750
751 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
752 struct i915_gpu_coredump *error)
753 {
754 const struct intel_engine_coredump *ee;
755 struct timespec64 ts;
756
757 if (*error->error_msg)
758 err_printf(m, "%s\n", error->error_msg);
759 err_printf(m, "Kernel: %s %s\n",
760 init_utsname()->release,
761 init_utsname()->machine);
762 err_printf(m, "Driver: %s\n", DRIVER_DATE);
763 ts = ktime_to_timespec64(error->time);
764 err_printf(m, "Time: %lld s %ld us\n",
765 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
766 ts = ktime_to_timespec64(error->boottime);
767 err_printf(m, "Boottime: %lld s %ld us\n",
768 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
769 ts = ktime_to_timespec64(error->uptime);
770 err_printf(m, "Uptime: %lld s %ld us\n",
771 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
772 err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
773 error->capture, jiffies_to_msecs(jiffies - error->capture));
774
775 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
776 err_printf(m, "Active process (on ring %s): %s [%d]\n",
777 ee->engine->name,
778 ee->context.comm,
779 ee->context.pid);
780
781 err_printf(m, "Reset count: %u\n", error->reset_count);
782 err_printf(m, "Suspend count: %u\n", error->suspend_count);
783 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
784 err_printf(m, "Subplatform: 0x%x\n",
785 intel_subplatform(&error->runtime_info,
786 error->device_info.platform));
787 err_print_pciid(m, m->i915);
788
789 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
790
791 if (HAS_CSR(m->i915)) {
792 struct intel_csr *csr = &m->i915->csr;
793
794 err_printf(m, "DMC loaded: %s\n",
795 yesno(csr->dmc_payload != NULL));
796 err_printf(m, "DMC fw version: %d.%d\n",
797 CSR_VERSION_MAJOR(csr->version),
798 CSR_VERSION_MINOR(csr->version));
799 }
800
801 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
802 err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
803
804 if (error->gt)
805 err_print_gt(m, error->gt);
806
807 if (error->overlay)
808 intel_overlay_print_error_state(m, error->overlay);
809
810 if (error->display)
811 intel_display_print_error_state(m, error->display);
812
813 err_print_capabilities(m, error);
814 err_print_params(m, &error->params);
815 }
816
817 static int err_print_to_sgl(struct i915_gpu_coredump *error)
818 {
819 struct drm_i915_error_state_buf m;
820
821 if (IS_ERR(error))
822 return PTR_ERR(error);
823
824 if (READ_ONCE(error->sgl))
825 return 0;
826
827 memset(&m, 0, sizeof(m));
828 m.i915 = error->i915;
829
830 __err_print_to_sgl(&m, error);
831
832 if (m.buf) {
833 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
834 m.bytes = 0;
835 m.buf = NULL;
836 }
837 if (m.cur) {
838 GEM_BUG_ON(m.end < m.cur);
839 sg_mark_end(m.cur - 1);
840 }
841 GEM_BUG_ON(m.sgl && !m.cur);
842
843 if (m.err) {
844 err_free_sgl(m.sgl);
845 return m.err;
846 }
847
848 if (cmpxchg(&error->sgl, NULL, m.sgl))
849 err_free_sgl(m.sgl);
850
851 return 0;
852 }
853
854 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
855 char *buf, loff_t off, size_t rem)
856 {
857 struct scatterlist *sg;
858 size_t count;
859 loff_t pos;
860 int err;
861
862 if (!error || !rem)
863 return 0;
864
865 err = err_print_to_sgl(error);
866 if (err)
867 return err;
868
869 sg = READ_ONCE(error->fit);
870 if (!sg || off < sg->dma_address)
871 sg = error->sgl;
872 if (!sg)
873 return 0;
874
875 pos = sg->dma_address;
876 count = 0;
877 do {
878 size_t len, start;
879
880 if (sg_is_chain(sg)) {
881 sg = sg_chain_ptr(sg);
882 GEM_BUG_ON(sg_is_chain(sg));
883 }
884
885 len = sg->length;
886 if (pos + len <= off) {
887 pos += len;
888 continue;
889 }
890
891 start = sg->offset;
892 if (pos < off) {
893 GEM_BUG_ON(off - pos > len);
894 len -= off - pos;
895 start += off - pos;
896 pos = off;
897 }
898
899 len = min(len, rem);
900 GEM_BUG_ON(!len || len > sg->length);
901
902 memcpy(buf, page_address(sg_page(sg)) + start, len);
903
904 count += len;
905 pos += len;
906
907 buf += len;
908 rem -= len;
909 if (!rem) {
910 WRITE_ONCE(error->fit, sg);
911 break;
912 }
913 } while (!sg_is_last(sg++));
914
915 return count;
916 }
917
918 static void i915_vma_coredump_free(struct i915_vma_coredump *vma)
919 {
920 while (vma) {
921 struct i915_vma_coredump *next = vma->next;
922 int page;
923
924 for (page = 0; page < vma->page_count; page++)
925 free_page((unsigned long)vma->pages[page]);
926
927 kfree(vma);
928 vma = next;
929 }
930 }
931
932 static void cleanup_params(struct i915_gpu_coredump *error)
933 {
934 i915_params_free(&error->params);
935 }
936
937 static void cleanup_uc(struct intel_uc_coredump *uc)
938 {
939 kfree(uc->guc_fw.path);
940 kfree(uc->huc_fw.path);
941 i915_vma_coredump_free(uc->guc_log);
942
943 kfree(uc);
944 }
945
946 static void cleanup_gt(struct intel_gt_coredump *gt)
947 {
948 while (gt->engine) {
949 struct intel_engine_coredump *ee = gt->engine;
950
951 gt->engine = ee->next;
952
953 i915_vma_coredump_free(ee->vma);
954 kfree(ee);
955 }
956
957 if (gt->uc)
958 cleanup_uc(gt->uc);
959
960 kfree(gt);
961 }
962
963 void __i915_gpu_coredump_free(struct kref *error_ref)
964 {
965 struct i915_gpu_coredump *error =
966 container_of(error_ref, typeof(*error), ref);
967
968 while (error->gt) {
969 struct intel_gt_coredump *gt = error->gt;
970
971 error->gt = gt->next;
972 cleanup_gt(gt);
973 }
974
975 kfree(error->overlay);
976 kfree(error->display);
977
978 cleanup_params(error);
979
980 err_free_sgl(error->sgl);
981 kfree(error);
982 }
983
984 static struct i915_vma_coredump *
985 i915_vma_coredump_create(const struct intel_gt *gt,
986 const struct i915_vma *vma,
987 const char *name,
988 struct i915_vma_compress *compress)
989 {
990 struct i915_ggtt *ggtt = gt->ggtt;
991 const u64 slot = ggtt->error_capture.start;
992 struct i915_vma_coredump *dst;
993 unsigned long num_pages;
994 struct sgt_iter iter;
995 int ret;
996
997 might_sleep();
998
999 if (!vma || !vma->pages || !compress)
1000 return NULL;
1001
1002 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
1003 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
1004 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL);
1005 if (!dst)
1006 return NULL;
1007
1008 if (!compress_start(compress)) {
1009 kfree(dst);
1010 return NULL;
1011 }
1012
1013 strcpy(dst->name, name);
1014 dst->next = NULL;
1015
1016 dst->gtt_offset = vma->node.start;
1017 dst->gtt_size = vma->node.size;
1018 dst->gtt_page_sizes = vma->page_sizes.gtt;
1019 dst->num_pages = num_pages;
1020 dst->page_count = 0;
1021 dst->unused = 0;
1022
1023 ret = -EINVAL;
1024 if (drm_mm_node_allocated(&ggtt->error_capture)) {
1025 void __iomem *s;
1026 dma_addr_t dma;
1027
1028 for_each_sgt_daddr(dma, iter, vma->pages) {
1029 ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1030 I915_CACHE_NONE, 0);
1031 mb();
1032
1033 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
1034 ret = compress_page(compress,
1035 (void __force *)s, dst,
1036 true);
1037 io_mapping_unmap(s);
1038 if (ret)
1039 break;
1040 }
1041 } else if (i915_gem_object_is_lmem(vma->obj)) {
1042 struct intel_memory_region *mem = vma->obj->mm.region;
1043 dma_addr_t dma;
1044
1045 for_each_sgt_daddr(dma, iter, vma->pages) {
1046 void __iomem *s;
1047
1048 s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE);
1049 ret = compress_page(compress,
1050 (void __force *)s, dst,
1051 true);
1052 io_mapping_unmap(s);
1053 if (ret)
1054 break;
1055 }
1056 } else {
1057 struct page *page;
1058
1059 for_each_sgt_page(page, iter, vma->pages) {
1060 void *s;
1061
1062 drm_clflush_pages(&page, 1);
1063
1064 s = kmap(page);
1065 ret = compress_page(compress, s, dst, false);
1066 kunmap(page);
1067
1068 drm_clflush_pages(&page, 1);
1069
1070 if (ret)
1071 break;
1072 }
1073 }
1074
1075 if (ret || compress_flush(compress, dst)) {
1076 while (dst->page_count--)
1077 pool_free(&compress->pool, dst->pages[dst->page_count]);
1078 kfree(dst);
1079 dst = NULL;
1080 }
1081 compress_finish(compress);
1082
1083 return dst;
1084 }
1085
1086 static void gt_record_fences(struct intel_gt_coredump *gt)
1087 {
1088 struct i915_ggtt *ggtt = gt->_gt->ggtt;
1089 struct intel_uncore *uncore = gt->_gt->uncore;
1090 int i;
1091
1092 if (INTEL_GEN(uncore->i915) >= 6) {
1093 for (i = 0; i < ggtt->num_fences; i++)
1094 gt->fence[i] =
1095 intel_uncore_read64(uncore,
1096 FENCE_REG_GEN6_LO(i));
1097 } else if (INTEL_GEN(uncore->i915) >= 4) {
1098 for (i = 0; i < ggtt->num_fences; i++)
1099 gt->fence[i] =
1100 intel_uncore_read64(uncore,
1101 FENCE_REG_965_LO(i));
1102 } else {
1103 for (i = 0; i < ggtt->num_fences; i++)
1104 gt->fence[i] =
1105 intel_uncore_read(uncore, FENCE_REG(i));
1106 }
1107 gt->nfence = i;
1108 }
1109
1110 static void engine_record_registers(struct intel_engine_coredump *ee)
1111 {
1112 const struct intel_engine_cs *engine = ee->engine;
1113 struct drm_i915_private *i915 = engine->i915;
1114
1115 if (INTEL_GEN(i915) >= 6) {
1116 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1117
1118 if (INTEL_GEN(i915) >= 12)
1119 ee->fault_reg = intel_uncore_read(engine->uncore,
1120 GEN12_RING_FAULT_REG);
1121 else if (INTEL_GEN(i915) >= 8)
1122 ee->fault_reg = intel_uncore_read(engine->uncore,
1123 GEN8_RING_FAULT_REG);
1124 else
1125 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1126 }
1127
1128 if (INTEL_GEN(i915) >= 4) {
1129 ee->esr = ENGINE_READ(engine, RING_ESR);
1130 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1131 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1132 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1133 ee->instps = ENGINE_READ(engine, RING_INSTPS);
1134 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1135 ee->ccid = ENGINE_READ(engine, CCID);
1136 if (INTEL_GEN(i915) >= 8) {
1137 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1138 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1139 }
1140 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1141 } else {
1142 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1143 ee->ipeir = ENGINE_READ(engine, IPEIR);
1144 ee->ipehr = ENGINE_READ(engine, IPEHR);
1145 }
1146
1147 intel_engine_get_instdone(engine, &ee->instdone);
1148
1149 ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1150 ee->acthd = intel_engine_get_active_head(engine);
1151 ee->start = ENGINE_READ(engine, RING_START);
1152 ee->head = ENGINE_READ(engine, RING_HEAD);
1153 ee->tail = ENGINE_READ(engine, RING_TAIL);
1154 ee->ctl = ENGINE_READ(engine, RING_CTL);
1155 if (INTEL_GEN(i915) > 2)
1156 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1157
1158 if (!HWS_NEEDS_PHYSICAL(i915)) {
1159 i915_reg_t mmio;
1160
1161 if (IS_GEN(i915, 7)) {
1162 switch (engine->id) {
1163 default:
1164 MISSING_CASE(engine->id);
1165 fallthrough;
1166 case RCS0:
1167 mmio = RENDER_HWS_PGA_GEN7;
1168 break;
1169 case BCS0:
1170 mmio = BLT_HWS_PGA_GEN7;
1171 break;
1172 case VCS0:
1173 mmio = BSD_HWS_PGA_GEN7;
1174 break;
1175 case VECS0:
1176 mmio = VEBOX_HWS_PGA_GEN7;
1177 break;
1178 }
1179 } else if (IS_GEN(engine->i915, 6)) {
1180 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1181 } else {
1182 /* XXX: gen8 returns to sanity */
1183 mmio = RING_HWS_PGA(engine->mmio_base);
1184 }
1185
1186 ee->hws = intel_uncore_read(engine->uncore, mmio);
1187 }
1188
1189 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);
1190
1191 if (HAS_PPGTT(i915)) {
1192 int i;
1193
1194 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1195
1196 if (IS_GEN(i915, 6)) {
1197 ee->vm_info.pp_dir_base =
1198 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1199 } else if (IS_GEN(i915, 7)) {
1200 ee->vm_info.pp_dir_base =
1201 ENGINE_READ(engine, RING_PP_DIR_BASE);
1202 } else if (INTEL_GEN(i915) >= 8) {
1203 u32 base = engine->mmio_base;
1204
1205 for (i = 0; i < 4; i++) {
1206 ee->vm_info.pdp[i] =
1207 intel_uncore_read(engine->uncore,
1208 GEN8_RING_PDP_UDW(base, i));
1209 ee->vm_info.pdp[i] <<= 32;
1210 ee->vm_info.pdp[i] |=
1211 intel_uncore_read(engine->uncore,
1212 GEN8_RING_PDP_LDW(base, i));
1213 }
1214 }
1215 }
1216 }
1217
1218 static void record_request(const struct i915_request *request,
1219 struct i915_request_coredump *erq)
1220 {
1221 erq->flags = request->fence.flags;
1222 erq->context = request->fence.context;
1223 erq->seqno = request->fence.seqno;
1224 erq->sched_attr = request->sched.attr;
1225 erq->head = request->head;
1226 erq->tail = request->tail;
1227
1228 erq->pid = 0;
1229 rcu_read_lock();
1230 if (!intel_context_is_closed(request->context)) {
1231 const struct i915_gem_context *ctx;
1232
1233 ctx = rcu_dereference(request->context->gem_context);
1234 if (ctx)
1235 erq->pid = pid_nr(ctx->pid);
1236 }
1237 rcu_read_unlock();
1238 }
1239
1240 static void engine_record_execlists(struct intel_engine_coredump *ee)
1241 {
1242 const struct intel_engine_execlists * const el = &ee->engine->execlists;
1243 struct i915_request * const *port = el->active;
1244 unsigned int n = 0;
1245
1246 while (*port)
1247 record_request(*port++, &ee->execlist[n++]);
1248
1249 ee->num_ports = n;
1250 }
1251
1252 static bool record_context(struct i915_gem_context_coredump *e,
1253 const struct i915_request *rq)
1254 {
1255 struct i915_gem_context *ctx;
1256 struct task_struct *task;
1257 bool simulated;
1258
1259 rcu_read_lock();
1260 ctx = rcu_dereference(rq->context->gem_context);
1261 if (ctx && !kref_get_unless_zero(&ctx->ref))
1262 ctx = NULL;
1263 rcu_read_unlock();
1264 if (!ctx)
1265 return true;
1266
1267 rcu_read_lock();
1268 task = pid_task(ctx->pid, PIDTYPE_PID);
1269 if (task) {
1270 strcpy(e->comm, task->comm);
1271 e->pid = task->pid;
1272 }
1273 rcu_read_unlock();
1274
1275 e->sched_attr = ctx->sched;
1276 e->guilty = atomic_read(&ctx->guilty_count);
1277 e->active = atomic_read(&ctx->active_count);
1278
1279 e->total_runtime = rq->context->runtime.total;
1280 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg);
1281
1282 simulated = i915_gem_context_no_error_capture(ctx);
1283
1284 i915_gem_context_put(ctx);
1285 return simulated;
1286 }
1287
1288 struct intel_engine_capture_vma {
1289 struct intel_engine_capture_vma *next;
1290 struct i915_vma *vma;
1291 char name[16];
1292 };
1293
1294 static struct intel_engine_capture_vma *
1295 capture_vma(struct intel_engine_capture_vma *next,
1296 struct i915_vma *vma,
1297 const char *name,
1298 gfp_t gfp)
1299 {
1300 struct intel_engine_capture_vma *c;
1301
1302 if (!vma)
1303 return next;
1304
1305 c = kmalloc(sizeof(*c), gfp);
1306 if (!c)
1307 return next;
1308
1309 if (!i915_active_acquire_if_busy(&vma->active)) {
1310 kfree(c);
1311 return next;
1312 }
1313
1314 strcpy(c->name, name);
1315 c->vma = vma; /* reference held while active */
1316
1317 c->next = next;
1318 return c;
1319 }
1320
1321 static struct intel_engine_capture_vma *
1322 capture_user(struct intel_engine_capture_vma *capture,
1323 const struct i915_request *rq,
1324 gfp_t gfp)
1325 {
1326 struct i915_capture_list *c;
1327
1328 for (c = rq->capture_list; c; c = c->next)
1329 capture = capture_vma(capture, c->vma, "user", gfp);
1330
1331 return capture;
1332 }
1333
1334 static void add_vma(struct intel_engine_coredump *ee,
1335 struct i915_vma_coredump *vma)
1336 {
1337 if (vma) {
1338 vma->next = ee->vma;
1339 ee->vma = vma;
1340 }
1341 }
1342
1343 struct intel_engine_coredump *
1344 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
1345 {
1346 struct intel_engine_coredump *ee;
1347
1348 ee = kzalloc(sizeof(*ee), gfp);
1349 if (!ee)
1350 return NULL;
1351
1352 ee->engine = engine;
1353
1354 engine_record_registers(ee);
1355 engine_record_execlists(ee);
1356
1357 return ee;
1358 }
1359
1360 struct intel_engine_capture_vma *
1361 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
1362 struct i915_request *rq,
1363 gfp_t gfp)
1364 {
1365 struct intel_engine_capture_vma *vma = NULL;
1366
1367 ee->simulated |= record_context(&ee->context, rq);
1368 if (ee->simulated)
1369 return NULL;
1370
1371 /*
1372 * We need to copy these to an anonymous buffer
1373 * as the simplest method to avoid being overwritten
1374 * by userspace.
1375 */
1376 vma = capture_vma(vma, rq->batch, "batch", gfp);
1377 vma = capture_user(vma, rq, gfp);
1378 vma = capture_vma(vma, rq->ring->vma, "ring", gfp);
1379 vma = capture_vma(vma, rq->context->state, "HW context", gfp);
1380
1381 ee->rq_head = rq->head;
1382 ee->rq_post = rq->postfix;
1383 ee->rq_tail = rq->tail;
1384
1385 return vma;
1386 }
1387
1388 void
1389 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
1390 struct intel_engine_capture_vma *capture,
1391 struct i915_vma_compress *compress)
1392 {
1393 const struct intel_engine_cs *engine = ee->engine;
1394
1395 while (capture) {
1396 struct intel_engine_capture_vma *this = capture;
1397 struct i915_vma *vma = this->vma;
1398
1399 add_vma(ee,
1400 i915_vma_coredump_create(engine->gt,
1401 vma, this->name,
1402 compress));
1403
1404 i915_active_release(&vma->active);
1405
1406 capture = this->next;
1407 kfree(this);
1408 }
1409
1410 add_vma(ee,
1411 i915_vma_coredump_create(engine->gt,
1412 engine->status_page.vma,
1413 "HW Status",
1414 compress));
1415
1416 add_vma(ee,
1417 i915_vma_coredump_create(engine->gt,
1418 engine->wa_ctx.vma,
1419 "WA context",
1420 compress));
1421 }
1422
1423 static struct intel_engine_coredump *
1424 capture_engine(struct intel_engine_cs *engine,
1425 struct i915_vma_compress *compress)
1426 {
1427 struct intel_engine_capture_vma *capture = NULL;
1428 struct intel_engine_coredump *ee;
1429 struct i915_request *rq;
1430 unsigned long flags;
1431
1432 ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
1433 if (!ee)
1434 return NULL;
1435
1436 spin_lock_irqsave(&engine->active.lock, flags);
1437 rq = intel_engine_find_active_request(engine);
1438 if (rq)
1439 capture = intel_engine_coredump_add_request(ee, rq,
1440 ATOMIC_MAYFAIL);
1441 spin_unlock_irqrestore(&engine->active.lock, flags);
1442 if (!capture) {
1443 kfree(ee);
1444 return NULL;
1445 }
1446
1447 intel_engine_coredump_add_vma(ee, capture, compress);
1448
1449 return ee;
1450 }
1451
1452 static void
1453 gt_record_engines(struct intel_gt_coredump *gt,
1454 struct i915_vma_compress *compress)
1455 {
1456 struct intel_engine_cs *engine;
1457 enum intel_engine_id id;
1458
1459 for_each_engine(engine, gt->_gt, id) {
1460 struct intel_engine_coredump *ee;
1461
1462 /* Refill our page pool before entering atomic section */
1463 pool_refill(&compress->pool, ALLOW_FAIL);
1464
1465 ee = capture_engine(engine, compress);
1466 if (!ee)
1467 continue;
1468
1469 gt->simulated |= ee->simulated;
1470 if (ee->simulated) {
1471 kfree(ee);
1472 continue;
1473 }
1474
1475 ee->next = gt->engine;
1476 gt->engine = ee;
1477 }
1478 }
1479
1480 static struct intel_uc_coredump *
1481 gt_record_uc(struct intel_gt_coredump *gt,
1482 struct i915_vma_compress *compress)
1483 {
1484 const struct intel_uc *uc = &gt->_gt->uc;
1485 struct intel_uc_coredump *error_uc;
1486
1487 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);
1488 if (!error_uc)
1489 return NULL;
1490
1491 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1492 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1493
1494 /* Non-default firmware paths will be specified by the modparam.
1495 * As modparams are generally accesible from the userspace make
1496 * explicit copies of the firmware paths.
1497 */
1498 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
1499 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL);
1500 error_uc->guc_log =
1501 i915_vma_coredump_create(gt->_gt,
1502 uc->guc.log.vma, "GuC log buffer",
1503 compress);
1504
1505 return error_uc;
1506 }
1507
1508 static void gt_capture_prepare(struct intel_gt_coredump *gt)
1509 {
1510 struct i915_ggtt *ggtt = gt->_gt->ggtt;
1511
1512 mutex_lock(&ggtt->error_mutex);
1513 }
1514
1515 static void gt_capture_finish(struct intel_gt_coredump *gt)
1516 {
1517 struct i915_ggtt *ggtt = gt->_gt->ggtt;
1518
1519 if (drm_mm_node_allocated(&ggtt->error_capture))
1520 ggtt->vm.clear_range(&ggtt->vm,
1521 ggtt->error_capture.start,
1522 PAGE_SIZE);
1523
1524 mutex_unlock(&ggtt->error_mutex);
1525 }
1526
1527 /* Capture all registers which don't fit into another category. */
1528 static void gt_record_regs(struct intel_gt_coredump *gt)
1529 {
1530 struct intel_uncore *uncore = gt->_gt->uncore;
1531 struct drm_i915_private *i915 = uncore->i915;
1532 int i;
1533
1534 /*
1535 * General organization
1536 * 1. Registers specific to a single generation
1537 * 2. Registers which belong to multiple generations
1538 * 3. Feature specific registers.
1539 * 4. Everything else
1540 * Please try to follow the order.
1541 */
1542
1543 /* 1: Registers specific to a single generation */
1544 if (IS_VALLEYVIEW(i915)) {
1545 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1546 gt->ier = intel_uncore_read(uncore, VLV_IER);
1547 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1548 }
1549
1550 if (IS_GEN(i915, 7))
1551 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1552
1553 if (INTEL_GEN(i915) >= 12) {
1554 gt->fault_data0 = intel_uncore_read(uncore,
1555 GEN12_FAULT_TLB_DATA0);
1556 gt->fault_data1 = intel_uncore_read(uncore,
1557 GEN12_FAULT_TLB_DATA1);
1558 } else if (INTEL_GEN(i915) >= 8) {
1559 gt->fault_data0 = intel_uncore_read(uncore,
1560 GEN8_FAULT_TLB_DATA0);
1561 gt->fault_data1 = intel_uncore_read(uncore,
1562 GEN8_FAULT_TLB_DATA1);
1563 }
1564
1565 if (IS_GEN(i915, 6)) {
1566 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1567 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1568 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1569 }
1570
1571 /* 2: Registers which belong to multiple generations */
1572 if (INTEL_GEN(i915) >= 7)
1573 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1574
1575 if (INTEL_GEN(i915) >= 6) {
1576 gt->derrmr = intel_uncore_read(uncore, DERRMR);
1577 if (INTEL_GEN(i915) < 12) {
1578 gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1579 gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1580 }
1581 }
1582
1583 /* 3: Feature specific registers */
1584 if (IS_GEN_RANGE(i915, 6, 7)) {
1585 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1586 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1587 }
1588
1589 if (IS_GEN_RANGE(i915, 8, 11))
1590 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1591
1592 if (IS_GEN(i915, 12))
1593 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1594
1595 if (INTEL_GEN(i915) >= 12) {
1596 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
1597 gt->sfc_done[i] =
1598 intel_uncore_read(uncore, GEN12_SFC_DONE(i));
1599 }
1600
1601 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1602 }
1603
1604 /* 4: Everything else */
1605 if (INTEL_GEN(i915) >= 11) {
1606 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1607 gt->gtier[0] =
1608 intel_uncore_read(uncore,
1609 GEN11_RENDER_COPY_INTR_ENABLE);
1610 gt->gtier[1] =
1611 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1612 gt->gtier[2] =
1613 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1614 gt->gtier[3] =
1615 intel_uncore_read(uncore,
1616 GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1617 gt->gtier[4] =
1618 intel_uncore_read(uncore,
1619 GEN11_CRYPTO_RSVD_INTR_ENABLE);
1620 gt->gtier[5] =
1621 intel_uncore_read(uncore,
1622 GEN11_GUNIT_CSME_INTR_ENABLE);
1623 gt->ngtier = 6;
1624 } else if (INTEL_GEN(i915) >= 8) {
1625 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1626 for (i = 0; i < 4; i++)
1627 gt->gtier[i] =
1628 intel_uncore_read(uncore, GEN8_GT_IER(i));
1629 gt->ngtier = 4;
1630 } else if (HAS_PCH_SPLIT(i915)) {
1631 gt->ier = intel_uncore_read(uncore, DEIER);
1632 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1633 gt->ngtier = 1;
1634 } else if (IS_GEN(i915, 2)) {
1635 gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1636 } else if (!IS_VALLEYVIEW(i915)) {
1637 gt->ier = intel_uncore_read(uncore, GEN2_IER);
1638 }
1639 gt->eir = intel_uncore_read(uncore, EIR);
1640 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1641 }
1642
1643 static void gt_record_info(struct intel_gt_coredump *gt)
1644 {
1645 memcpy(&gt->info, &gt->_gt->info, sizeof(struct intel_gt_info));
1646 }
1647
1648 /*
1649 * Generate a semi-unique error code. The code is not meant to have meaning, The
1650 * code's only purpose is to try to prevent false duplicated bug reports by
1651 * grossly estimating a GPU error state.
1652 *
1653 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1654 * the hang if we could strip the GTT offset information from it.
1655 *
1656 * It's only a small step better than a random number in its current form.
1657 */
1658 static u32 generate_ecode(const struct intel_engine_coredump *ee)
1659 {
1660 /*
1661 * IPEHR would be an ideal way to detect errors, as it's the gross
1662 * measure of "the command that hung." However, has some very common
1663 * synchronization commands which almost always appear in the case
1664 * strictly a client bug. Use instdone to differentiate those some.
1665 */
1666 return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1667 }
1668
1669 static const char *error_msg(struct i915_gpu_coredump *error)
1670 {
1671 struct intel_engine_coredump *first = NULL;
1672 struct intel_gt_coredump *gt;
1673 intel_engine_mask_t engines;
1674 int len;
1675
1676 engines = 0;
1677 for (gt = error->gt; gt; gt = gt->next) {
1678 struct intel_engine_coredump *cs;
1679
1680 if (gt->engine && !first)
1681 first = gt->engine;
1682
1683 for (cs = gt->engine; cs; cs = cs->next)
1684 engines |= cs->engine->mask;
1685 }
1686
1687 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1688 "GPU HANG: ecode %d:%x:%08x",
1689 INTEL_GEN(error->i915), engines,
1690 generate_ecode(first));
1691 if (first && first->context.pid) {
1692 /* Just show the first executing process, more is confusing */
1693 len += scnprintf(error->error_msg + len,
1694 sizeof(error->error_msg) - len,
1695 ", in %s [%d]",
1696 first->context.comm, first->context.pid);
1697 }
1698
1699 return error->error_msg;
1700 }
1701
1702 static void capture_gen(struct i915_gpu_coredump *error)
1703 {
1704 struct drm_i915_private *i915 = error->i915;
1705
1706 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1707 error->suspended = i915->runtime_pm.suspended;
1708
1709 error->iommu = -1;
1710 #ifdef CONFIG_INTEL_IOMMU
1711 error->iommu = intel_iommu_gfx_mapped;
1712 #endif
1713 error->reset_count = i915_reset_count(&i915->gpu_error);
1714 error->suspend_count = i915->suspend_count;
1715
1716 i915_params_copy(&error->params, &i915->params);
1717 memcpy(&error->device_info,
1718 INTEL_INFO(i915),
1719 sizeof(error->device_info));
1720 memcpy(&error->runtime_info,
1721 RUNTIME_INFO(i915),
1722 sizeof(error->runtime_info));
1723 error->driver_caps = i915->caps;
1724 }
1725
1726 struct i915_gpu_coredump *
1727 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
1728 {
1729 struct i915_gpu_coredump *error;
1730
1731 if (!i915->params.error_capture)
1732 return NULL;
1733
1734 error = kzalloc(sizeof(*error), gfp);
1735 if (!error)
1736 return NULL;
1737
1738 kref_init(&error->ref);
1739 error->i915 = i915;
1740
1741 error->time = ktime_get_real();
1742 error->boottime = ktime_get_boottime();
1743 error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time);
1744 error->capture = jiffies;
1745
1746 capture_gen(error);
1747
1748 return error;
1749 }
1750
1751 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1752
1753 struct intel_gt_coredump *
1754 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
1755 {
1756 struct intel_gt_coredump *gc;
1757
1758 gc = kzalloc(sizeof(*gc), gfp);
1759 if (!gc)
1760 return NULL;
1761
1762 gc->_gt = gt;
1763 gc->awake = intel_gt_pm_is_awake(gt);
1764
1765 gt_record_regs(gc);
1766 gt_record_fences(gc);
1767
1768 return gc;
1769 }
1770
1771 struct i915_vma_compress *
1772 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
1773 {
1774 struct i915_vma_compress *compress;
1775
1776 compress = kmalloc(sizeof(*compress), ALLOW_FAIL);
1777 if (!compress)
1778 return NULL;
1779
1780 if (!compress_init(compress)) {
1781 kfree(compress);
1782 return NULL;
1783 }
1784
1785 gt_capture_prepare(gt);
1786
1787 return compress;
1788 }
1789
1790 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
1791 struct i915_vma_compress *compress)
1792 {
1793 if (!compress)
1794 return;
1795
1796 gt_capture_finish(gt);
1797
1798 compress_fini(compress);
1799 kfree(compress);
1800 }
1801
1802 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
1803 {
1804 struct i915_gpu_coredump *error;
1805
1806 /* Check if GPU capture has been disabled */
1807 error = READ_ONCE(i915->gpu_error.first_error);
1808 if (IS_ERR(error))
1809 return error;
1810
1811 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);
1812 if (!error)
1813 return ERR_PTR(-ENOMEM);
1814
1815 error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL);
1816 if (error->gt) {
1817 struct i915_vma_compress *compress;
1818
1819 compress = i915_vma_capture_prepare(error->gt);
1820 if (!compress) {
1821 kfree(error->gt);
1822 kfree(error);
1823 return ERR_PTR(-ENOMEM);
1824 }
1825
1826 gt_record_info(error->gt);
1827 gt_record_engines(error->gt, compress);
1828
1829 if (INTEL_INFO(i915)->has_gt_uc)
1830 error->gt->uc = gt_record_uc(error->gt, compress);
1831
1832 i915_vma_capture_finish(error->gt, compress);
1833
1834 error->simulated |= error->gt->simulated;
1835 }
1836
1837 error->overlay = intel_overlay_capture_error_state(i915);
1838 error->display = intel_display_capture_error_state(i915);
1839
1840 return error;
1841 }
1842
1843 void i915_error_state_store(struct i915_gpu_coredump *error)
1844 {
1845 struct drm_i915_private *i915;
1846 static bool warned;
1847
1848 if (IS_ERR_OR_NULL(error))
1849 return;
1850
1851 i915 = error->i915;
1852 drm_info(&i915->drm, "%s\n", error_msg(error));
1853
1854 if (error->simulated ||
1855 cmpxchg(&i915->gpu_error.first_error, NULL, error))
1856 return;
1857
1858 i915_gpu_coredump_get(error);
1859
1860 if (!xchg(&warned, true) &&
1861 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1862 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1863 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
1864 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n");
1865 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1866 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
1867 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1868 i915->drm.primary->index);
1869 }
1870 }
1871
1872 /**
1873 * i915_capture_error_state - capture an error record for later analysis
1874 * @i915: i915 device
1875 *
1876 * Should be called when an error is detected (either a hang or an error
1877 * interrupt) to capture error state from the time of the error. Fills
1878 * out a structure which becomes available in debugfs for user level tools
1879 * to pick up.
1880 */
1881 void i915_capture_error_state(struct drm_i915_private *i915)
1882 {
1883 struct i915_gpu_coredump *error;
1884
1885 error = i915_gpu_coredump(i915);
1886 if (IS_ERR(error)) {
1887 cmpxchg(&i915->gpu_error.first_error, NULL, error);
1888 return;
1889 }
1890
1891 i915_error_state_store(error);
1892 i915_gpu_coredump_put(error);
1893 }
1894
1895 struct i915_gpu_coredump *
1896 i915_first_error_state(struct drm_i915_private *i915)
1897 {
1898 struct i915_gpu_coredump *error;
1899
1900 spin_lock_irq(&i915->gpu_error.lock);
1901 error = i915->gpu_error.first_error;
1902 if (!IS_ERR_OR_NULL(error))
1903 i915_gpu_coredump_get(error);
1904 spin_unlock_irq(&i915->gpu_error.lock);
1905
1906 return error;
1907 }
1908
1909 void i915_reset_error_state(struct drm_i915_private *i915)
1910 {
1911 struct i915_gpu_coredump *error;
1912
1913 spin_lock_irq(&i915->gpu_error.lock);
1914 error = i915->gpu_error.first_error;
1915 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
1916 i915->gpu_error.first_error = NULL;
1917 spin_unlock_irq(&i915->gpu_error.lock);
1918
1919 if (!IS_ERR_OR_NULL(error))
1920 i915_gpu_coredump_put(error);
1921 }
1922
1923 void i915_disable_error_state(struct drm_i915_private *i915, int err)
1924 {
1925 spin_lock_irq(&i915->gpu_error.lock);
1926 if (!i915->gpu_error.first_error)
1927 i915->gpu_error.first_error = ERR_PTR(err);
1928 spin_unlock_irq(&i915->gpu_error.lock);
1929 }
Linux with added FPC-III support