drivers/gpu/drm/panel/panel-raydium-rm68200.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2017
   4  *
   5  * Authors: Philippe Cornu <philippe.cornu@st.com>
   6  *          Yannick Fertre <yannick.fertre@st.com>
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/gpio/consumer.h>
  11 #include <linux/mod_devicetable.h>
  12 #include <linux/module.h>
  13 #include <linux/regulator/consumer.h>
  14
  15 #include <video/mipi_display.h>
  16
  17 #include <drm/drm_mipi_dsi.h>
  18 #include <drm/drm_modes.h>
  19 #include <drm/drm_panel.h>
  20 #include <drm/drm_print.h>
  21
  22 /*** Manufacturer Command Set ***/
  23 #define MCS_CMD_MODE_SW         0xFE /* CMD Mode Switch */
  24 #define MCS_CMD1_UCS            0x00 /* User Command Set (UCS = CMD1) */
  25 #define MCS_CMD2_P0             0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
  26 #define MCS_CMD2_P1             0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
  27 #define MCS_CMD2_P2             0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
  28 #define MCS_CMD2_P3             0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
  29
  30 /* CMD2 P0 commands (Display Options and Power) */
  31 #define MCS_STBCTR              0x12 /* TE1 Output Setting Zig-Zag Connection */
  32 #define MCS_SGOPCTR             0x16 /* Source Bias Current */
  33 #define MCS_SDCTR               0x1A /* Source Output Delay Time */
  34 #define MCS_INVCTR              0x1B /* Inversion Type */
  35 #define MCS_EXT_PWR_IC          0x24 /* External PWR IC Control */
  36 #define MCS_SETAVDD             0x27 /* PFM Control for AVDD Output */
  37 #define MCS_SETAVEE             0x29 /* PFM Control for AVEE Output */
  38 #define MCS_BT2CTR              0x2B /* DDVDL Charge Pump Control */
  39 #define MCS_BT3CTR              0x2F /* VGH Charge Pump Control */
  40 #define MCS_BT4CTR              0x34 /* VGL Charge Pump Control */
  41 #define MCS_VCMCTR              0x46 /* VCOM Output Level Control */
  42 #define MCS_SETVGN              0x52 /* VG M/S N Control */
  43 #define MCS_SETVGP              0x54 /* VG M/S P Control */
  44 #define MCS_SW_CTRL             0x5F /* Interface Control for PFM and MIPI */
  45
  46 /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
  47 #define GOA_VSTV1               0x00
  48 #define GOA_VSTV2               0x07
  49 #define GOA_VCLK1               0x0E
  50 #define GOA_VCLK2               0x17
  51 #define GOA_VCLK_OPT1           0x20
  52 #define GOA_BICLK1              0x2A
  53 #define GOA_BICLK2              0x37
  54 #define GOA_BICLK3              0x44
  55 #define GOA_BICLK4              0x4F
  56 #define GOA_BICLK_OPT1          0x5B
  57 #define GOA_BICLK_OPT2          0x60
  58 #define MCS_GOA_GPO1            0x6D
  59 #define MCS_GOA_GPO2            0x71
  60 #define MCS_GOA_EQ              0x74
  61 #define MCS_GOA_CLK_GALLON      0x7C
  62 #define MCS_GOA_FS_SEL0         0x7E
  63 #define MCS_GOA_FS_SEL1         0x87
  64 #define MCS_GOA_FS_SEL2         0x91
  65 #define MCS_GOA_FS_SEL3         0x9B
  66 #define MCS_GOA_BS_SEL0         0xAC
  67 #define MCS_GOA_BS_SEL1         0xB5
  68 #define MCS_GOA_BS_SEL2         0xBF
  69 #define MCS_GOA_BS_SEL3         0xC9
  70 #define MCS_GOA_BS_SEL4         0xD3
  71
  72 /* CMD2 P3 commands (Gamma) */
  73 #define MCS_GAMMA_VP            0x60 /* Gamma VP1~VP16 */
  74 #define MCS_GAMMA_VN            0x70 /* Gamma VN1~VN16 */
  75
  76 struct rm68200 {
  77         struct device *dev;
  78         struct drm_panel panel;
  79         struct gpio_desc *reset_gpio;
  80         struct regulator *supply;
  81         bool prepared;
  82         bool enabled;
  83 };
  84
  85 static const struct drm_display_mode default_mode = {
  86         .clock = 52582,
  87         .hdisplay = 720,
  88         .hsync_start = 720 + 38,
  89         .hsync_end = 720 + 38 + 8,
  90         .htotal = 720 + 38 + 8 + 38,
  91         .vdisplay = 1280,
  92         .vsync_start = 1280 + 12,
  93         .vsync_end = 1280 + 12 + 4,
  94         .vtotal = 1280 + 12 + 4 + 12,
  95         .flags = 0,
  96         .width_mm = 68,
  97         .height_mm = 122,
  98 };
  99
 100 static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel)
 101 {
 102         return container_of(panel, struct rm68200, panel);
 103 }
 104
 105 static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data,
 106                                   size_t len)
 107 {
 108         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 109         int err;
 110
 111         err = mipi_dsi_dcs_write_buffer(dsi, data, len);
 112         if (err < 0)
 113                 DRM_ERROR_RATELIMITED("MIPI DSI DCS write buffer failed: %d\n",
 114                                       err);
 115 }
 116
 117 static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value)
 118 {
 119         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 120         int err;
 121
 122         err = mipi_dsi_dcs_write(dsi, cmd, &value, 1);
 123         if (err < 0)
 124                 DRM_ERROR_RATELIMITED("MIPI DSI DCS write failed: %d\n", err);
 125 }
 126
 127 #define dcs_write_seq(ctx, seq...)                              \
 128 ({                                                              \
 129         static const u8 d[] = { seq };                          \
 130                                                                 \
 131         rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d));           \
 132 })
 133
 134 /*
 135  * This panel is not able to auto-increment all cmd addresses so for some of
 136  * them, we need to send them one by one...
 137  */
 138 #define dcs_write_cmd_seq(ctx, cmd, seq...)                     \
 139 ({                                                              \
 140         static const u8 d[] = { seq };                          \
 141         unsigned int i;                                         \
 142                                                                 \
 143         for (i = 0; i < ARRAY_SIZE(d) ; i++)                    \
 144                 rm68200_dcs_write_cmd(ctx, cmd + i, d[i]);      \
 145 })
 146
 147 static void rm68200_init_sequence(struct rm68200 *ctx)
 148 {
 149         /* Enter CMD2 with page 0 */
 150         dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
 151         dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
 152         dcs_write_seq(ctx, MCS_BT2CTR, 0xE5);
 153         dcs_write_seq(ctx, MCS_SETAVDD, 0x0A);
 154         dcs_write_seq(ctx, MCS_SETAVEE, 0x0A);
 155         dcs_write_seq(ctx, MCS_SGOPCTR, 0x52);
 156         dcs_write_seq(ctx, MCS_BT3CTR, 0x53);
 157         dcs_write_seq(ctx, MCS_BT4CTR, 0x5A);
 158         dcs_write_seq(ctx, MCS_INVCTR, 0x00);
 159         dcs_write_seq(ctx, MCS_STBCTR, 0x0A);
 160         dcs_write_seq(ctx, MCS_SDCTR, 0x06);
 161         dcs_write_seq(ctx, MCS_VCMCTR, 0x56);
 162         dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00);
 163         dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00);
 164         dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
 165
 166         dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
 167         dcs_write_seq(ctx, GOA_VSTV1, 0x05);
 168         dcs_write_seq(ctx, 0x02, 0x0B);
 169         dcs_write_seq(ctx, 0x03, 0x0F);
 170         dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50);
 171         dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
 172                           0x50);
 173         dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
 174                           0x00, 0x85, 0x08);
 175         dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
 176                           0x00, 0x85, 0x08);
 177         dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 178                       0x00, 0x00, 0x00, 0x00);
 179         dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08);
 180         dcs_write_seq(ctx, 0x2D, 0x01);
 181         dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
 182                       0x00);
 183         dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
 184         dcs_write_seq(ctx, 0x3D, 0x40);
 185         dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
 186         dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 187                       0x00, 0x00, 0x00, 0x00, 0x00);
 188         dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 189                       0x00, 0x00);
 190         dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00);
 191         dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
 192         dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 193                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 194         dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
 195         dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
 196         dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
 197                       0x00, 0x00);
 198         dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
 199         dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
 200                           0x16, 0x12, 0x08, 0x3F);
 201         dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
 202                           0x0A, 0x0E, 0x3F, 0x3F, 0x00);
 203         dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
 204                           0x05, 0x01, 0x3F, 0x3F, 0x0F);
 205         dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
 206                           0x3F);
 207         dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
 208         dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F);
 209         dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
 210                           0x15, 0x11, 0x0F, 0x3F);
 211         dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
 212                           0x0D, 0x09, 0x3F, 0x3F, 0x07);
 213         dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
 214                           0x02, 0x06, 0x3F, 0x3F, 0x08);
 215         dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
 216                           0x3F, 0x3F, 0x0E, 0x10, 0x14);
 217         dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
 218         dcs_write_seq(ctx, 0xDC, 0x02);
 219         dcs_write_seq(ctx, 0xDE, 0x12);
 220
 221         dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
 222         dcs_write_seq(ctx, 0x01, 0x75);
 223
 224         dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
 225         dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 226                           0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 227                           0x12, 0x0C, 0x00);
 228         dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 229                           0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 230                           0x12, 0x0C, 0x00);
 231
 232         /* Exit CMD2 */
 233         dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
 234 }
 235
 236 static int rm68200_disable(struct drm_panel *panel)
 237 {
 238         struct rm68200 *ctx = panel_to_rm68200(panel);
 239
 240         if (!ctx->enabled)
 241                 return 0;
 242
 243         ctx->enabled = false;
 244
 245         return 0;
 246 }
 247
 248 static int rm68200_unprepare(struct drm_panel *panel)
 249 {
 250         struct rm68200 *ctx = panel_to_rm68200(panel);
 251         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 252         int ret;
 253
 254         if (!ctx->prepared)
 255                 return 0;
 256
 257         ret = mipi_dsi_dcs_set_display_off(dsi);
 258         if (ret)
 259                 DRM_WARN("failed to set display off: %d\n", ret);
 260
 261         ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
 262         if (ret)
 263                 DRM_WARN("failed to enter sleep mode: %d\n", ret);
 264
 265         msleep(120);
 266
 267         if (ctx->reset_gpio) {
 268                 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
 269                 msleep(20);
 270         }
 271
 272         regulator_disable(ctx->supply);
 273
 274         ctx->prepared = false;
 275
 276         return 0;
 277 }
 278
 279 static int rm68200_prepare(struct drm_panel *panel)
 280 {
 281         struct rm68200 *ctx = panel_to_rm68200(panel);
 282         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 283         int ret;
 284
 285         if (ctx->prepared)
 286                 return 0;
 287
 288         ret = regulator_enable(ctx->supply);
 289         if (ret < 0) {
 290                 DRM_ERROR("failed to enable supply: %d\n", ret);
 291                 return ret;
 292         }
 293
 294         if (ctx->reset_gpio) {
 295                 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
 296                 msleep(20);
 297                 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
 298                 msleep(100);
 299         }
 300
 301         rm68200_init_sequence(ctx);
 302
 303         ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
 304         if (ret)
 305                 return ret;
 306
 307         msleep(125);
 308
 309         ret = mipi_dsi_dcs_set_display_on(dsi);
 310         if (ret)
 311                 return ret;
 312
 313         msleep(20);
 314
 315         ctx->prepared = true;
 316
 317         return 0;
 318 }
 319
 320 static int rm68200_enable(struct drm_panel *panel)
 321 {
 322         struct rm68200 *ctx = panel_to_rm68200(panel);
 323
 324         if (ctx->enabled)
 325                 return 0;
 326
 327         ctx->enabled = true;
 328
 329         return 0;
 330 }
 331
 332 static int rm68200_get_modes(struct drm_panel *panel,
 333                              struct drm_connector *connector)
 334 {
 335         struct drm_display_mode *mode;
 336
 337         mode = drm_mode_duplicate(connector->dev, &default_mode);
 338         if (!mode) {
 339                 DRM_ERROR("failed to add mode %ux%ux@%u\n",
 340                           default_mode.hdisplay, default_mode.vdisplay,
 341                           drm_mode_vrefresh(&default_mode));
 342                 return -ENOMEM;
 343         }
 344
 345         drm_mode_set_name(mode);
 346
 347         mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 348         drm_mode_probed_add(connector, mode);
 349
 350         connector->display_info.width_mm = mode->width_mm;
 351         connector->display_info.height_mm = mode->height_mm;
 352
 353         return 1;
 354 }
 355
 356 static const struct drm_panel_funcs rm68200_drm_funcs = {
 357         .disable = rm68200_disable,
 358         .unprepare = rm68200_unprepare,
 359         .prepare = rm68200_prepare,
 360         .enable = rm68200_enable,
 361         .get_modes = rm68200_get_modes,
 362 };
 363
 364 static int rm68200_probe(struct mipi_dsi_device *dsi)
 365 {
 366         struct device *dev = &dsi->dev;
 367         struct rm68200 *ctx;
 368         int ret;
 369
 370         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 371         if (!ctx)
 372                 return -ENOMEM;
 373
 374         ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
 375         if (IS_ERR(ctx->reset_gpio)) {
 376                 ret = PTR_ERR(ctx->reset_gpio);
 377                 dev_err(dev, "cannot get reset GPIO: %d\n", ret);
 378                 return ret;
 379         }
 380
 381         ctx->supply = devm_regulator_get(dev, "power");
 382         if (IS_ERR(ctx->supply)) {
 383                 ret = PTR_ERR(ctx->supply);
 384                 if (ret != -EPROBE_DEFER)
 385                         dev_err(dev, "cannot get regulator: %d\n", ret);
 386                 return ret;
 387         }
 388
 389         mipi_dsi_set_drvdata(dsi, ctx);
 390
 391         ctx->dev = dev;
 392
 393         dsi->lanes = 2;
 394         dsi->format = MIPI_DSI_FMT_RGB888;
 395         dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
 396                           MIPI_DSI_MODE_LPM;
 397
 398         drm_panel_init(&ctx->panel, dev, &rm68200_drm_funcs,
 399                        DRM_MODE_CONNECTOR_DSI);
 400
 401         ret = drm_panel_of_backlight(&ctx->panel);
 402         if (ret)
 403                 return ret;
 404
 405         drm_panel_add(&ctx->panel);
 406
 407         ret = mipi_dsi_attach(dsi);
 408         if (ret < 0) {
 409                 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
 410                 drm_panel_remove(&ctx->panel);
 411                 return ret;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static int rm68200_remove(struct mipi_dsi_device *dsi)
 418 {
 419         struct rm68200 *ctx = mipi_dsi_get_drvdata(dsi);
 420
 421         mipi_dsi_detach(dsi);
 422         drm_panel_remove(&ctx->panel);
 423
 424         return 0;
 425 }
 426
 427 static const struct of_device_id raydium_rm68200_of_match[] = {
 428         { .compatible = "raydium,rm68200" },
 429         { }
 430 };
 431 MODULE_DEVICE_TABLE(of, raydium_rm68200_of_match);
 432
 433 static struct mipi_dsi_driver raydium_rm68200_driver = {
 434         .probe = rm68200_probe,
 435         .remove = rm68200_remove,
 436         .driver = {
 437                 .name = "panel-raydium-rm68200",
 438                 .of_match_table = raydium_rm68200_of_match,
 439         },
 440 };
 441 module_mipi_dsi_driver(raydium_rm68200_driver);
 442
 443 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
 444 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
 445 MODULE_DESCRIPTION("DRM Driver for Raydium RM68200 MIPI DSI panel");
 446 MODULE_LICENSE("GPL v2");