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Linux 5.9.7
[linux/fpc-iii.git] / drivers / misc / cardreader / rts5227.c
blobf5f392ddf3d67bc11fe8aee9a5c3eaeaf29010b7
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 * Roger Tseng <rogerable@realtek.com>
9 */
10
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/rtsx_pci.h>
14
15 #include "rtsx_pcr.h"
16
17 static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
18 {
19 u8 val;
20
21 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
22 return val & 0x0F;
23 }
24
25 static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
26 {
27 u8 driving_3v3[4][3] = {
28 {0x13, 0x13, 0x13},
29 {0x96, 0x96, 0x96},
30 {0x7F, 0x7F, 0x7F},
31 {0x96, 0x96, 0x96},
32 };
33 u8 driving_1v8[4][3] = {
34 {0x99, 0x99, 0x99},
35 {0xAA, 0xAA, 0xAA},
36 {0xFE, 0xFE, 0xFE},
37 {0xB3, 0xB3, 0xB3},
38 };
39 u8 (*driving)[3], drive_sel;
40
41 if (voltage == OUTPUT_3V3) {
42 driving = driving_3v3;
43 drive_sel = pcr->sd30_drive_sel_3v3;
44 } else {
45 driving = driving_1v8;
46 drive_sel = pcr->sd30_drive_sel_1v8;
47 }
48
49 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
50 0xFF, driving[drive_sel][0]);
51 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
52 0xFF, driving[drive_sel][1]);
53 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
54 0xFF, driving[drive_sel][2]);
55 }
56
57 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
58 {
59 struct pci_dev *pdev = pcr->pci;
60 u32 reg;
61
62 pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
63 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
64
65 if (!rtsx_vendor_setting_valid(reg))
66 return;
67
68 pcr->aspm_en = rtsx_reg_to_aspm(reg);
69 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
70 pcr->card_drive_sel &= 0x3F;
71 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
72
73 pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
74 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
75 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
76 if (rtsx_reg_check_reverse_socket(reg))
77 pcr->flags |= PCR_REVERSE_SOCKET;
78 }
79
80 static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
81 {
82 /* Set relink_time to 0 */
83 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
84 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
85 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
86
87 if (pm_state == HOST_ENTER_S3)
88 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x10);
89
90 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
91 }
92
93 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
94 {
95 u16 cap;
96
97 rtsx_pci_init_cmd(pcr);
98
99 /* Configure GPIO as output */
100 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
101 /* Reset ASPM state to default value */
102 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
103 /* Switch LDO3318 source from DV33 to card_3v3 */
104 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
106 /* LED shine disabled, set initial shine cycle period */
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
108 /* Configure LTR */
109 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
110 if (cap & PCI_EXP_DEVCTL2_LTR_EN)
111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
112 /* Configure OBFF */
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
114 /* Configure driving */
115 rts5227_fill_driving(pcr, OUTPUT_3V3);
116 /* Configure force_clock_req */
117 if (pcr->flags & PCR_REVERSE_SOCKET)
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
119 else
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
122
123 return rtsx_pci_send_cmd(pcr, 100);
124 }
125
126 static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
127 {
128 int err;
129
130 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
131 if (err < 0)
132 return err;
133
134 /* Optimize RX sensitivity */
135 return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
136 }
137
138 static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
139 {
140 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
141 }
142
143 static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
144 {
145 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
146 }
147
148 static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
149 {
150 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
151 }
152
153 static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
154 {
155 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
156 }
157
158 static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
159 {
160 int err;
161
162 if (pcr->option.ocp_en)
163 rtsx_pci_enable_ocp(pcr);
164
165 rtsx_pci_init_cmd(pcr);
166 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
167 SD_POWER_MASK, SD_PARTIAL_POWER_ON);
168
169 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
170 LDO3318_PWR_MASK, 0x02);
171
172 err = rtsx_pci_send_cmd(pcr, 100);
173 if (err < 0)
174 return err;
175
176 /* To avoid too large in-rush current */
177 msleep(20);
178 rtsx_pci_init_cmd(pcr);
179 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
180 SD_POWER_MASK, SD_POWER_ON);
181
182 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
183 LDO3318_PWR_MASK, 0x06);
184
185 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
186 SD_OUTPUT_EN, SD_OUTPUT_EN);
187 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
188 MS_OUTPUT_EN, MS_OUTPUT_EN);
189 return rtsx_pci_send_cmd(pcr, 100);
190 }
191
192 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
193 {
194 if (pcr->option.ocp_en)
195 rtsx_pci_disable_ocp(pcr);
196
197 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
198 PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
199 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
200
201 return 0;
202 }
203
204 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
205 {
206 int err;
207
208 if (voltage == OUTPUT_3V3) {
209 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
210 if (err < 0)
211 return err;
212 } else if (voltage == OUTPUT_1V8) {
213 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
214 if (err < 0)
215 return err;
216 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
217 if (err < 0)
218 return err;
219 } else {
220 return -EINVAL;
221 }
222
223 /* set pad drive */
224 rtsx_pci_init_cmd(pcr);
225 rts5227_fill_driving(pcr, voltage);
226 return rtsx_pci_send_cmd(pcr, 100);
227 }
228
229 static const struct pcr_ops rts5227_pcr_ops = {
230 .fetch_vendor_settings = rts5227_fetch_vendor_settings,
231 .extra_init_hw = rts5227_extra_init_hw,
232 .optimize_phy = rts5227_optimize_phy,
233 .turn_on_led = rts5227_turn_on_led,
234 .turn_off_led = rts5227_turn_off_led,
235 .enable_auto_blink = rts5227_enable_auto_blink,
236 .disable_auto_blink = rts5227_disable_auto_blink,
237 .card_power_on = rts5227_card_power_on,
238 .card_power_off = rts5227_card_power_off,
239 .switch_output_voltage = rts5227_switch_output_voltage,
240 .cd_deglitch = NULL,
241 .conv_clk_and_div_n = NULL,
242 .force_power_down = rts5227_force_power_down,
243 };
244
245 /* SD Pull Control Enable:
246 * SD_DAT[3:0] ==> pull up
247 * SD_CD ==> pull up
248 * SD_WP ==> pull up
249 * SD_CMD ==> pull up
250 * SD_CLK ==> pull down
251 */
252 static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
253 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
254 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
255 0,
256 };
257
258 /* SD Pull Control Disable:
259 * SD_DAT[3:0] ==> pull down
260 * SD_CD ==> pull up
261 * SD_WP ==> pull down
262 * SD_CMD ==> pull down
263 * SD_CLK ==> pull down
264 */
265 static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
266 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
267 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
268 0,
269 };
270
271 /* MS Pull Control Enable:
272 * MS CD ==> pull up
273 * others ==> pull down
274 */
275 static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
276 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
277 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
278 0,
279 };
280
281 /* MS Pull Control Disable:
282 * MS CD ==> pull up
283 * others ==> pull down
284 */
285 static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
286 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
287 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
288 0,
289 };
290
291 void rts5227_init_params(struct rtsx_pcr *pcr)
292 {
293 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
294 pcr->num_slots = 2;
295 pcr->ops = &rts5227_pcr_ops;
296
297 pcr->flags = 0;
298 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
299 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
300 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
301 pcr->aspm_en = ASPM_L1_EN;
302 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
303 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
304
305 pcr->ic_version = rts5227_get_ic_version(pcr);
306 pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
307 pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
308 pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
309 pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
310
311 pcr->reg_pm_ctrl3 = PM_CTRL3;
312 }
313
314 static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
315 {
316 int err;
317
318 err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
319 0x00);
320 if (err < 0)
321 return err;
322
323 if (is_version(pcr, 0x522A, IC_VER_A)) {
324 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
325 PHY_RCR2_INIT_27S);
326 if (err)
327 return err;
328
329 rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
330 rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
331 rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
332 rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
333 }
334
335 return 0;
336 }
337
338 static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
339 {
340 rts5227_extra_init_hw(pcr);
341
342 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
343 FUNC_FORCE_UPME_XMT_DBG);
344 rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
345 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
346 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
347
348 return 0;
349 }
350
351 static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
352 {
353 int err;
354
355 if (voltage == OUTPUT_3V3) {
356 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
357 if (err < 0)
358 return err;
359 } else if (voltage == OUTPUT_1V8) {
360 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
361 if (err < 0)
362 return err;
363 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
364 if (err < 0)
365 return err;
366 } else {
367 return -EINVAL;
368 }
369
370 /* set pad drive */
371 rtsx_pci_init_cmd(pcr);
372 rts5227_fill_driving(pcr, voltage);
373 return rtsx_pci_send_cmd(pcr, 100);
374 }
375
376
377 /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
378 */
379 static const struct pcr_ops rts522a_pcr_ops = {
380 .fetch_vendor_settings = rts5227_fetch_vendor_settings,
381 .extra_init_hw = rts522a_extra_init_hw,
382 .optimize_phy = rts522a_optimize_phy,
383 .turn_on_led = rts5227_turn_on_led,
384 .turn_off_led = rts5227_turn_off_led,
385 .enable_auto_blink = rts5227_enable_auto_blink,
386 .disable_auto_blink = rts5227_disable_auto_blink,
387 .card_power_on = rts5227_card_power_on,
388 .card_power_off = rts5227_card_power_off,
389 .switch_output_voltage = rts522a_switch_output_voltage,
390 .cd_deglitch = NULL,
391 .conv_clk_and_div_n = NULL,
392 .force_power_down = rts5227_force_power_down,
393 };
394
395 void rts522a_init_params(struct rtsx_pcr *pcr)
396 {
397 rts5227_init_params(pcr);
398 pcr->ops = &rts522a_pcr_ops;
399 pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
400 pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
401
402 pcr->option.ocp_en = 1;
403 if (pcr->option.ocp_en)
404 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
405 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
406 pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
407
408 }
Linux with added FPC-III support