drivers/spi/spi-mtk-nor.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Mediatek SPI NOR controller driver
   4 //
   5 // Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
   6
   7 #include <linux/bits.h>
   8 #include <linux/clk.h>
   9 #include <linux/completion.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of_device.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/spi/spi-mem.h>
  19 #include <linux/string.h>
  20
  21 #define DRIVER_NAME "mtk-spi-nor"
  22
  23 #define MTK_NOR_REG_CMD                 0x00
  24 #define MTK_NOR_CMD_WRITE               BIT(4)
  25 #define MTK_NOR_CMD_PROGRAM             BIT(2)
  26 #define MTK_NOR_CMD_READ                BIT(0)
  27 #define MTK_NOR_CMD_MASK                GENMASK(5, 0)
  28
  29 #define MTK_NOR_REG_PRG_CNT             0x04
  30 #define MTK_NOR_REG_RDATA               0x0c
  31
  32 #define MTK_NOR_REG_RADR0               0x10
  33 #define MTK_NOR_REG_RADR(n)             (MTK_NOR_REG_RADR0 + 4 * (n))
  34 #define MTK_NOR_REG_RADR3               0xc8
  35
  36 #define MTK_NOR_REG_WDATA               0x1c
  37
  38 #define MTK_NOR_REG_PRGDATA0            0x20
  39 #define MTK_NOR_REG_PRGDATA(n)          (MTK_NOR_REG_PRGDATA0 + 4 * (n))
  40 #define MTK_NOR_REG_PRGDATA_MAX         5
  41
  42 #define MTK_NOR_REG_SHIFT0              0x38
  43 #define MTK_NOR_REG_SHIFT(n)            (MTK_NOR_REG_SHIFT0 + 4 * (n))
  44 #define MTK_NOR_REG_SHIFT_MAX           9
  45
  46 #define MTK_NOR_REG_CFG1                0x60
  47 #define MTK_NOR_FAST_READ               BIT(0)
  48
  49 #define MTK_NOR_REG_CFG2                0x64
  50 #define MTK_NOR_WR_CUSTOM_OP_EN         BIT(4)
  51 #define MTK_NOR_WR_BUF_EN               BIT(0)
  52
  53 #define MTK_NOR_REG_PP_DATA             0x98
  54
  55 #define MTK_NOR_REG_IRQ_STAT            0xa8
  56 #define MTK_NOR_REG_IRQ_EN              0xac
  57 #define MTK_NOR_IRQ_DMA                 BIT(7)
  58 #define MTK_NOR_IRQ_MASK                GENMASK(7, 0)
  59
  60 #define MTK_NOR_REG_CFG3                0xb4
  61 #define MTK_NOR_DISABLE_WREN            BIT(7)
  62 #define MTK_NOR_DISABLE_SR_POLL         BIT(5)
  63
  64 #define MTK_NOR_REG_WP                  0xc4
  65 #define MTK_NOR_ENABLE_SF_CMD           0x30
  66
  67 #define MTK_NOR_REG_BUSCFG              0xcc
  68 #define MTK_NOR_4B_ADDR                 BIT(4)
  69 #define MTK_NOR_QUAD_ADDR               BIT(3)
  70 #define MTK_NOR_QUAD_READ               BIT(2)
  71 #define MTK_NOR_DUAL_ADDR               BIT(1)
  72 #define MTK_NOR_DUAL_READ               BIT(0)
  73 #define MTK_NOR_BUS_MODE_MASK           GENMASK(4, 0)
  74
  75 #define MTK_NOR_REG_DMA_CTL             0x718
  76 #define MTK_NOR_DMA_START               BIT(0)
  77
  78 #define MTK_NOR_REG_DMA_FADR            0x71c
  79 #define MTK_NOR_REG_DMA_DADR            0x720
  80 #define MTK_NOR_REG_DMA_END_DADR        0x724
  81
  82 #define MTK_NOR_PRG_MAX_SIZE            6
  83 // Reading DMA src/dst addresses have to be 16-byte aligned
  84 #define MTK_NOR_DMA_ALIGN               16
  85 #define MTK_NOR_DMA_ALIGN_MASK          (MTK_NOR_DMA_ALIGN - 1)
  86 // and we allocate a bounce buffer if destination address isn't aligned.
  87 #define MTK_NOR_BOUNCE_BUF_SIZE         PAGE_SIZE
  88
  89 // Buffered page program can do one 128-byte transfer
  90 #define MTK_NOR_PP_SIZE                 128
  91
  92 #define CLK_TO_US(sp, clkcnt)           DIV_ROUND_UP(clkcnt, sp->spi_freq / 1000000)
  93
  94 struct mtk_nor {
  95         struct spi_controller *ctlr;
  96         struct device *dev;
  97         void __iomem *base;
  98         u8 *buffer;
  99         struct clk *spi_clk;
 100         struct clk *ctlr_clk;
 101         unsigned int spi_freq;
 102         bool wbuf_en;
 103         bool has_irq;
 104         struct completion op_done;
 105 };
 106
 107 static inline void mtk_nor_rmw(struct mtk_nor *sp, u32 reg, u32 set, u32 clr)
 108 {
 109         u32 val = readl(sp->base + reg);
 110
 111         val &= ~clr;
 112         val |= set;
 113         writel(val, sp->base + reg);
 114 }
 115
 116 static inline int mtk_nor_cmd_exec(struct mtk_nor *sp, u32 cmd, ulong clk)
 117 {
 118         ulong delay = CLK_TO_US(sp, clk);
 119         u32 reg;
 120         int ret;
 121
 122         writel(cmd, sp->base + MTK_NOR_REG_CMD);
 123         ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CMD, reg, !(reg & cmd),
 124                                  delay / 3, (delay + 1) * 200);
 125         if (ret < 0)
 126                 dev_err(sp->dev, "command %u timeout.\n", cmd);
 127         return ret;
 128 }
 129
 130 static void mtk_nor_set_addr(struct mtk_nor *sp, const struct spi_mem_op *op)
 131 {
 132         u32 addr = op->addr.val;
 133         int i;
 134
 135         for (i = 0; i < 3; i++) {
 136                 writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR(i));
 137                 addr >>= 8;
 138         }
 139         if (op->addr.nbytes == 4) {
 140                 writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR3);
 141                 mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, MTK_NOR_4B_ADDR, 0);
 142         } else {
 143                 mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, 0, MTK_NOR_4B_ADDR);
 144         }
 145 }
 146
 147 static bool mtk_nor_match_read(const struct spi_mem_op *op)
 148 {
 149         int dummy = 0;
 150
 151         if (op->dummy.buswidth)
 152                 dummy = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth;
 153
 154         if ((op->data.buswidth == 2) || (op->data.buswidth == 4)) {
 155                 if (op->addr.buswidth == 1)
 156                         return dummy == 8;
 157                 else if (op->addr.buswidth == 2)
 158                         return dummy == 4;
 159                 else if (op->addr.buswidth == 4)
 160                         return dummy == 6;
 161         } else if ((op->addr.buswidth == 1) && (op->data.buswidth == 1)) {
 162                 if (op->cmd.opcode == 0x03)
 163                         return dummy == 0;
 164                 else if (op->cmd.opcode == 0x0b)
 165                         return dummy == 8;
 166         }
 167         return false;
 168 }
 169
 170 static int mtk_nor_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
 171 {
 172         size_t len;
 173
 174         if (!op->data.nbytes)
 175                 return 0;
 176
 177         if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) {
 178                 if ((op->data.dir == SPI_MEM_DATA_IN) &&
 179                     mtk_nor_match_read(op)) {
 180                         // limit size to prevent timeout calculation overflow
 181                         if (op->data.nbytes > 0x400000)
 182                                 op->data.nbytes = 0x400000;
 183
 184                         if ((op->addr.val & MTK_NOR_DMA_ALIGN_MASK) ||
 185                             (op->data.nbytes < MTK_NOR_DMA_ALIGN))
 186                                 op->data.nbytes = 1;
 187                         else if (!((ulong)(op->data.buf.in) &
 188                                    MTK_NOR_DMA_ALIGN_MASK))
 189                                 op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK;
 190                         else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE)
 191                                 op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE;
 192                         return 0;
 193                 } else if (op->data.dir == SPI_MEM_DATA_OUT) {
 194                         if (op->data.nbytes >= MTK_NOR_PP_SIZE)
 195                                 op->data.nbytes = MTK_NOR_PP_SIZE;
 196                         else
 197                                 op->data.nbytes = 1;
 198                         return 0;
 199                 }
 200         }
 201
 202         len = MTK_NOR_PRG_MAX_SIZE - op->cmd.nbytes - op->addr.nbytes -
 203               op->dummy.nbytes;
 204         if (op->data.nbytes > len)
 205                 op->data.nbytes = len;
 206
 207         return 0;
 208 }
 209
 210 static bool mtk_nor_supports_op(struct spi_mem *mem,
 211                                 const struct spi_mem_op *op)
 212 {
 213         size_t len;
 214
 215         if (op->cmd.buswidth != 1)
 216                 return false;
 217
 218         /* DTR ops not supported. */
 219         if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
 220                 return false;
 221         if (op->cmd.nbytes != 1)
 222                 return false;
 223
 224         if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) {
 225                 if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op))
 226                         return true;
 227                 else if (op->data.dir == SPI_MEM_DATA_OUT)
 228                         return (op->addr.buswidth == 1) &&
 229                                (op->dummy.buswidth == 0) &&
 230                                (op->data.buswidth == 1);
 231         }
 232         len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
 233         if ((len > MTK_NOR_PRG_MAX_SIZE) ||
 234             ((op->data.nbytes) && (len == MTK_NOR_PRG_MAX_SIZE)))
 235                 return false;
 236         return true;
 237 }
 238
 239 static void mtk_nor_setup_bus(struct mtk_nor *sp, const struct spi_mem_op *op)
 240 {
 241         u32 reg = 0;
 242
 243         if (op->addr.nbytes == 4)
 244                 reg |= MTK_NOR_4B_ADDR;
 245
 246         if (op->data.buswidth == 4) {
 247                 reg |= MTK_NOR_QUAD_READ;
 248                 writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(4));
 249                 if (op->addr.buswidth == 4)
 250                         reg |= MTK_NOR_QUAD_ADDR;
 251         } else if (op->data.buswidth == 2) {
 252                 reg |= MTK_NOR_DUAL_READ;
 253                 writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(3));
 254                 if (op->addr.buswidth == 2)
 255                         reg |= MTK_NOR_DUAL_ADDR;
 256         } else {
 257                 if (op->cmd.opcode == 0x0b)
 258                         mtk_nor_rmw(sp, MTK_NOR_REG_CFG1, MTK_NOR_FAST_READ, 0);
 259                 else
 260                         mtk_nor_rmw(sp, MTK_NOR_REG_CFG1, 0, MTK_NOR_FAST_READ);
 261         }
 262         mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, reg, MTK_NOR_BUS_MODE_MASK);
 263 }
 264
 265 static int mtk_nor_read_dma(struct mtk_nor *sp, u32 from, unsigned int length,
 266                             u8 *buffer)
 267 {
 268         int ret = 0;
 269         ulong delay;
 270         u32 reg;
 271         dma_addr_t dma_addr;
 272
 273         dma_addr = dma_map_single(sp->dev, buffer, length, DMA_FROM_DEVICE);
 274         if (dma_mapping_error(sp->dev, dma_addr)) {
 275                 dev_err(sp->dev, "failed to map dma buffer.\n");
 276                 return -EINVAL;
 277         }
 278
 279         writel(from, sp->base + MTK_NOR_REG_DMA_FADR);
 280         writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR);
 281         writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR);
 282
 283         if (sp->has_irq) {
 284                 reinit_completion(&sp->op_done);
 285                 mtk_nor_rmw(sp, MTK_NOR_REG_IRQ_EN, MTK_NOR_IRQ_DMA, 0);
 286         }
 287
 288         mtk_nor_rmw(sp, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0);
 289
 290         delay = CLK_TO_US(sp, (length + 5) * BITS_PER_BYTE);
 291
 292         if (sp->has_irq) {
 293                 if (!wait_for_completion_timeout(&sp->op_done,
 294                                                  (delay + 1) * 100))
 295                         ret = -ETIMEDOUT;
 296         } else {
 297                 ret = readl_poll_timeout(sp->base + MTK_NOR_REG_DMA_CTL, reg,
 298                                          !(reg & MTK_NOR_DMA_START), delay / 3,
 299                                          (delay + 1) * 100);
 300         }
 301
 302         dma_unmap_single(sp->dev, dma_addr, length, DMA_FROM_DEVICE);
 303         if (ret < 0)
 304                 dev_err(sp->dev, "dma read timeout.\n");
 305
 306         return ret;
 307 }
 308
 309 static int mtk_nor_read_bounce(struct mtk_nor *sp, u32 from,
 310                                unsigned int length, u8 *buffer)
 311 {
 312         unsigned int rdlen;
 313         int ret;
 314
 315         if (length & MTK_NOR_DMA_ALIGN_MASK)
 316                 rdlen = (length + MTK_NOR_DMA_ALIGN) & ~MTK_NOR_DMA_ALIGN_MASK;
 317         else
 318                 rdlen = length;
 319
 320         ret = mtk_nor_read_dma(sp, from, rdlen, sp->buffer);
 321         if (ret)
 322                 return ret;
 323
 324         memcpy(buffer, sp->buffer, length);
 325         return 0;
 326 }
 327
 328 static int mtk_nor_read_pio(struct mtk_nor *sp, const struct spi_mem_op *op)
 329 {
 330         u8 *buf = op->data.buf.in;
 331         int ret;
 332
 333         ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_READ, 6 * BITS_PER_BYTE);
 334         if (!ret)
 335                 buf[0] = readb(sp->base + MTK_NOR_REG_RDATA);
 336         return ret;
 337 }
 338
 339 static int mtk_nor_write_buffer_enable(struct mtk_nor *sp)
 340 {
 341         int ret;
 342         u32 val;
 343
 344         if (sp->wbuf_en)
 345                 return 0;
 346
 347         val = readl(sp->base + MTK_NOR_REG_CFG2);
 348         writel(val | MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
 349         ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
 350                                  val & MTK_NOR_WR_BUF_EN, 0, 10000);
 351         if (!ret)
 352                 sp->wbuf_en = true;
 353         return ret;
 354 }
 355
 356 static int mtk_nor_write_buffer_disable(struct mtk_nor *sp)
 357 {
 358         int ret;
 359         u32 val;
 360
 361         if (!sp->wbuf_en)
 362                 return 0;
 363         val = readl(sp->base + MTK_NOR_REG_CFG2);
 364         writel(val & ~MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
 365         ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
 366                                  !(val & MTK_NOR_WR_BUF_EN), 0, 10000);
 367         if (!ret)
 368                 sp->wbuf_en = false;
 369         return ret;
 370 }
 371
 372 static int mtk_nor_pp_buffered(struct mtk_nor *sp, const struct spi_mem_op *op)
 373 {
 374         const u8 *buf = op->data.buf.out;
 375         u32 val;
 376         int ret, i;
 377
 378         ret = mtk_nor_write_buffer_enable(sp);
 379         if (ret < 0)
 380                 return ret;
 381
 382         for (i = 0; i < op->data.nbytes; i += 4) {
 383                 val = buf[i + 3] << 24 | buf[i + 2] << 16 | buf[i + 1] << 8 |
 384                       buf[i];
 385                 writel(val, sp->base + MTK_NOR_REG_PP_DATA);
 386         }
 387         return mtk_nor_cmd_exec(sp, MTK_NOR_CMD_WRITE,
 388                                 (op->data.nbytes + 5) * BITS_PER_BYTE);
 389 }
 390
 391 static int mtk_nor_pp_unbuffered(struct mtk_nor *sp,
 392                                  const struct spi_mem_op *op)
 393 {
 394         const u8 *buf = op->data.buf.out;
 395         int ret;
 396
 397         ret = mtk_nor_write_buffer_disable(sp);
 398         if (ret < 0)
 399                 return ret;
 400         writeb(buf[0], sp->base + MTK_NOR_REG_WDATA);
 401         return mtk_nor_cmd_exec(sp, MTK_NOR_CMD_WRITE, 6 * BITS_PER_BYTE);
 402 }
 403
 404 static int mtk_nor_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 405 {
 406         struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master);
 407         int ret;
 408
 409         if ((op->data.nbytes == 0) ||
 410             ((op->addr.nbytes != 3) && (op->addr.nbytes != 4)))
 411                 return -ENOTSUPP;
 412
 413         if (op->data.dir == SPI_MEM_DATA_OUT) {
 414                 mtk_nor_set_addr(sp, op);
 415                 writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA0);
 416                 if (op->data.nbytes == MTK_NOR_PP_SIZE)
 417                         return mtk_nor_pp_buffered(sp, op);
 418                 return mtk_nor_pp_unbuffered(sp, op);
 419         }
 420
 421         if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) {
 422                 ret = mtk_nor_write_buffer_disable(sp);
 423                 if (ret < 0)
 424                         return ret;
 425                 mtk_nor_setup_bus(sp, op);
 426                 if (op->data.nbytes == 1) {
 427                         mtk_nor_set_addr(sp, op);
 428                         return mtk_nor_read_pio(sp, op);
 429                 } else if (((ulong)(op->data.buf.in) &
 430                             MTK_NOR_DMA_ALIGN_MASK)) {
 431                         return mtk_nor_read_bounce(sp, op->addr.val,
 432                                                    op->data.nbytes,
 433                                                    op->data.buf.in);
 434                 } else {
 435                         return mtk_nor_read_dma(sp, op->addr.val,
 436                                                 op->data.nbytes,
 437                                                 op->data.buf.in);
 438                 }
 439         }
 440
 441         return -ENOTSUPP;
 442 }
 443
 444 static int mtk_nor_setup(struct spi_device *spi)
 445 {
 446         struct mtk_nor *sp = spi_controller_get_devdata(spi->master);
 447
 448         if (spi->max_speed_hz && (spi->max_speed_hz < sp->spi_freq)) {
 449                 dev_err(&spi->dev, "spi clock should be %u Hz.\n",
 450                         sp->spi_freq);
 451                 return -EINVAL;
 452         }
 453         spi->max_speed_hz = sp->spi_freq;
 454
 455         return 0;
 456 }
 457
 458 static int mtk_nor_transfer_one_message(struct spi_controller *master,
 459                                         struct spi_message *m)
 460 {
 461         struct mtk_nor *sp = spi_controller_get_devdata(master);
 462         struct spi_transfer *t = NULL;
 463         unsigned long trx_len = 0;
 464         int stat = 0;
 465         int reg_offset = MTK_NOR_REG_PRGDATA_MAX;
 466         void __iomem *reg;
 467         const u8 *txbuf;
 468         u8 *rxbuf;
 469         int i;
 470
 471         list_for_each_entry(t, &m->transfers, transfer_list) {
 472                 txbuf = t->tx_buf;
 473                 for (i = 0; i < t->len; i++, reg_offset--) {
 474                         reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
 475                         if (txbuf)
 476                                 writeb(txbuf[i], reg);
 477                         else
 478                                 writeb(0, reg);
 479                 }
 480                 trx_len += t->len;
 481         }
 482
 483         writel(trx_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
 484
 485         stat = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM,
 486                                 trx_len * BITS_PER_BYTE);
 487         if (stat < 0)
 488                 goto msg_done;
 489
 490         reg_offset = trx_len - 1;
 491         list_for_each_entry(t, &m->transfers, transfer_list) {
 492                 rxbuf = t->rx_buf;
 493                 for (i = 0; i < t->len; i++, reg_offset--) {
 494                         reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset);
 495                         if (rxbuf)
 496                                 rxbuf[i] = readb(reg);
 497                 }
 498         }
 499
 500         m->actual_length = trx_len;
 501 msg_done:
 502         m->status = stat;
 503         spi_finalize_current_message(master);
 504
 505         return 0;
 506 }
 507
 508 static void mtk_nor_disable_clk(struct mtk_nor *sp)
 509 {
 510         clk_disable_unprepare(sp->spi_clk);
 511         clk_disable_unprepare(sp->ctlr_clk);
 512 }
 513
 514 static int mtk_nor_enable_clk(struct mtk_nor *sp)
 515 {
 516         int ret;
 517
 518         ret = clk_prepare_enable(sp->spi_clk);
 519         if (ret)
 520                 return ret;
 521
 522         ret = clk_prepare_enable(sp->ctlr_clk);
 523         if (ret) {
 524                 clk_disable_unprepare(sp->spi_clk);
 525                 return ret;
 526         }
 527
 528         return 0;
 529 }
 530
 531 static int mtk_nor_init(struct mtk_nor *sp)
 532 {
 533         int ret;
 534
 535         ret = mtk_nor_enable_clk(sp);
 536         if (ret)
 537                 return ret;
 538
 539         sp->spi_freq = clk_get_rate(sp->spi_clk);
 540
 541         writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP);
 542         mtk_nor_rmw(sp, MTK_NOR_REG_CFG2, MTK_NOR_WR_CUSTOM_OP_EN, 0);
 543         mtk_nor_rmw(sp, MTK_NOR_REG_CFG3,
 544                     MTK_NOR_DISABLE_WREN | MTK_NOR_DISABLE_SR_POLL, 0);
 545
 546         return ret;
 547 }
 548
 549 static irqreturn_t mtk_nor_irq_handler(int irq, void *data)
 550 {
 551         struct mtk_nor *sp = data;
 552         u32 irq_status, irq_enabled;
 553
 554         irq_status = readl(sp->base + MTK_NOR_REG_IRQ_STAT);
 555         irq_enabled = readl(sp->base + MTK_NOR_REG_IRQ_EN);
 556         // write status back to clear interrupt
 557         writel(irq_status, sp->base + MTK_NOR_REG_IRQ_STAT);
 558
 559         if (!(irq_status & irq_enabled))
 560                 return IRQ_NONE;
 561
 562         if (irq_status & MTK_NOR_IRQ_DMA) {
 563                 complete(&sp->op_done);
 564                 writel(0, sp->base + MTK_NOR_REG_IRQ_EN);
 565         }
 566
 567         return IRQ_HANDLED;
 568 }
 569
 570 static size_t mtk_max_msg_size(struct spi_device *spi)
 571 {
 572         return MTK_NOR_PRG_MAX_SIZE;
 573 }
 574
 575 static const struct spi_controller_mem_ops mtk_nor_mem_ops = {
 576         .adjust_op_size = mtk_nor_adjust_op_size,
 577         .supports_op = mtk_nor_supports_op,
 578         .exec_op = mtk_nor_exec_op
 579 };
 580
 581 static const struct of_device_id mtk_nor_match[] = {
 582         { .compatible = "mediatek,mt8173-nor" },
 583         { /* sentinel */ }
 584 };
 585 MODULE_DEVICE_TABLE(of, mtk_nor_match);
 586
 587 static int mtk_nor_probe(struct platform_device *pdev)
 588 {
 589         struct spi_controller *ctlr;
 590         struct mtk_nor *sp;
 591         void __iomem *base;
 592         u8 *buffer;
 593         struct clk *spi_clk, *ctlr_clk;
 594         int ret, irq;
 595
 596         base = devm_platform_ioremap_resource(pdev, 0);
 597         if (IS_ERR(base))
 598                 return PTR_ERR(base);
 599
 600         spi_clk = devm_clk_get(&pdev->dev, "spi");
 601         if (IS_ERR(spi_clk))
 602                 return PTR_ERR(spi_clk);
 603
 604         ctlr_clk = devm_clk_get(&pdev->dev, "sf");
 605         if (IS_ERR(ctlr_clk))
 606                 return PTR_ERR(ctlr_clk);
 607
 608         buffer = devm_kmalloc(&pdev->dev,
 609                               MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
 610                               GFP_KERNEL);
 611         if (!buffer)
 612                 return -ENOMEM;
 613
 614         if ((ulong)buffer & MTK_NOR_DMA_ALIGN_MASK)
 615                 buffer = (u8 *)(((ulong)buffer + MTK_NOR_DMA_ALIGN) &
 616                                 ~MTK_NOR_DMA_ALIGN_MASK);
 617
 618         ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
 619         if (!ctlr) {
 620                 dev_err(&pdev->dev, "failed to allocate spi controller\n");
 621                 return -ENOMEM;
 622         }
 623
 624         ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
 625         ctlr->dev.of_node = pdev->dev.of_node;
 626         ctlr->max_message_size = mtk_max_msg_size;
 627         ctlr->mem_ops = &mtk_nor_mem_ops;
 628         ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
 629         ctlr->num_chipselect = 1;
 630         ctlr->setup = mtk_nor_setup;
 631         ctlr->transfer_one_message = mtk_nor_transfer_one_message;
 632
 633         dev_set_drvdata(&pdev->dev, ctlr);
 634
 635         sp = spi_controller_get_devdata(ctlr);
 636         sp->base = base;
 637         sp->buffer = buffer;
 638         sp->has_irq = false;
 639         sp->wbuf_en = false;
 640         sp->ctlr = ctlr;
 641         sp->dev = &pdev->dev;
 642         sp->spi_clk = spi_clk;
 643         sp->ctlr_clk = ctlr_clk;
 644
 645         irq = platform_get_irq_optional(pdev, 0);
 646         if (irq < 0) {
 647                 dev_warn(sp->dev, "IRQ not available.");
 648         } else {
 649                 writel(MTK_NOR_IRQ_MASK, base + MTK_NOR_REG_IRQ_STAT);
 650                 writel(0, base + MTK_NOR_REG_IRQ_EN);
 651                 ret = devm_request_irq(sp->dev, irq, mtk_nor_irq_handler, 0,
 652                                        pdev->name, sp);
 653                 if (ret < 0) {
 654                         dev_warn(sp->dev, "failed to request IRQ.");
 655                 } else {
 656                         init_completion(&sp->op_done);
 657                         sp->has_irq = true;
 658                 }
 659         }
 660
 661         ret = mtk_nor_init(sp);
 662         if (ret < 0) {
 663                 kfree(ctlr);
 664                 return ret;
 665         }
 666
 667         dev_info(&pdev->dev, "spi frequency: %d Hz\n", sp->spi_freq);
 668
 669         return devm_spi_register_controller(&pdev->dev, ctlr);
 670 }
 671
 672 static int mtk_nor_remove(struct platform_device *pdev)
 673 {
 674         struct spi_controller *ctlr;
 675         struct mtk_nor *sp;
 676
 677         ctlr = dev_get_drvdata(&pdev->dev);
 678         sp = spi_controller_get_devdata(ctlr);
 679
 680         mtk_nor_disable_clk(sp);
 681
 682         return 0;
 683 }
 684
 685 static struct platform_driver mtk_nor_driver = {
 686         .driver = {
 687                 .name = DRIVER_NAME,
 688                 .of_match_table = mtk_nor_match,
 689         },
 690         .probe = mtk_nor_probe,
 691         .remove = mtk_nor_remove,
 692 };
 693
 694 module_platform_driver(mtk_nor_driver);
 695
 696 MODULE_DESCRIPTION("Mediatek SPI NOR controller driver");
 697 MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
 698 MODULE_LICENSE("GPL v2");
 699 MODULE_ALIAS("platform:" DRIVER_NAME);