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xen/balloon: Fix declared-but-not-defined warning
[linux/fpc-iii.git] / sound / soc / pxa / pxa-ssp.c
blob3cad990dad2cd35e8334ff54ea14632c0319dd8c
1 /*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/pxa2xx_ssp.h>
24 #include <linux/of.h>
25 #include <linux/dmaengine.h>
26
27 #include <asm/irq.h>
28
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/initval.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/pxa2xx-lib.h>
35 #include <sound/dmaengine_pcm.h>
36
37 #include "../../arm/pxa2xx-pcm.h"
38 #include "pxa-ssp.h"
39
40 /*
41 * SSP audio private data
42 */
43 struct ssp_priv {
44 struct ssp_device *ssp;
45 unsigned int sysclk;
46 int dai_fmt;
47 #ifdef CONFIG_PM
48 uint32_t cr0;
49 uint32_t cr1;
50 uint32_t to;
51 uint32_t psp;
52 #endif
53 };
54
55 static void dump_registers(struct ssp_device *ssp)
56 {
57 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
58 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
59 pxa_ssp_read_reg(ssp, SSTO));
60
61 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
62 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
63 pxa_ssp_read_reg(ssp, SSACD));
64 }
65
66 static void pxa_ssp_enable(struct ssp_device *ssp)
67 {
68 uint32_t sscr0;
69
70 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
71 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
72 }
73
74 static void pxa_ssp_disable(struct ssp_device *ssp)
75 {
76 uint32_t sscr0;
77
78 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
79 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
80 }
81
82 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
83 int out, struct snd_dmaengine_dai_dma_data *dma)
84 {
85 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
86 DMA_SLAVE_BUSWIDTH_2_BYTES;
87 dma->maxburst = 16;
88 dma->addr = ssp->phys_base + SSDR;
89 }
90
91 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
92 struct snd_soc_dai *cpu_dai)
93 {
94 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
95 struct ssp_device *ssp = priv->ssp;
96 struct snd_dmaengine_dai_dma_data *dma;
97 int ret = 0;
98
99 if (!cpu_dai->active) {
100 clk_prepare_enable(ssp->clk);
101 pxa_ssp_disable(ssp);
102 }
103
104 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
105 if (!dma)
106 return -ENOMEM;
107
108 dma->filter_data = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
109 &ssp->drcmr_tx : &ssp->drcmr_rx;
110
111 snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
112
113 return ret;
114 }
115
116 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
117 struct snd_soc_dai *cpu_dai)
118 {
119 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
120 struct ssp_device *ssp = priv->ssp;
121
122 if (!cpu_dai->active) {
123 pxa_ssp_disable(ssp);
124 clk_disable_unprepare(ssp->clk);
125 }
126
127 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
128 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
129 }
130
131 #ifdef CONFIG_PM
132
133 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
134 {
135 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
136 struct ssp_device *ssp = priv->ssp;
137
138 if (!cpu_dai->active)
139 clk_prepare_enable(ssp->clk);
140
141 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
142 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
143 priv->to = __raw_readl(ssp->mmio_base + SSTO);
144 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
145
146 pxa_ssp_disable(ssp);
147 clk_disable_unprepare(ssp->clk);
148 return 0;
149 }
150
151 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
152 {
153 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
154 struct ssp_device *ssp = priv->ssp;
155 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
156
157 clk_prepare_enable(ssp->clk);
158
159 __raw_writel(sssr, ssp->mmio_base + SSSR);
160 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
161 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
162 __raw_writel(priv->to, ssp->mmio_base + SSTO);
163 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
164
165 if (cpu_dai->active)
166 pxa_ssp_enable(ssp);
167 else
168 clk_disable_unprepare(ssp->clk);
169
170 return 0;
171 }
172
173 #else
174 #define pxa_ssp_suspend NULL
175 #define pxa_ssp_resume NULL
176 #endif
177
178 /**
179 * ssp_set_clkdiv - set SSP clock divider
180 * @div: serial clock rate divider
181 */
182 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
183 {
184 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
185
186 if (ssp->type == PXA25x_SSP) {
187 sscr0 &= ~0x0000ff00;
188 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
189 } else {
190 sscr0 &= ~0x000fff00;
191 sscr0 |= (div - 1) << 8; /* 1..4096 */
192 }
193 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
194 }
195
196 /**
197 * pxa_ssp_get_clkdiv - get SSP clock divider
198 */
199 static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
200 {
201 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
202 u32 div;
203
204 if (ssp->type == PXA25x_SSP)
205 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
206 else
207 div = ((sscr0 >> 8) & 0xfff) + 1;
208 return div;
209 }
210
211 /*
212 * Set the SSP ports SYSCLK.
213 */
214 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
215 int clk_id, unsigned int freq, int dir)
216 {
217 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
218 struct ssp_device *ssp = priv->ssp;
219 int val;
220
221 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
222 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
223
224 dev_dbg(&ssp->pdev->dev,
225 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
226 cpu_dai->id, clk_id, freq);
227
228 switch (clk_id) {
229 case PXA_SSP_CLK_NET_PLL:
230 sscr0 |= SSCR0_MOD;
231 break;
232 case PXA_SSP_CLK_PLL:
233 /* Internal PLL is fixed */
234 if (ssp->type == PXA25x_SSP)
235 priv->sysclk = 1843200;
236 else
237 priv->sysclk = 13000000;
238 break;
239 case PXA_SSP_CLK_EXT:
240 priv->sysclk = freq;
241 sscr0 |= SSCR0_ECS;
242 break;
243 case PXA_SSP_CLK_NET:
244 priv->sysclk = freq;
245 sscr0 |= SSCR0_NCS | SSCR0_MOD;
246 break;
247 case PXA_SSP_CLK_AUDIO:
248 priv->sysclk = 0;
249 pxa_ssp_set_scr(ssp, 1);
250 sscr0 |= SSCR0_ACS;
251 break;
252 default:
253 return -ENODEV;
254 }
255
256 /* The SSP clock must be disabled when changing SSP clock mode
257 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
258 if (ssp->type != PXA3xx_SSP)
259 clk_disable_unprepare(ssp->clk);
260 val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
261 pxa_ssp_write_reg(ssp, SSCR0, val);
262 if (ssp->type != PXA3xx_SSP)
263 clk_prepare_enable(ssp->clk);
264
265 return 0;
266 }
267
268 /*
269 * Set the SSP clock dividers.
270 */
271 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
272 int div_id, int div)
273 {
274 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
275 struct ssp_device *ssp = priv->ssp;
276 int val;
277
278 switch (div_id) {
279 case PXA_SSP_AUDIO_DIV_ACDS:
280 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
281 pxa_ssp_write_reg(ssp, SSACD, val);
282 break;
283 case PXA_SSP_AUDIO_DIV_SCDB:
284 val = pxa_ssp_read_reg(ssp, SSACD);
285 val &= ~SSACD_SCDB;
286 if (ssp->type == PXA3xx_SSP)
287 val &= ~SSACD_SCDX8;
288 switch (div) {
289 case PXA_SSP_CLK_SCDB_1:
290 val |= SSACD_SCDB;
291 break;
292 case PXA_SSP_CLK_SCDB_4:
293 break;
294 case PXA_SSP_CLK_SCDB_8:
295 if (ssp->type == PXA3xx_SSP)
296 val |= SSACD_SCDX8;
297 else
298 return -EINVAL;
299 break;
300 default:
301 return -EINVAL;
302 }
303 pxa_ssp_write_reg(ssp, SSACD, val);
304 break;
305 case PXA_SSP_DIV_SCR:
306 pxa_ssp_set_scr(ssp, div);
307 break;
308 default:
309 return -ENODEV;
310 }
311
312 return 0;
313 }
314
315 /*
316 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
317 */
318 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
319 int source, unsigned int freq_in, unsigned int freq_out)
320 {
321 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
322 struct ssp_device *ssp = priv->ssp;
323 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
324
325 if (ssp->type == PXA3xx_SSP)
326 pxa_ssp_write_reg(ssp, SSACDD, 0);
327
328 switch (freq_out) {
329 case 5622000:
330 break;
331 case 11345000:
332 ssacd |= (0x1 << 4);
333 break;
334 case 12235000:
335 ssacd |= (0x2 << 4);
336 break;
337 case 14857000:
338 ssacd |= (0x3 << 4);
339 break;
340 case 32842000:
341 ssacd |= (0x4 << 4);
342 break;
343 case 48000000:
344 ssacd |= (0x5 << 4);
345 break;
346 case 0:
347 /* Disable */
348 break;
349
350 default:
351 /* PXA3xx has a clock ditherer which can be used to generate
352 * a wider range of frequencies - calculate a value for it.
353 */
354 if (ssp->type == PXA3xx_SSP) {
355 u32 val;
356 u64 tmp = 19968;
357 tmp *= 1000000;
358 do_div(tmp, freq_out);
359 val = tmp;
360
361 val = (val << 16) | 64;
362 pxa_ssp_write_reg(ssp, SSACDD, val);
363
364 ssacd |= (0x6 << 4);
365
366 dev_dbg(&ssp->pdev->dev,
367 "Using SSACDD %x to supply %uHz\n",
368 val, freq_out);
369 break;
370 }
371
372 return -EINVAL;
373 }
374
375 pxa_ssp_write_reg(ssp, SSACD, ssacd);
376
377 return 0;
378 }
379
380 /*
381 * Set the active slots in TDM/Network mode
382 */
383 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
384 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
385 {
386 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
387 struct ssp_device *ssp = priv->ssp;
388 u32 sscr0;
389
390 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
391 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
392
393 /* set slot width */
394 if (slot_width > 16)
395 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
396 else
397 sscr0 |= SSCR0_DataSize(slot_width);
398
399 if (slots > 1) {
400 /* enable network mode */
401 sscr0 |= SSCR0_MOD;
402
403 /* set number of active slots */
404 sscr0 |= SSCR0_SlotsPerFrm(slots);
405
406 /* set active slot mask */
407 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
408 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
409 }
410 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
411
412 return 0;
413 }
414
415 /*
416 * Tristate the SSP DAI lines
417 */
418 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
419 int tristate)
420 {
421 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
422 struct ssp_device *ssp = priv->ssp;
423 u32 sscr1;
424
425 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
426 if (tristate)
427 sscr1 &= ~SSCR1_TTE;
428 else
429 sscr1 |= SSCR1_TTE;
430 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
431
432 return 0;
433 }
434
435 /*
436 * Set up the SSP DAI format.
437 * The SSP Port must be inactive before calling this function as the
438 * physical interface format is changed.
439 */
440 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
441 unsigned int fmt)
442 {
443 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
444 struct ssp_device *ssp = priv->ssp;
445 u32 sscr0, sscr1, sspsp, scfr;
446
447 /* check if we need to change anything at all */
448 if (priv->dai_fmt == fmt)
449 return 0;
450
451 /* we can only change the settings if the port is not in use */
452 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
453 dev_err(&ssp->pdev->dev,
454 "can't change hardware dai format: stream is in use");
455 return -EINVAL;
456 }
457
458 /* reset port settings */
459 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
460 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
461 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
462 sspsp = 0;
463
464 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
465 case SND_SOC_DAIFMT_CBM_CFM:
466 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
467 break;
468 case SND_SOC_DAIFMT_CBM_CFS:
469 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
470 break;
471 case SND_SOC_DAIFMT_CBS_CFS:
472 break;
473 default:
474 return -EINVAL;
475 }
476
477 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
478 case SND_SOC_DAIFMT_NB_NF:
479 sspsp |= SSPSP_SFRMP;
480 break;
481 case SND_SOC_DAIFMT_NB_IF:
482 break;
483 case SND_SOC_DAIFMT_IB_IF:
484 sspsp |= SSPSP_SCMODE(2);
485 break;
486 case SND_SOC_DAIFMT_IB_NF:
487 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
494 case SND_SOC_DAIFMT_I2S:
495 sscr0 |= SSCR0_PSP;
496 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
497 /* See hw_params() */
498 break;
499
500 case SND_SOC_DAIFMT_DSP_A:
501 sspsp |= SSPSP_FSRT;
502 case SND_SOC_DAIFMT_DSP_B:
503 sscr0 |= SSCR0_MOD | SSCR0_PSP;
504 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
505 break;
506
507 default:
508 return -EINVAL;
509 }
510
511 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
512 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
513 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
514
515 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
516 case SND_SOC_DAIFMT_CBM_CFM:
517 case SND_SOC_DAIFMT_CBM_CFS:
518 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
519 pxa_ssp_write_reg(ssp, SSCR1, scfr);
520
521 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
522 cpu_relax();
523 break;
524 }
525
526 dump_registers(ssp);
527
528 /* Since we are configuring the timings for the format by hand
529 * we have to defer some things until hw_params() where we
530 * know parameters like the sample size.
531 */
532 priv->dai_fmt = fmt;
533
534 return 0;
535 }
536
537 /*
538 * Set the SSP audio DMA parameters and sample size.
539 * Can be called multiple times by oss emulation.
540 */
541 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
542 struct snd_pcm_hw_params *params,
543 struct snd_soc_dai *cpu_dai)
544 {
545 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
546 struct ssp_device *ssp = priv->ssp;
547 int chn = params_channels(params);
548 u32 sscr0;
549 u32 sspsp;
550 int width = snd_pcm_format_physical_width(params_format(params));
551 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
552 struct snd_dmaengine_dai_dma_data *dma_data;
553
554 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
555
556 /* Network mode with one active slot (ttsa == 1) can be used
557 * to force 16-bit frame width on the wire (for S16_LE), even
558 * with two channels. Use 16-bit DMA transfers for this case.
559 */
560 pxa_ssp_set_dma_params(ssp,
561 ((chn == 2) && (ttsa != 1)) || (width == 32),
562 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
563
564 /* we can only change the settings if the port is not in use */
565 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
566 return 0;
567
568 /* clear selected SSP bits */
569 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
570
571 /* bit size */
572 switch (params_format(params)) {
573 case SNDRV_PCM_FORMAT_S16_LE:
574 if (ssp->type == PXA3xx_SSP)
575 sscr0 |= SSCR0_FPCKE;
576 sscr0 |= SSCR0_DataSize(16);
577 break;
578 case SNDRV_PCM_FORMAT_S24_LE:
579 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
580 break;
581 case SNDRV_PCM_FORMAT_S32_LE:
582 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
583 break;
584 }
585 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
586
587 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
588 case SND_SOC_DAIFMT_I2S:
589 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
590
591 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
592 /* This is a special case where the bitclk is 64fs
593 * and we're not dealing with 2*32 bits of audio
594 * samples.
595 *
596 * The SSP values used for that are all found out by
597 * trying and failing a lot; some of the registers
598 * needed for that mode are only available on PXA3xx.
599 */
600 if (ssp->type != PXA3xx_SSP)
601 return -EINVAL;
602
603 sspsp |= SSPSP_SFRMWDTH(width * 2);
604 sspsp |= SSPSP_SFRMDLY(width * 4);
605 sspsp |= SSPSP_EDMYSTOP(3);
606 sspsp |= SSPSP_DMYSTOP(3);
607 sspsp |= SSPSP_DMYSTRT(1);
608 } else {
609 /* The frame width is the width the LRCLK is
610 * asserted for; the delay is expressed in
611 * half cycle units. We need the extra cycle
612 * because the data starts clocking out one BCLK
613 * after LRCLK changes polarity.
614 */
615 sspsp |= SSPSP_SFRMWDTH(width + 1);
616 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
617 sspsp |= SSPSP_DMYSTRT(1);
618 }
619
620 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
621 break;
622 default:
623 break;
624 }
625
626 /* When we use a network mode, we always require TDM slots
627 * - complain loudly and fail if they've not been set up yet.
628 */
629 if ((sscr0 & SSCR0_MOD) && !ttsa) {
630 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
631 return -EINVAL;
632 }
633
634 dump_registers(ssp);
635
636 return 0;
637 }
638
639 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
640 struct ssp_device *ssp, int value)
641 {
642 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
643 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
644 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
645 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
646
647 if (value && (sscr0 & SSCR0_SSE))
648 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
649
650 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
651 if (value)
652 sscr1 |= SSCR1_TSRE;
653 else
654 sscr1 &= ~SSCR1_TSRE;
655 } else {
656 if (value)
657 sscr1 |= SSCR1_RSRE;
658 else
659 sscr1 &= ~SSCR1_RSRE;
660 }
661
662 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
663
664 if (value) {
665 pxa_ssp_write_reg(ssp, SSSR, sssr);
666 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
667 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
668 }
669 }
670
671 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
672 struct snd_soc_dai *cpu_dai)
673 {
674 int ret = 0;
675 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
676 struct ssp_device *ssp = priv->ssp;
677 int val;
678
679 switch (cmd) {
680 case SNDRV_PCM_TRIGGER_RESUME:
681 pxa_ssp_enable(ssp);
682 break;
683 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
684 pxa_ssp_set_running_bit(substream, ssp, 1);
685 val = pxa_ssp_read_reg(ssp, SSSR);
686 pxa_ssp_write_reg(ssp, SSSR, val);
687 break;
688 case SNDRV_PCM_TRIGGER_START:
689 pxa_ssp_set_running_bit(substream, ssp, 1);
690 break;
691 case SNDRV_PCM_TRIGGER_STOP:
692 pxa_ssp_set_running_bit(substream, ssp, 0);
693 break;
694 case SNDRV_PCM_TRIGGER_SUSPEND:
695 pxa_ssp_disable(ssp);
696 break;
697 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
698 pxa_ssp_set_running_bit(substream, ssp, 0);
699 break;
700
701 default:
702 ret = -EINVAL;
703 }
704
705 dump_registers(ssp);
706
707 return ret;
708 }
709
710 static int pxa_ssp_probe(struct snd_soc_dai *dai)
711 {
712 struct device *dev = dai->dev;
713 struct ssp_priv *priv;
714 int ret;
715
716 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
717 if (!priv)
718 return -ENOMEM;
719
720 if (dev->of_node) {
721 struct device_node *ssp_handle;
722
723 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
724 if (!ssp_handle) {
725 dev_err(dev, "unable to get 'port' phandle\n");
726 ret = -ENODEV;
727 goto err_priv;
728 }
729
730 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
731 if (priv->ssp == NULL) {
732 ret = -ENODEV;
733 goto err_priv;
734 }
735 } else {
736 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
737 if (priv->ssp == NULL) {
738 ret = -ENODEV;
739 goto err_priv;
740 }
741 }
742
743 priv->dai_fmt = (unsigned int) -1;
744 snd_soc_dai_set_drvdata(dai, priv);
745
746 return 0;
747
748 err_priv:
749 kfree(priv);
750 return ret;
751 }
752
753 static int pxa_ssp_remove(struct snd_soc_dai *dai)
754 {
755 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
756
757 pxa_ssp_free(priv->ssp);
758 kfree(priv);
759 return 0;
760 }
761
762 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
763 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
764 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
765 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
766 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
767
768 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
769
770 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
771 .startup = pxa_ssp_startup,
772 .shutdown = pxa_ssp_shutdown,
773 .trigger = pxa_ssp_trigger,
774 .hw_params = pxa_ssp_hw_params,
775 .set_sysclk = pxa_ssp_set_dai_sysclk,
776 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
777 .set_pll = pxa_ssp_set_dai_pll,
778 .set_fmt = pxa_ssp_set_dai_fmt,
779 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
780 .set_tristate = pxa_ssp_set_dai_tristate,
781 };
782
783 static struct snd_soc_dai_driver pxa_ssp_dai = {
784 .probe = pxa_ssp_probe,
785 .remove = pxa_ssp_remove,
786 .suspend = pxa_ssp_suspend,
787 .resume = pxa_ssp_resume,
788 .playback = {
789 .channels_min = 1,
790 .channels_max = 8,
791 .rates = PXA_SSP_RATES,
792 .formats = PXA_SSP_FORMATS,
793 },
794 .capture = {
795 .channels_min = 1,
796 .channels_max = 8,
797 .rates = PXA_SSP_RATES,
798 .formats = PXA_SSP_FORMATS,
799 },
800 .ops = &pxa_ssp_dai_ops,
801 };
802
803 static const struct snd_soc_component_driver pxa_ssp_component = {
804 .name = "pxa-ssp",
805 };
806
807 #ifdef CONFIG_OF
808 static const struct of_device_id pxa_ssp_of_ids[] = {
809 { .compatible = "mrvl,pxa-ssp-dai" },
810 {}
811 };
812 MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
813 #endif
814
815 static int asoc_ssp_probe(struct platform_device *pdev)
816 {
817 return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
818 &pxa_ssp_dai, 1);
819 }
820
821 static struct platform_driver asoc_ssp_driver = {
822 .driver = {
823 .name = "pxa-ssp-dai",
824 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
825 },
826
827 .probe = asoc_ssp_probe,
828 };
829
830 module_platform_driver(asoc_ssp_driver);
831
832 /* Module information */
833 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
834 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
835 MODULE_LICENSE("GPL");
836 MODULE_ALIAS("platform:pxa-ssp-dai");
Linux with added FPC-III support