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OMAP: DSS2: fix irq-stats compilation
[linux/fpc-iii.git] / arch / sh / kernel / cpu / sh4a / setup-sh7724.c
blobd32f96c1cc15f9ed7d911bfd4e28474f731661d7
1 /*
2 * SH7724 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15 #include <linux/platform_device.h>
16 #include <linux/init.h>
17 #include <linux/serial.h>
18 #include <linux/mm.h>
19 #include <linux/serial_sci.h>
20 #include <linux/uio_driver.h>
21 #include <linux/sh_timer.h>
22 #include <linux/io.h>
23 #include <linux/notifier.h>
24 #include <asm/suspend.h>
25 #include <asm/clock.h>
26 #include <asm/dma-sh.h>
27 #include <asm/mmzone.h>
28 #include <cpu/sh7724.h>
29
30 /* DMA */
31 static struct sh_dmae_pdata dma_platform_data = {
32 .mode = SHDMA_DMAOR1,
33 };
34
35 static struct platform_device dma_device = {
36 .name = "sh-dma-engine",
37 .id = -1,
38 .dev = {
39 .platform_data = &dma_platform_data,
40 },
41 };
42
43 /* Serial */
44 static struct plat_sci_port scif0_platform_data = {
45 .mapbase = 0xffe00000,
46 .flags = UPF_BOOT_AUTOCONF,
47 .type = PORT_SCIF,
48 .irqs = { 80, 80, 80, 80 },
49 .clk = "scif0",
50 };
51
52 static struct platform_device scif0_device = {
53 .name = "sh-sci",
54 .id = 0,
55 .dev = {
56 .platform_data = &scif0_platform_data,
57 },
58 };
59
60 static struct plat_sci_port scif1_platform_data = {
61 .mapbase = 0xffe10000,
62 .flags = UPF_BOOT_AUTOCONF,
63 .type = PORT_SCIF,
64 .irqs = { 81, 81, 81, 81 },
65 .clk = "scif1",
66 };
67
68 static struct platform_device scif1_device = {
69 .name = "sh-sci",
70 .id = 1,
71 .dev = {
72 .platform_data = &scif1_platform_data,
73 },
74 };
75
76 static struct plat_sci_port scif2_platform_data = {
77 .mapbase = 0xffe20000,
78 .flags = UPF_BOOT_AUTOCONF,
79 .type = PORT_SCIF,
80 .irqs = { 82, 82, 82, 82 },
81 .clk = "scif2",
82 };
83
84 static struct platform_device scif2_device = {
85 .name = "sh-sci",
86 .id = 2,
87 .dev = {
88 .platform_data = &scif2_platform_data,
89 },
90 };
91
92 static struct plat_sci_port scif3_platform_data = {
93 .mapbase = 0xa4e30000,
94 .flags = UPF_BOOT_AUTOCONF,
95 .type = PORT_SCIFA,
96 .irqs = { 56, 56, 56, 56 },
97 .clk = "scif3",
98 };
99
100 static struct platform_device scif3_device = {
101 .name = "sh-sci",
102 .id = 3,
103 .dev = {
104 .platform_data = &scif3_platform_data,
105 },
106 };
107
108 static struct plat_sci_port scif4_platform_data = {
109 .mapbase = 0xa4e40000,
110 .flags = UPF_BOOT_AUTOCONF,
111 .type = PORT_SCIFA,
112 .irqs = { 88, 88, 88, 88 },
113 .clk = "scif4",
114 };
115
116 static struct platform_device scif4_device = {
117 .name = "sh-sci",
118 .id = 4,
119 .dev = {
120 .platform_data = &scif4_platform_data,
121 },
122 };
123
124 static struct plat_sci_port scif5_platform_data = {
125 .mapbase = 0xa4e50000,
126 .flags = UPF_BOOT_AUTOCONF,
127 .type = PORT_SCIFA,
128 .irqs = { 109, 109, 109, 109 },
129 .clk = "scif5",
130 };
131
132 static struct platform_device scif5_device = {
133 .name = "sh-sci",
134 .id = 5,
135 .dev = {
136 .platform_data = &scif5_platform_data,
137 },
138 };
139
140 /* RTC */
141 static struct resource rtc_resources[] = {
142 [0] = {
143 .start = 0xa465fec0,
144 .end = 0xa465fec0 + 0x58 - 1,
145 .flags = IORESOURCE_IO,
146 },
147 [1] = {
148 /* Period IRQ */
149 .start = 69,
150 .flags = IORESOURCE_IRQ,
151 },
152 [2] = {
153 /* Carry IRQ */
154 .start = 70,
155 .flags = IORESOURCE_IRQ,
156 },
157 [3] = {
158 /* Alarm IRQ */
159 .start = 68,
160 .flags = IORESOURCE_IRQ,
161 },
162 };
163
164 static struct platform_device rtc_device = {
165 .name = "sh-rtc",
166 .id = -1,
167 .num_resources = ARRAY_SIZE(rtc_resources),
168 .resource = rtc_resources,
169 .archdata = {
170 .hwblk_id = HWBLK_RTC,
171 },
172 };
173
174 /* I2C0 */
175 static struct resource iic0_resources[] = {
176 [0] = {
177 .name = "IIC0",
178 .start = 0x04470000,
179 .end = 0x04470018 - 1,
180 .flags = IORESOURCE_MEM,
181 },
182 [1] = {
183 .start = 96,
184 .end = 99,
185 .flags = IORESOURCE_IRQ,
186 },
187 };
188
189 static struct platform_device iic0_device = {
190 .name = "i2c-sh_mobile",
191 .id = 0, /* "i2c0" clock */
192 .num_resources = ARRAY_SIZE(iic0_resources),
193 .resource = iic0_resources,
194 .archdata = {
195 .hwblk_id = HWBLK_IIC0,
196 },
197 };
198
199 /* I2C1 */
200 static struct resource iic1_resources[] = {
201 [0] = {
202 .name = "IIC1",
203 .start = 0x04750000,
204 .end = 0x04750018 - 1,
205 .flags = IORESOURCE_MEM,
206 },
207 [1] = {
208 .start = 92,
209 .end = 95,
210 .flags = IORESOURCE_IRQ,
211 },
212 };
213
214 static struct platform_device iic1_device = {
215 .name = "i2c-sh_mobile",
216 .id = 1, /* "i2c1" clock */
217 .num_resources = ARRAY_SIZE(iic1_resources),
218 .resource = iic1_resources,
219 .archdata = {
220 .hwblk_id = HWBLK_IIC1,
221 },
222 };
223
224 /* VPU */
225 static struct uio_info vpu_platform_data = {
226 .name = "VPU5F",
227 .version = "0",
228 .irq = 60,
229 };
230
231 static struct resource vpu_resources[] = {
232 [0] = {
233 .name = "VPU",
234 .start = 0xfe900000,
235 .end = 0xfe902807,
236 .flags = IORESOURCE_MEM,
237 },
238 [1] = {
239 /* place holder for contiguous memory */
240 },
241 };
242
243 static struct platform_device vpu_device = {
244 .name = "uio_pdrv_genirq",
245 .id = 0,
246 .dev = {
247 .platform_data = &vpu_platform_data,
248 },
249 .resource = vpu_resources,
250 .num_resources = ARRAY_SIZE(vpu_resources),
251 .archdata = {
252 .hwblk_id = HWBLK_VPU,
253 },
254 };
255
256 /* VEU0 */
257 static struct uio_info veu0_platform_data = {
258 .name = "VEU3F0",
259 .version = "0",
260 .irq = 83,
261 };
262
263 static struct resource veu0_resources[] = {
264 [0] = {
265 .name = "VEU3F0",
266 .start = 0xfe920000,
267 .end = 0xfe9200cb,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 /* place holder for contiguous memory */
272 },
273 };
274
275 static struct platform_device veu0_device = {
276 .name = "uio_pdrv_genirq",
277 .id = 1,
278 .dev = {
279 .platform_data = &veu0_platform_data,
280 },
281 .resource = veu0_resources,
282 .num_resources = ARRAY_SIZE(veu0_resources),
283 .archdata = {
284 .hwblk_id = HWBLK_VEU0,
285 },
286 };
287
288 /* VEU1 */
289 static struct uio_info veu1_platform_data = {
290 .name = "VEU3F1",
291 .version = "0",
292 .irq = 54,
293 };
294
295 static struct resource veu1_resources[] = {
296 [0] = {
297 .name = "VEU3F1",
298 .start = 0xfe924000,
299 .end = 0xfe9240cb,
300 .flags = IORESOURCE_MEM,
301 },
302 [1] = {
303 /* place holder for contiguous memory */
304 },
305 };
306
307 static struct platform_device veu1_device = {
308 .name = "uio_pdrv_genirq",
309 .id = 2,
310 .dev = {
311 .platform_data = &veu1_platform_data,
312 },
313 .resource = veu1_resources,
314 .num_resources = ARRAY_SIZE(veu1_resources),
315 .archdata = {
316 .hwblk_id = HWBLK_VEU1,
317 },
318 };
319
320 static struct sh_timer_config cmt_platform_data = {
321 .name = "CMT",
322 .channel_offset = 0x60,
323 .timer_bit = 5,
324 .clk = "cmt0",
325 .clockevent_rating = 125,
326 .clocksource_rating = 200,
327 };
328
329 static struct resource cmt_resources[] = {
330 [0] = {
331 .name = "CMT",
332 .start = 0x044a0060,
333 .end = 0x044a006b,
334 .flags = IORESOURCE_MEM,
335 },
336 [1] = {
337 .start = 104,
338 .flags = IORESOURCE_IRQ,
339 },
340 };
341
342 static struct platform_device cmt_device = {
343 .name = "sh_cmt",
344 .id = 0,
345 .dev = {
346 .platform_data = &cmt_platform_data,
347 },
348 .resource = cmt_resources,
349 .num_resources = ARRAY_SIZE(cmt_resources),
350 .archdata = {
351 .hwblk_id = HWBLK_CMT,
352 },
353 };
354
355 static struct sh_timer_config tmu0_platform_data = {
356 .name = "TMU0",
357 .channel_offset = 0x04,
358 .timer_bit = 0,
359 .clk = "tmu0",
360 .clockevent_rating = 200,
361 };
362
363 static struct resource tmu0_resources[] = {
364 [0] = {
365 .name = "TMU0",
366 .start = 0xffd80008,
367 .end = 0xffd80013,
368 .flags = IORESOURCE_MEM,
369 },
370 [1] = {
371 .start = 16,
372 .flags = IORESOURCE_IRQ,
373 },
374 };
375
376 static struct platform_device tmu0_device = {
377 .name = "sh_tmu",
378 .id = 0,
379 .dev = {
380 .platform_data = &tmu0_platform_data,
381 },
382 .resource = tmu0_resources,
383 .num_resources = ARRAY_SIZE(tmu0_resources),
384 .archdata = {
385 .hwblk_id = HWBLK_TMU0,
386 },
387 };
388
389 static struct sh_timer_config tmu1_platform_data = {
390 .name = "TMU1",
391 .channel_offset = 0x10,
392 .timer_bit = 1,
393 .clk = "tmu0",
394 .clocksource_rating = 200,
395 };
396
397 static struct resource tmu1_resources[] = {
398 [0] = {
399 .name = "TMU1",
400 .start = 0xffd80014,
401 .end = 0xffd8001f,
402 .flags = IORESOURCE_MEM,
403 },
404 [1] = {
405 .start = 17,
406 .flags = IORESOURCE_IRQ,
407 },
408 };
409
410 static struct platform_device tmu1_device = {
411 .name = "sh_tmu",
412 .id = 1,
413 .dev = {
414 .platform_data = &tmu1_platform_data,
415 },
416 .resource = tmu1_resources,
417 .num_resources = ARRAY_SIZE(tmu1_resources),
418 .archdata = {
419 .hwblk_id = HWBLK_TMU0,
420 },
421 };
422
423 static struct sh_timer_config tmu2_platform_data = {
424 .name = "TMU2",
425 .channel_offset = 0x1c,
426 .timer_bit = 2,
427 .clk = "tmu0",
428 };
429
430 static struct resource tmu2_resources[] = {
431 [0] = {
432 .name = "TMU2",
433 .start = 0xffd80020,
434 .end = 0xffd8002b,
435 .flags = IORESOURCE_MEM,
436 },
437 [1] = {
438 .start = 18,
439 .flags = IORESOURCE_IRQ,
440 },
441 };
442
443 static struct platform_device tmu2_device = {
444 .name = "sh_tmu",
445 .id = 2,
446 .dev = {
447 .platform_data = &tmu2_platform_data,
448 },
449 .resource = tmu2_resources,
450 .num_resources = ARRAY_SIZE(tmu2_resources),
451 .archdata = {
452 .hwblk_id = HWBLK_TMU0,
453 },
454 };
455
456
457 static struct sh_timer_config tmu3_platform_data = {
458 .name = "TMU3",
459 .channel_offset = 0x04,
460 .timer_bit = 0,
461 .clk = "tmu1",
462 };
463
464 static struct resource tmu3_resources[] = {
465 [0] = {
466 .name = "TMU3",
467 .start = 0xffd90008,
468 .end = 0xffd90013,
469 .flags = IORESOURCE_MEM,
470 },
471 [1] = {
472 .start = 57,
473 .flags = IORESOURCE_IRQ,
474 },
475 };
476
477 static struct platform_device tmu3_device = {
478 .name = "sh_tmu",
479 .id = 3,
480 .dev = {
481 .platform_data = &tmu3_platform_data,
482 },
483 .resource = tmu3_resources,
484 .num_resources = ARRAY_SIZE(tmu3_resources),
485 .archdata = {
486 .hwblk_id = HWBLK_TMU1,
487 },
488 };
489
490 static struct sh_timer_config tmu4_platform_data = {
491 .name = "TMU4",
492 .channel_offset = 0x10,
493 .timer_bit = 1,
494 .clk = "tmu1",
495 };
496
497 static struct resource tmu4_resources[] = {
498 [0] = {
499 .name = "TMU4",
500 .start = 0xffd90014,
501 .end = 0xffd9001f,
502 .flags = IORESOURCE_MEM,
503 },
504 [1] = {
505 .start = 58,
506 .flags = IORESOURCE_IRQ,
507 },
508 };
509
510 static struct platform_device tmu4_device = {
511 .name = "sh_tmu",
512 .id = 4,
513 .dev = {
514 .platform_data = &tmu4_platform_data,
515 },
516 .resource = tmu4_resources,
517 .num_resources = ARRAY_SIZE(tmu4_resources),
518 .archdata = {
519 .hwblk_id = HWBLK_TMU1,
520 },
521 };
522
523 static struct sh_timer_config tmu5_platform_data = {
524 .name = "TMU5",
525 .channel_offset = 0x1c,
526 .timer_bit = 2,
527 .clk = "tmu1",
528 };
529
530 static struct resource tmu5_resources[] = {
531 [0] = {
532 .name = "TMU5",
533 .start = 0xffd90020,
534 .end = 0xffd9002b,
535 .flags = IORESOURCE_MEM,
536 },
537 [1] = {
538 .start = 57,
539 .flags = IORESOURCE_IRQ,
540 },
541 };
542
543 static struct platform_device tmu5_device = {
544 .name = "sh_tmu",
545 .id = 5,
546 .dev = {
547 .platform_data = &tmu5_platform_data,
548 },
549 .resource = tmu5_resources,
550 .num_resources = ARRAY_SIZE(tmu5_resources),
551 .archdata = {
552 .hwblk_id = HWBLK_TMU1,
553 },
554 };
555
556 /* JPU */
557 static struct uio_info jpu_platform_data = {
558 .name = "JPU",
559 .version = "0",
560 .irq = 27,
561 };
562
563 static struct resource jpu_resources[] = {
564 [0] = {
565 .name = "JPU",
566 .start = 0xfe980000,
567 .end = 0xfe9902d3,
568 .flags = IORESOURCE_MEM,
569 },
570 [1] = {
571 /* place holder for contiguous memory */
572 },
573 };
574
575 static struct platform_device jpu_device = {
576 .name = "uio_pdrv_genirq",
577 .id = 3,
578 .dev = {
579 .platform_data = &jpu_platform_data,
580 },
581 .resource = jpu_resources,
582 .num_resources = ARRAY_SIZE(jpu_resources),
583 .archdata = {
584 .hwblk_id = HWBLK_JPU,
585 },
586 };
587
588 /* SPU2DSP0 */
589 static struct uio_info spu0_platform_data = {
590 .name = "SPU2DSP0",
591 .version = "0",
592 .irq = 86,
593 };
594
595 static struct resource spu0_resources[] = {
596 [0] = {
597 .name = "SPU2DSP0",
598 .start = 0xFE200000,
599 .end = 0xFE2FFFFF,
600 .flags = IORESOURCE_MEM,
601 },
602 [1] = {
603 /* place holder for contiguous memory */
604 },
605 };
606
607 static struct platform_device spu0_device = {
608 .name = "uio_pdrv_genirq",
609 .id = 4,
610 .dev = {
611 .platform_data = &spu0_platform_data,
612 },
613 .resource = spu0_resources,
614 .num_resources = ARRAY_SIZE(spu0_resources),
615 .archdata = {
616 .hwblk_id = HWBLK_SPU,
617 },
618 };
619
620 /* SPU2DSP1 */
621 static struct uio_info spu1_platform_data = {
622 .name = "SPU2DSP1",
623 .version = "0",
624 .irq = 87,
625 };
626
627 static struct resource spu1_resources[] = {
628 [0] = {
629 .name = "SPU2DSP1",
630 .start = 0xFE300000,
631 .end = 0xFE3FFFFF,
632 .flags = IORESOURCE_MEM,
633 },
634 [1] = {
635 /* place holder for contiguous memory */
636 },
637 };
638
639 static struct platform_device spu1_device = {
640 .name = "uio_pdrv_genirq",
641 .id = 5,
642 .dev = {
643 .platform_data = &spu1_platform_data,
644 },
645 .resource = spu1_resources,
646 .num_resources = ARRAY_SIZE(spu1_resources),
647 .archdata = {
648 .hwblk_id = HWBLK_SPU,
649 },
650 };
651
652 static struct platform_device *sh7724_devices[] __initdata = {
653 &scif0_device,
654 &scif1_device,
655 &scif2_device,
656 &scif3_device,
657 &scif4_device,
658 &scif5_device,
659 &cmt_device,
660 &tmu0_device,
661 &tmu1_device,
662 &tmu2_device,
663 &tmu3_device,
664 &tmu4_device,
665 &tmu5_device,
666 &dma_device,
667 &rtc_device,
668 &iic0_device,
669 &iic1_device,
670 &vpu_device,
671 &veu0_device,
672 &veu1_device,
673 &jpu_device,
674 &spu0_device,
675 &spu1_device,
676 };
677
678 static int __init sh7724_devices_setup(void)
679 {
680 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
681 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
682 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
683 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
684 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
685 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
686
687 return platform_add_devices(sh7724_devices,
688 ARRAY_SIZE(sh7724_devices));
689 }
690 arch_initcall(sh7724_devices_setup);
691
692 static struct platform_device *sh7724_early_devices[] __initdata = {
693 &scif0_device,
694 &scif1_device,
695 &scif2_device,
696 &scif3_device,
697 &scif4_device,
698 &scif5_device,
699 &cmt_device,
700 &tmu0_device,
701 &tmu1_device,
702 &tmu2_device,
703 &tmu3_device,
704 &tmu4_device,
705 &tmu5_device,
706 };
707
708 void __init plat_early_device_setup(void)
709 {
710 early_platform_add_devices(sh7724_early_devices,
711 ARRAY_SIZE(sh7724_early_devices));
712 }
713
714 #define RAMCR_CACHE_L2FC 0x0002
715 #define RAMCR_CACHE_L2E 0x0001
716 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
717 void __uses_jump_to_uncached l2_cache_init(void)
718 {
719 /* Enable L2 cache */
720 ctrl_outl(L2_CACHE_ENABLE, RAMCR);
721 }
722
723 enum {
724 UNUSED = 0,
725
726 /* interrupt sources */
727 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
728 HUDI,
729 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
730 _2DG_TRI, _2DG_INI, _2DG_CEI,
731 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
732 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
733 SCIFA3,
734 VPU,
735 TPU,
736 CEU1,
737 BEU1,
738 USB0, USB1,
739 ATAPI,
740 RTC_ATI, RTC_PRI, RTC_CUI,
741 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
742 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
743 KEYSC,
744 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
745 VEU0,
746 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
747 SPU_SPUI0, SPU_SPUI1,
748 SCIFA4,
749 ICB,
750 ETHI,
751 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
752 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
753 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
754 CMT,
755 TSIF,
756 FSI,
757 SCIFA5,
758 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
759 IRDA,
760 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
761 JPU,
762 _2DDMAC,
763 MMC_MMC2I, MMC_MMC3I,
764 LCDC,
765 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
766
767 /* interrupt groups */
768 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
769 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
770 };
771
772 static struct intc_vect vectors[] __initdata = {
773 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
774 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
775 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
776 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
777
778 INTC_VECT(DMAC1A_DEI0, 0x700),
779 INTC_VECT(DMAC1A_DEI1, 0x720),
780 INTC_VECT(DMAC1A_DEI2, 0x740),
781 INTC_VECT(DMAC1A_DEI3, 0x760),
782
783 INTC_VECT(_2DG_TRI, 0x780),
784 INTC_VECT(_2DG_INI, 0x7A0),
785 INTC_VECT(_2DG_CEI, 0x7C0),
786
787 INTC_VECT(DMAC0A_DEI0, 0x800),
788 INTC_VECT(DMAC0A_DEI1, 0x820),
789 INTC_VECT(DMAC0A_DEI2, 0x840),
790 INTC_VECT(DMAC0A_DEI3, 0x860),
791
792 INTC_VECT(VIO_CEU0, 0x880),
793 INTC_VECT(VIO_BEU0, 0x8A0),
794 INTC_VECT(VIO_VEU1, 0x8C0),
795 INTC_VECT(VIO_VOU, 0x8E0),
796
797 INTC_VECT(SCIFA3, 0x900),
798 INTC_VECT(VPU, 0x980),
799 INTC_VECT(TPU, 0x9A0),
800 INTC_VECT(CEU1, 0x9E0),
801 INTC_VECT(BEU1, 0xA00),
802 INTC_VECT(USB0, 0xA20),
803 INTC_VECT(USB1, 0xA40),
804 INTC_VECT(ATAPI, 0xA60),
805
806 INTC_VECT(RTC_ATI, 0xA80),
807 INTC_VECT(RTC_PRI, 0xAA0),
808 INTC_VECT(RTC_CUI, 0xAC0),
809
810 INTC_VECT(DMAC1B_DEI4, 0xB00),
811 INTC_VECT(DMAC1B_DEI5, 0xB20),
812 INTC_VECT(DMAC1B_DADERR, 0xB40),
813
814 INTC_VECT(DMAC0B_DEI4, 0xB80),
815 INTC_VECT(DMAC0B_DEI5, 0xBA0),
816 INTC_VECT(DMAC0B_DADERR, 0xBC0),
817
818 INTC_VECT(KEYSC, 0xBE0),
819 INTC_VECT(SCIF_SCIF0, 0xC00),
820 INTC_VECT(SCIF_SCIF1, 0xC20),
821 INTC_VECT(SCIF_SCIF2, 0xC40),
822 INTC_VECT(VEU0, 0xC60),
823 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
824 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
825 INTC_VECT(SPU_SPUI0, 0xCC0),
826 INTC_VECT(SPU_SPUI1, 0xCE0),
827 INTC_VECT(SCIFA4, 0xD00),
828
829 INTC_VECT(ICB, 0xD20),
830 INTC_VECT(ETHI, 0xD60),
831
832 INTC_VECT(I2C1_ALI, 0xD80),
833 INTC_VECT(I2C1_TACKI, 0xDA0),
834 INTC_VECT(I2C1_WAITI, 0xDC0),
835 INTC_VECT(I2C1_DTEI, 0xDE0),
836
837 INTC_VECT(I2C0_ALI, 0xE00),
838 INTC_VECT(I2C0_TACKI, 0xE20),
839 INTC_VECT(I2C0_WAITI, 0xE40),
840 INTC_VECT(I2C0_DTEI, 0xE60),
841
842 INTC_VECT(SDHI0_SDHII0, 0xE80),
843 INTC_VECT(SDHI0_SDHII1, 0xEA0),
844 INTC_VECT(SDHI0_SDHII2, 0xEC0),
845 INTC_VECT(SDHI0_SDHII3, 0xEE0),
846
847 INTC_VECT(CMT, 0xF00),
848 INTC_VECT(TSIF, 0xF20),
849 INTC_VECT(FSI, 0xF80),
850 INTC_VECT(SCIFA5, 0xFA0),
851
852 INTC_VECT(TMU0_TUNI0, 0x400),
853 INTC_VECT(TMU0_TUNI1, 0x420),
854 INTC_VECT(TMU0_TUNI2, 0x440),
855
856 INTC_VECT(IRDA, 0x480),
857
858 INTC_VECT(SDHI1_SDHII0, 0x4E0),
859 INTC_VECT(SDHI1_SDHII1, 0x500),
860 INTC_VECT(SDHI1_SDHII2, 0x520),
861
862 INTC_VECT(JPU, 0x560),
863 INTC_VECT(_2DDMAC, 0x4A0),
864
865 INTC_VECT(MMC_MMC2I, 0x5A0),
866 INTC_VECT(MMC_MMC3I, 0x5C0),
867
868 INTC_VECT(LCDC, 0xF40),
869
870 INTC_VECT(TMU1_TUNI0, 0x920),
871 INTC_VECT(TMU1_TUNI1, 0x940),
872 INTC_VECT(TMU1_TUNI2, 0x960),
873 };
874
875 static struct intc_group groups[] __initdata = {
876 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
877 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
878 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
879 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
880 INTC_GROUP(USB, USB0, USB1),
881 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
882 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
883 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
884 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
885 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
886 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
887 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
888 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
889 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
890 };
891
892 static struct intc_mask_reg mask_registers[] __initdata = {
893 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
894 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
895 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
896 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
897 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
898 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
899 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
900 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
901 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
902 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
903 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
904 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
905 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
906 JPU, 0, 0, LCDC } },
907 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
908 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
909 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
910 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
911 { 0, 0, ICB, SCIFA4,
912 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
913 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
914 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
915 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
916 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
917 { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
918 0, 0, SCIFA5, FSI } },
919 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
920 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
921 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
922 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
923 0, RTC_CUI, RTC_PRI, RTC_ATI } },
924 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
925 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
926 0, TPU, 0, TSIF } },
927 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
928 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
929 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
930 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
931 };
932
933 static struct intc_prio_reg prio_registers[] __initdata = {
934 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
935 TMU0_TUNI2, IRDA } },
936 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
937 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
938 TMU1_TUNI2, SPU } },
939 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
940 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
941 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
942 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
943 SCIF_SCIF2, VEU0 } },
944 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
945 I2C1, I2C0 } },
946 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
947 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
948 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
949 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
950 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
951 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
952 };
953
954 static struct intc_sense_reg sense_registers[] __initdata = {
955 { 0xa414001c, 16, 2, /* ICR1 */
956 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
957 };
958
959 static struct intc_mask_reg ack_registers[] __initdata = {
960 { 0xa4140024, 0, 8, /* INTREQ00 */
961 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
962 };
963
964 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
965 mask_registers, prio_registers, sense_registers,
966 ack_registers);
967
968 void __init plat_irq_setup(void)
969 {
970 register_intc_controller(&intc_desc);
971 }
972
973 static struct {
974 /* BSC */
975 unsigned long mmselr;
976 unsigned long cs0bcr;
977 unsigned long cs4bcr;
978 unsigned long cs5abcr;
979 unsigned long cs5bbcr;
980 unsigned long cs6abcr;
981 unsigned long cs6bbcr;
982 unsigned long cs4wcr;
983 unsigned long cs5awcr;
984 unsigned long cs5bwcr;
985 unsigned long cs6awcr;
986 unsigned long cs6bwcr;
987 /* INTC */
988 unsigned short ipra;
989 unsigned short iprb;
990 unsigned short iprc;
991 unsigned short iprd;
992 unsigned short ipre;
993 unsigned short iprf;
994 unsigned short iprg;
995 unsigned short iprh;
996 unsigned short ipri;
997 unsigned short iprj;
998 unsigned short iprk;
999 unsigned short iprl;
1000 unsigned char imr0;
1001 unsigned char imr1;
1002 unsigned char imr2;
1003 unsigned char imr3;
1004 unsigned char imr4;
1005 unsigned char imr5;
1006 unsigned char imr6;
1007 unsigned char imr7;
1008 unsigned char imr8;
1009 unsigned char imr9;
1010 unsigned char imr10;
1011 unsigned char imr11;
1012 unsigned char imr12;
1013 /* RWDT */
1014 unsigned short rwtcnt;
1015 unsigned short rwtcsr;
1016 /* CPG */
1017 unsigned long irdaclk;
1018 unsigned long spuclk;
1019 } sh7724_rstandby_state;
1020
1021 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1022 unsigned long flags, void *unused)
1023 {
1024 if (!(flags & SUSP_SH_RSTANDBY))
1025 return NOTIFY_DONE;
1026
1027 /* BCR */
1028 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1029 sh7724_rstandby_state.mmselr |= 0xa5a50000;
1030 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1031 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1032 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1033 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1034 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1035 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1036 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1037 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1038 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1039 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1040 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1041
1042 /* INTC */
1043 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1044 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1045 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1046 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1047 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1048 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1049 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1050 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1051 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1052 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1053 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1054 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1055 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1056 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1057 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1058 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1059 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1060 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1061 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1062 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1063 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1064 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1065 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1066 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1067 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1068
1069 /* RWDT */
1070 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1071 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1072 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1073 sh7724_rstandby_state.rwtcsr |= 0xa500;
1074 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1075
1076 /* CPG */
1077 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1078 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1079
1080 return NOTIFY_DONE;
1081 }
1082
1083 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1084 unsigned long flags, void *unused)
1085 {
1086 if (!(flags & SUSP_SH_RSTANDBY))
1087 return NOTIFY_DONE;
1088
1089 /* BCR */
1090 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1091 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1092 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1093 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1094 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1095 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1096 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1097 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1098 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1099 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1100 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1101 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1102
1103 /* INTC */
1104 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1105 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1106 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1107 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1108 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1109 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1110 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1111 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1112 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1113 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1114 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1115 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1116 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1117 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1118 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1119 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1120 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1121 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1122 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1123 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1124 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1125 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1126 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1127 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1128 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1129
1130 /* RWDT */
1131 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1132 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1133
1134 /* CPG */
1135 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1136 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1137
1138 return NOTIFY_DONE;
1139 }
1140
1141 static struct notifier_block sh7724_pre_sleep_notifier = {
1142 .notifier_call = sh7724_pre_sleep_notifier_call,
1143 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1144 };
1145
1146 static struct notifier_block sh7724_post_sleep_notifier = {
1147 .notifier_call = sh7724_post_sleep_notifier_call,
1148 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1149 };
1150
1151 static int __init sh7724_sleep_setup(void)
1152 {
1153 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1154 &sh7724_pre_sleep_notifier);
1155
1156 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1157 &sh7724_post_sleep_notifier);
1158 return 0;
1159 }
1160 arch_initcall(sh7724_sleep_setup);
1161
Linux with added FPC-III support