arch/sh/kernel/cpu/sh4a/setup-sh7786.c

   1 /*
   2  * SH7786 Setup
   3  *
   4  * Copyright (C) 2009  Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  * Paul Mundt <paul.mundt@renesas.com>
   7  *
   8  * Based on SH7785 Setup
   9  *
  10  *  Copyright (C) 2007  Paul Mundt
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file "COPYING" in the main directory of this archive
  14  * for more details.
  15  */
  16 #include <linux/platform_device.h>
  17 #include <linux/init.h>
  18 #include <linux/serial.h>
  19 #include <linux/serial_sci.h>
  20 #include <linux/io.h>
  21 #include <linux/mm.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/sh_timer.h>
  24 #include <asm/mmzone.h>
  25
  26 static struct plat_sci_port scif0_platform_data = {
  27         .mapbase        = 0xffea0000,
  28         .flags          = UPF_BOOT_AUTOCONF,
  29         .type           = PORT_SCIF,
  30         .irqs           = { 40, 41, 43, 42 },
  31 };
  32
  33 static struct platform_device scif0_device = {
  34         .name           = "sh-sci",
  35         .id             = 0,
  36         .dev            = {
  37                 .platform_data  = &scif0_platform_data,
  38         },
  39 };
  40
  41 /*
  42  * The rest of these all have multiplexed IRQs
  43  */
  44 static struct plat_sci_port scif1_platform_data = {
  45         .mapbase        = 0xffeb0000,
  46         .flags          = UPF_BOOT_AUTOCONF,
  47         .type           = PORT_SCIF,
  48         .irqs           = { 44, 44, 44, 44 },
  49 };
  50
  51 static struct platform_device scif1_device = {
  52         .name           = "sh-sci",
  53         .id             = 1,
  54         .dev            = {
  55                 .platform_data  = &scif1_platform_data,
  56         },
  57 };
  58
  59 static struct plat_sci_port scif2_platform_data = {
  60         .mapbase        = 0xffec0000,
  61         .flags          = UPF_BOOT_AUTOCONF,
  62         .type           = PORT_SCIF,
  63         .irqs           = { 50, 50, 50, 50 },
  64 };
  65
  66 static struct platform_device scif2_device = {
  67         .name           = "sh-sci",
  68         .id             = 2,
  69         .dev            = {
  70                 .platform_data  = &scif2_platform_data,
  71         },
  72 };
  73
  74 static struct plat_sci_port scif3_platform_data = {
  75         .mapbase        = 0xffed0000,
  76         .flags          = UPF_BOOT_AUTOCONF,
  77         .type           = PORT_SCIF,
  78         .irqs           = { 51, 51, 51, 51 },
  79 };
  80
  81 static struct platform_device scif3_device = {
  82         .name           = "sh-sci",
  83         .id             = 3,
  84         .dev            = {
  85                 .platform_data  = &scif3_platform_data,
  86         },
  87 };
  88
  89 static struct plat_sci_port scif4_platform_data = {
  90         .mapbase        = 0xffee0000,
  91         .flags          = UPF_BOOT_AUTOCONF,
  92         .type           = PORT_SCIF,
  93         .irqs           = { 52, 52, 52, 52 },
  94 };
  95
  96 static struct platform_device scif4_device = {
  97         .name           = "sh-sci",
  98         .id             = 4,
  99         .dev            = {
 100                 .platform_data  = &scif4_platform_data,
 101         },
 102 };
 103
 104 static struct plat_sci_port scif5_platform_data = {
 105         .mapbase        = 0xffef0000,
 106         .flags          = UPF_BOOT_AUTOCONF,
 107         .type           = PORT_SCIF,
 108         .irqs           = { 53, 53, 53, 53 },
 109 };
 110
 111 static struct platform_device scif5_device = {
 112         .name           = "sh-sci",
 113         .id             = 5,
 114         .dev            = {
 115                 .platform_data  = &scif5_platform_data,
 116         },
 117 };
 118
 119 static struct sh_timer_config tmu0_platform_data = {
 120         .name = "TMU0",
 121         .channel_offset = 0x04,
 122         .timer_bit = 0,
 123         .clk = "peripheral_clk",
 124         .clockevent_rating = 200,
 125 };
 126
 127 static struct resource tmu0_resources[] = {
 128         [0] = {
 129                 .name   = "TMU0",
 130                 .start  = 0xffd80008,
 131                 .end    = 0xffd80013,
 132                 .flags  = IORESOURCE_MEM,
 133         },
 134         [1] = {
 135                 .start  = 16,
 136                 .flags  = IORESOURCE_IRQ,
 137         },
 138 };
 139
 140 static struct platform_device tmu0_device = {
 141         .name           = "sh_tmu",
 142         .id             = 0,
 143         .dev = {
 144                 .platform_data  = &tmu0_platform_data,
 145         },
 146         .resource       = tmu0_resources,
 147         .num_resources  = ARRAY_SIZE(tmu0_resources),
 148 };
 149
 150 static struct sh_timer_config tmu1_platform_data = {
 151         .name = "TMU1",
 152         .channel_offset = 0x10,
 153         .timer_bit = 1,
 154         .clk = "peripheral_clk",
 155         .clocksource_rating = 200,
 156 };
 157
 158 static struct resource tmu1_resources[] = {
 159         [0] = {
 160                 .name   = "TMU1",
 161                 .start  = 0xffd80014,
 162                 .end    = 0xffd8001f,
 163                 .flags  = IORESOURCE_MEM,
 164         },
 165         [1] = {
 166                 .start  = 17,
 167                 .flags  = IORESOURCE_IRQ,
 168         },
 169 };
 170
 171 static struct platform_device tmu1_device = {
 172         .name           = "sh_tmu",
 173         .id             = 1,
 174         .dev = {
 175                 .platform_data  = &tmu1_platform_data,
 176         },
 177         .resource       = tmu1_resources,
 178         .num_resources  = ARRAY_SIZE(tmu1_resources),
 179 };
 180
 181 static struct sh_timer_config tmu2_platform_data = {
 182         .name = "TMU2",
 183         .channel_offset = 0x1c,
 184         .timer_bit = 2,
 185         .clk = "peripheral_clk",
 186 };
 187
 188 static struct resource tmu2_resources[] = {
 189         [0] = {
 190                 .name   = "TMU2",
 191                 .start  = 0xffd80020,
 192                 .end    = 0xffd8002f,
 193                 .flags  = IORESOURCE_MEM,
 194         },
 195         [1] = {
 196                 .start  = 18,
 197                 .flags  = IORESOURCE_IRQ,
 198         },
 199 };
 200
 201 static struct platform_device tmu2_device = {
 202         .name           = "sh_tmu",
 203         .id             = 2,
 204         .dev = {
 205                 .platform_data  = &tmu2_platform_data,
 206         },
 207         .resource       = tmu2_resources,
 208         .num_resources  = ARRAY_SIZE(tmu2_resources),
 209 };
 210
 211 static struct sh_timer_config tmu3_platform_data = {
 212         .name = "TMU3",
 213         .channel_offset = 0x04,
 214         .timer_bit = 0,
 215         .clk = "peripheral_clk",
 216 };
 217
 218 static struct resource tmu3_resources[] = {
 219         [0] = {
 220                 .name   = "TMU3",
 221                 .start  = 0xffda0008,
 222                 .end    = 0xffda0013,
 223                 .flags  = IORESOURCE_MEM,
 224         },
 225         [1] = {
 226                 .start  = 20,
 227                 .flags  = IORESOURCE_IRQ,
 228         },
 229 };
 230
 231 static struct platform_device tmu3_device = {
 232         .name           = "sh_tmu",
 233         .id             = 3,
 234         .dev = {
 235                 .platform_data  = &tmu3_platform_data,
 236         },
 237         .resource       = tmu3_resources,
 238         .num_resources  = ARRAY_SIZE(tmu3_resources),
 239 };
 240
 241 static struct sh_timer_config tmu4_platform_data = {
 242         .name = "TMU4",
 243         .channel_offset = 0x10,
 244         .timer_bit = 1,
 245         .clk = "peripheral_clk",
 246 };
 247
 248 static struct resource tmu4_resources[] = {
 249         [0] = {
 250                 .name   = "TMU4",
 251                 .start  = 0xffda0014,
 252                 .end    = 0xffda001f,
 253                 .flags  = IORESOURCE_MEM,
 254         },
 255         [1] = {
 256                 .start  = 21,
 257                 .flags  = IORESOURCE_IRQ,
 258         },
 259 };
 260
 261 static struct platform_device tmu4_device = {
 262         .name           = "sh_tmu",
 263         .id             = 4,
 264         .dev = {
 265                 .platform_data  = &tmu4_platform_data,
 266         },
 267         .resource       = tmu4_resources,
 268         .num_resources  = ARRAY_SIZE(tmu4_resources),
 269 };
 270
 271 static struct sh_timer_config tmu5_platform_data = {
 272         .name = "TMU5",
 273         .channel_offset = 0x1c,
 274         .timer_bit = 2,
 275         .clk = "peripheral_clk",
 276 };
 277
 278 static struct resource tmu5_resources[] = {
 279         [0] = {
 280                 .name   = "TMU5",
 281                 .start  = 0xffda0020,
 282                 .end    = 0xffda002b,
 283                 .flags  = IORESOURCE_MEM,
 284         },
 285         [1] = {
 286                 .start  = 22,
 287                 .flags  = IORESOURCE_IRQ,
 288         },
 289 };
 290
 291 static struct platform_device tmu5_device = {
 292         .name           = "sh_tmu",
 293         .id             = 5,
 294         .dev = {
 295                 .platform_data  = &tmu5_platform_data,
 296         },
 297         .resource       = tmu5_resources,
 298         .num_resources  = ARRAY_SIZE(tmu5_resources),
 299 };
 300
 301 static struct sh_timer_config tmu6_platform_data = {
 302         .name = "TMU6",
 303         .channel_offset = 0x04,
 304         .timer_bit = 0,
 305         .clk = "peripheral_clk",
 306 };
 307
 308 static struct resource tmu6_resources[] = {
 309         [0] = {
 310                 .name   = "TMU6",
 311                 .start  = 0xffdc0008,
 312                 .end    = 0xffdc0013,
 313                 .flags  = IORESOURCE_MEM,
 314         },
 315         [1] = {
 316                 .start  = 45,
 317                 .flags  = IORESOURCE_IRQ,
 318         },
 319 };
 320
 321 static struct platform_device tmu6_device = {
 322         .name           = "sh_tmu",
 323         .id             = 6,
 324         .dev = {
 325                 .platform_data  = &tmu6_platform_data,
 326         },
 327         .resource       = tmu6_resources,
 328         .num_resources  = ARRAY_SIZE(tmu6_resources),
 329 };
 330
 331 static struct sh_timer_config tmu7_platform_data = {
 332         .name = "TMU7",
 333         .channel_offset = 0x10,
 334         .timer_bit = 1,
 335         .clk = "peripheral_clk",
 336 };
 337
 338 static struct resource tmu7_resources[] = {
 339         [0] = {
 340                 .name   = "TMU7",
 341                 .start  = 0xffdc0014,
 342                 .end    = 0xffdc001f,
 343                 .flags  = IORESOURCE_MEM,
 344         },
 345         [1] = {
 346                 .start  = 45,
 347                 .flags  = IORESOURCE_IRQ,
 348         },
 349 };
 350
 351 static struct platform_device tmu7_device = {
 352         .name           = "sh_tmu",
 353         .id             = 7,
 354         .dev = {
 355                 .platform_data  = &tmu7_platform_data,
 356         },
 357         .resource       = tmu7_resources,
 358         .num_resources  = ARRAY_SIZE(tmu7_resources),
 359 };
 360
 361 static struct sh_timer_config tmu8_platform_data = {
 362         .name = "TMU8",
 363         .channel_offset = 0x1c,
 364         .timer_bit = 2,
 365         .clk = "peripheral_clk",
 366 };
 367
 368 static struct resource tmu8_resources[] = {
 369         [0] = {
 370                 .name   = "TMU8",
 371                 .start  = 0xffdc0020,
 372                 .end    = 0xffdc002b,
 373                 .flags  = IORESOURCE_MEM,
 374         },
 375         [1] = {
 376                 .start  = 45,
 377                 .flags  = IORESOURCE_IRQ,
 378         },
 379 };
 380
 381 static struct platform_device tmu8_device = {
 382         .name           = "sh_tmu",
 383         .id             = 8,
 384         .dev = {
 385                 .platform_data  = &tmu8_platform_data,
 386         },
 387         .resource       = tmu8_resources,
 388         .num_resources  = ARRAY_SIZE(tmu8_resources),
 389 };
 390
 391 static struct sh_timer_config tmu9_platform_data = {
 392         .name = "TMU9",
 393         .channel_offset = 0x04,
 394         .timer_bit = 0,
 395         .clk = "peripheral_clk",
 396 };
 397
 398 static struct resource tmu9_resources[] = {
 399         [0] = {
 400                 .name   = "TMU9",
 401                 .start  = 0xffde0008,
 402                 .end    = 0xffde0013,
 403                 .flags  = IORESOURCE_MEM,
 404         },
 405         [1] = {
 406                 .start  = 46,
 407                 .flags  = IORESOURCE_IRQ,
 408         },
 409 };
 410
 411 static struct platform_device tmu9_device = {
 412         .name           = "sh_tmu",
 413         .id             = 9,
 414         .dev = {
 415                 .platform_data  = &tmu9_platform_data,
 416         },
 417         .resource       = tmu9_resources,
 418         .num_resources  = ARRAY_SIZE(tmu9_resources),
 419 };
 420
 421 static struct sh_timer_config tmu10_platform_data = {
 422         .name = "TMU10",
 423         .channel_offset = 0x10,
 424         .timer_bit = 1,
 425         .clk = "peripheral_clk",
 426 };
 427
 428 static struct resource tmu10_resources[] = {
 429         [0] = {
 430                 .name   = "TMU10",
 431                 .start  = 0xffde0014,
 432                 .end    = 0xffde001f,
 433                 .flags  = IORESOURCE_MEM,
 434         },
 435         [1] = {
 436                 .start  = 46,
 437                 .flags  = IORESOURCE_IRQ,
 438         },
 439 };
 440
 441 static struct platform_device tmu10_device = {
 442         .name           = "sh_tmu",
 443         .id             = 10,
 444         .dev = {
 445                 .platform_data  = &tmu10_platform_data,
 446         },
 447         .resource       = tmu10_resources,
 448         .num_resources  = ARRAY_SIZE(tmu10_resources),
 449 };
 450
 451 static struct sh_timer_config tmu11_platform_data = {
 452         .name = "TMU11",
 453         .channel_offset = 0x1c,
 454         .timer_bit = 2,
 455         .clk = "peripheral_clk",
 456 };
 457
 458 static struct resource tmu11_resources[] = {
 459         [0] = {
 460                 .name   = "TMU11",
 461                 .start  = 0xffde0020,
 462                 .end    = 0xffde002b,
 463                 .flags  = IORESOURCE_MEM,
 464         },
 465         [1] = {
 466                 .start  = 46,
 467                 .flags  = IORESOURCE_IRQ,
 468         },
 469 };
 470
 471 static struct platform_device tmu11_device = {
 472         .name           = "sh_tmu",
 473         .id             = 11,
 474         .dev = {
 475                 .platform_data  = &tmu11_platform_data,
 476         },
 477         .resource       = tmu11_resources,
 478         .num_resources  = ARRAY_SIZE(tmu11_resources),
 479 };
 480
 481 static struct resource usb_ohci_resources[] = {
 482         [0] = {
 483                 .start  = 0xffe70400,
 484                 .end    = 0xffe704ff,
 485                 .flags  = IORESOURCE_MEM,
 486         },
 487         [1] = {
 488                 .start  = 77,
 489                 .end    = 77,
 490                 .flags  = IORESOURCE_IRQ,
 491         },
 492 };
 493
 494 static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
 495 static struct platform_device usb_ohci_device = {
 496         .name           = "sh_ohci",
 497         .id             = -1,
 498         .dev = {
 499                 .dma_mask               = &usb_ohci_dma_mask,
 500                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 501         },
 502         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 503         .resource       = usb_ohci_resources,
 504 };
 505
 506 static struct platform_device *sh7786_early_devices[] __initdata = {
 507         &scif0_device,
 508         &scif1_device,
 509         &scif2_device,
 510         &scif3_device,
 511         &scif4_device,
 512         &scif5_device,
 513         &tmu0_device,
 514         &tmu1_device,
 515         &tmu2_device,
 516         &tmu3_device,
 517         &tmu4_device,
 518         &tmu5_device,
 519         &tmu6_device,
 520         &tmu7_device,
 521         &tmu8_device,
 522         &tmu9_device,
 523         &tmu10_device,
 524         &tmu11_device,
 525 };
 526
 527 static struct platform_device *sh7786_devices[] __initdata = {
 528         &usb_ohci_device,
 529 };
 530
 531
 532 /*
 533  * Please call this function if your platform board
 534  * use external clock for USB
 535  * */
 536 #define USBCTL0         0xffe70858
 537 #define CLOCK_MODE_MASK 0xffffff7f
 538 #define EXT_CLOCK_MODE  0x00000080
 539 void __init sh7786_usb_use_exclock(void)
 540 {
 541         u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
 542         __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
 543 }
 544
 545 #define USBINITREG1     0xffe70094
 546 #define USBINITREG2     0xffe7009c
 547 #define USBINITVAL1     0x00ff0040
 548 #define USBINITVAL2     0x00000001
 549
 550 #define USBPCTL1        0xffe70804
 551 #define USBST           0xffe70808
 552 #define PHY_ENB         0x00000001
 553 #define PLL_ENB         0x00000002
 554 #define PHY_RST         0x00000004
 555 #define ACT_PLL_STATUS  0xc0000000
 556 static void __init sh7786_usb_setup(void)
 557 {
 558         int i = 1000000;
 559
 560         /*
 561          * USB initial settings
 562          *
 563          * The following settings are necessary
 564          * for using the USB modules.
 565          *
 566          * see "USB Inital Settings" for detail
 567          */
 568         __raw_writel(USBINITVAL1, USBINITREG1);
 569         __raw_writel(USBINITVAL2, USBINITREG2);
 570
 571         /*
 572          * Set the PHY and PLL enable bit
 573          */
 574         __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
 575         while (i--) {
 576                 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
 577                         /* Set the PHY RST bit */
 578                         __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
 579                         printk(KERN_INFO "sh7786 usb setup done\n");
 580                         break;
 581                 }
 582                 cpu_relax();
 583         }
 584 }
 585
 586 static int __init sh7786_devices_setup(void)
 587 {
 588         int ret;
 589
 590         sh7786_usb_setup();
 591
 592         ret = platform_add_devices(sh7786_early_devices,
 593                                    ARRAY_SIZE(sh7786_early_devices));
 594         if (unlikely(ret != 0))
 595                 return ret;
 596
 597         return platform_add_devices(sh7786_devices,
 598                                     ARRAY_SIZE(sh7786_devices));
 599 }
 600 arch_initcall(sh7786_devices_setup);
 601
 602 void __init plat_early_device_setup(void)
 603 {
 604         early_platform_add_devices(sh7786_early_devices,
 605                                    ARRAY_SIZE(sh7786_early_devices));
 606 }
 607
 608 enum {
 609         UNUSED = 0,
 610
 611         /* interrupt sources */
 612
 613         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 614         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 615         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 616         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 617
 618         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 619         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 620         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 621         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 622
 623         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 624         WDT,
 625         TMU0_0, TMU0_1, TMU0_2, TMU0_3,
 626         TMU1_0, TMU1_1, TMU1_2,
 627         DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 628         HUDI1, HUDI0,
 629         DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 630         HPB_0, HPB_1, HPB_2,
 631         SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 632         SCIF1,
 633         TMU2, TMU3,
 634         SCIF2, SCIF3, SCIF4, SCIF5,
 635         Eth_0, Eth_1,
 636         PCIeC0_0, PCIeC0_1, PCIeC0_2,
 637         PCIeC1_0, PCIeC1_1, PCIeC1_2,
 638         USB,
 639         I2C0, I2C1,
 640         DU,
 641         SSI0, SSI1, SSI2, SSI3,
 642         PCIeC2_0, PCIeC2_1, PCIeC2_2,
 643         HAC0, HAC1,
 644         FLCTL,
 645         HSPI,
 646         GPIO0, GPIO1,
 647         Thermal,
 648         INTICI0, INTICI1, INTICI2, INTICI3,
 649         INTICI4, INTICI5, INTICI6, INTICI7,
 650 };
 651
 652 static struct intc_vect vectors[] __initdata = {
 653         INTC_VECT(WDT, 0x3e0),
 654         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
 655         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
 656         INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
 657         INTC_VECT(TMU1_2, 0x4c0),
 658         INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
 659         INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
 660         INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
 661         INTC_VECT(DMAC0_6, 0x5c0),
 662         INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
 663         INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
 664         INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
 665         INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
 666         INTC_VECT(HPB_2, 0x6e0),
 667         INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
 668         INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
 669         INTC_VECT(SCIF1, 0x780),
 670         INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
 671         INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
 672         INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
 673         INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
 674         INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
 675         INTC_VECT(PCIeC0_2, 0xb20),
 676         INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
 677         INTC_VECT(PCIeC1_2, 0xb80),
 678         INTC_VECT(USB, 0xba0),
 679         INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
 680         INTC_VECT(DU, 0xd00),
 681         INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
 682         INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
 683         INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
 684         INTC_VECT(PCIeC2_2, 0xde0),
 685         INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
 686         INTC_VECT(FLCTL, 0xe40),
 687         INTC_VECT(HSPI, 0xe80),
 688         INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
 689         INTC_VECT(Thermal, 0xee0),
 690         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
 691         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
 692         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
 693         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
 694 };
 695
 696 #define CnINTMSK0       0xfe410030
 697 #define CnINTMSK1       0xfe410040
 698 #define CnINTMSKCLR0    0xfe410050
 699 #define CnINTMSKCLR1    0xfe410060
 700 #define CnINT2MSKR0     0xfe410a20
 701 #define CnINT2MSKR1     0xfe410a24
 702 #define CnINT2MSKR2     0xfe410a28
 703 #define CnINT2MSKR3     0xfe410a2c
 704 #define CnINT2MSKCR0    0xfe410a30
 705 #define CnINT2MSKCR1    0xfe410a34
 706 #define CnINT2MSKCR2    0xfe410a38
 707 #define CnINT2MSKCR3    0xfe410a3c
 708 #define INTMSK2         0xfe410068
 709 #define INTMSKCLR2      0xfe41006c
 710
 711 static struct intc_mask_reg mask_registers[] __initdata = {
 712         { CnINTMSK0, CnINTMSKCLR0, 32,
 713           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 714         { INTMSK2, INTMSKCLR2, 32,
 715           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 716             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 717             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 718             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 719             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 720             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 721             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 722             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 723         { CnINT2MSKR0, CnINT2MSKCR0 , 32,
 724           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 725             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
 726         { CnINT2MSKR1, CnINT2MSKCR1, 32,
 727           { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
 728             DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 729             HUDI1, HUDI0,
 730             DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 731             HPB_0, HPB_1, HPB_2,
 732             SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 733             SCIF1,
 734             TMU2, TMU3, 0, } },
 735         { CnINT2MSKR2, CnINT2MSKCR2, 32,
 736           { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
 737             Eth_0, Eth_1,
 738             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 739             PCIeC0_0, PCIeC0_1, PCIeC0_2,
 740             PCIeC1_0, PCIeC1_1, PCIeC1_2,
 741             USB, 0, 0 } },
 742         { CnINT2MSKR3, CnINT2MSKCR3, 32,
 743           { 0, 0, 0, 0, 0, 0,
 744             I2C0, I2C1,
 745             DU, SSI0, SSI1, SSI2, SSI3,
 746             PCIeC2_0, PCIeC2_1, PCIeC2_2,
 747             HAC0, HAC1,
 748             FLCTL, 0,
 749             HSPI, GPIO0, GPIO1, Thermal,
 750             0, 0, 0, 0, 0, 0, 0, 0 } },
 751 };
 752
 753 static struct intc_prio_reg prio_registers[] __initdata = {
 754         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 755                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 756         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
 757         { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
 758                                                  TMU0_2, TMU0_3 } },
 759         { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
 760                                                  TMU1_2, 0 } },
 761         { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
 762                                                  DMAC0_2, DMAC0_3 } },
 763         { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
 764                                                  DMAC0_6, HUDI1 } },
 765         { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
 766                                                  DMAC1_1, DMAC1_2 } },
 767         { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
 768                                                  HPB_1, HPB_2 } },
 769         { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
 770                                                  SCIF0_2, SCIF0_3 } },
 771         { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
 772         { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
 773         { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
 774                                                   Eth_0, Eth_1 } },
 775         { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
 776         { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
 777         { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
 778         { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
 779         { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
 780                                                   PCIeC1_0, PCIeC1_1 } },
 781         { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
 782         { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
 783         { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
 784         { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
 785         { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
 786                                                   PCIeC2_1, PCIeC2_2 } },
 787         { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
 788         { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
 789                                                   GPIO1, Thermal } },
 790         { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
 791         { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
 792         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
 793           { INTICI7, INTICI6, INTICI5, INTICI4,
 794             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
 795 };
 796
 797 static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
 798                          mask_registers, prio_registers, NULL);
 799
 800 /* Support for external interrupt pins in IRQ mode */
 801
 802 static struct intc_vect vectors_irq0123[] __initdata = {
 803         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
 804         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
 805 };
 806
 807 static struct intc_vect vectors_irq4567[] __initdata = {
 808         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
 809         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
 810 };
 811
 812 static struct intc_sense_reg sense_registers[] __initdata = {
 813         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 814                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 815 };
 816
 817 static struct intc_mask_reg ack_registers[] __initdata = {
 818         { 0xfe410024, 0, 32, /* INTREQ */
 819           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 820 };
 821
 822 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
 823                              vectors_irq0123, NULL, mask_registers,
 824                              prio_registers, sense_registers, ack_registers);
 825
 826 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
 827                              vectors_irq4567, NULL, mask_registers,
 828                              prio_registers, sense_registers, ack_registers);
 829
 830 /* External interrupt pins in IRL mode */
 831
 832 static struct intc_vect vectors_irl0123[] __initdata = {
 833         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 834         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 835         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 836         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 837         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 838         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 839         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 840         INTC_VECT(IRL0_HHHL, 0x3c0),
 841 };
 842
 843 static struct intc_vect vectors_irl4567[] __initdata = {
 844         INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
 845         INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
 846         INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
 847         INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
 848         INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
 849         INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
 850         INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
 851         INTC_VECT(IRL4_HHHL, 0xac0),
 852 };
 853
 854 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
 855                          NULL, mask_registers, NULL, NULL);
 856
 857 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 858                          NULL, mask_registers, NULL, NULL);
 859
 860 #define INTC_ICR0       0xfe410000
 861 #define INTC_INTMSK0    CnINTMSK0
 862 #define INTC_INTMSK1    CnINTMSK1
 863 #define INTC_INTMSK2    INTMSK2
 864 #define INTC_INTMSKCLR1 CnINTMSKCLR1
 865 #define INTC_INTMSKCLR2 INTMSKCLR2
 866
 867 void __init plat_irq_setup(void)
 868 {
 869         /* disable IRQ3-0 + IRQ7-4 */
 870         ctrl_outl(0xff000000, INTC_INTMSK0);
 871
 872         /* disable IRL3-0 + IRL7-4 */
 873         ctrl_outl(0xc0000000, INTC_INTMSK1);
 874         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 875
 876         /* select IRL mode for IRL3-0 + IRL7-4 */
 877         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 878
 879         register_intc_controller(&intc_desc);
 880 }
 881
 882 void __init plat_irq_setup_pins(int mode)
 883 {
 884         switch (mode) {
 885         case IRQ_MODE_IRQ7654:
 886                 /* select IRQ mode for IRL7-4 */
 887                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 888                 register_intc_controller(&intc_desc_irq4567);
 889                 break;
 890         case IRQ_MODE_IRQ3210:
 891                 /* select IRQ mode for IRL3-0 */
 892                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 893                 register_intc_controller(&intc_desc_irq0123);
 894                 break;
 895         case IRQ_MODE_IRL7654:
 896                 /* enable IRL7-4 but don't provide any masking */
 897                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 898                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 899                 break;
 900         case IRQ_MODE_IRL3210:
 901                 /* enable IRL0-3 but don't provide any masking */
 902                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 903                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 904                 break;
 905         case IRQ_MODE_IRL7654_MASK:
 906                 /* enable IRL7-4 and mask using cpu intc controller */
 907                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 908                 register_intc_controller(&intc_desc_irl4567);
 909                 break;
 910         case IRQ_MODE_IRL3210_MASK:
 911                 /* enable IRL0-3 and mask using cpu intc controller */
 912                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 913                 register_intc_controller(&intc_desc_irl0123);
 914                 break;
 915         default:
 916                 BUG();
 917         }
 918 }
 919
 920 void __init plat_mem_setup(void)
 921 {
 922 }