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ALSA: hda - Add pcm_mmap_prepare op.
[linux/fpc-iii.git] / sound / pci / hda / hda_intel.c
blobaa8b765c92995c455fd1f67b43ea0e8c98c66b0a
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65 #include "hda_i915.h"
66 #include "hda_priv.h"
67
68
69 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
70 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
71 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
72 static char *model[SNDRV_CARDS];
73 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
75 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
76 static int probe_only[SNDRV_CARDS];
77 static int jackpoll_ms[SNDRV_CARDS];
78 static bool single_cmd;
79 static int enable_msi = -1;
80 #ifdef CONFIG_SND_HDA_PATCH_LOADER
81 static char *patch[SNDRV_CARDS];
82 #endif
83 #ifdef CONFIG_SND_HDA_INPUT_BEEP
84 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
85 CONFIG_SND_HDA_INPUT_BEEP_MODE};
86 #endif
87
88 module_param_array(index, int, NULL, 0444);
89 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
90 module_param_array(id, charp, NULL, 0444);
91 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
92 module_param_array(enable, bool, NULL, 0444);
93 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
94 module_param_array(model, charp, NULL, 0444);
95 MODULE_PARM_DESC(model, "Use the given board model.");
96 module_param_array(position_fix, int, NULL, 0444);
97 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
98 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
99 module_param_array(bdl_pos_adj, int, NULL, 0644);
100 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
101 module_param_array(probe_mask, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
103 module_param_array(probe_only, int, NULL, 0444);
104 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
105 module_param_array(jackpoll_ms, int, NULL, 0444);
106 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
107 module_param(single_cmd, bool, 0444);
108 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
109 "(for debugging only).");
110 module_param(enable_msi, bint, 0444);
111 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
112 #ifdef CONFIG_SND_HDA_PATCH_LOADER
113 module_param_array(patch, charp, NULL, 0444);
114 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
115 #endif
116 #ifdef CONFIG_SND_HDA_INPUT_BEEP
117 module_param_array(beep_mode, bool, NULL, 0444);
118 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
119 "(0=off, 1=on) (default=1).");
120 #endif
121
122 #ifdef CONFIG_PM
123 static int param_set_xint(const char *val, const struct kernel_param *kp);
124 static struct kernel_param_ops param_ops_xint = {
125 .set = param_set_xint,
126 .get = param_get_int,
127 };
128 #define param_check_xint param_check_int
129
130 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
131 static int *power_save_addr = &power_save;
132 module_param(power_save, xint, 0644);
133 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
134 "(in second, 0 = disable).");
135
136 /* reset the HD-audio controller in power save mode.
137 * this may give more power-saving, but will take longer time to
138 * wake up.
139 */
140 static bool power_save_controller = 1;
141 module_param(power_save_controller, bool, 0644);
142 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
143 #else
144 static int *power_save_addr;
145 #endif /* CONFIG_PM */
146
147 static int align_buffer_size = -1;
148 module_param(align_buffer_size, bint, 0644);
149 MODULE_PARM_DESC(align_buffer_size,
150 "Force buffer and period sizes to be multiple of 128 bytes.");
151
152 #ifdef CONFIG_X86
153 static bool hda_snoop = true;
154 module_param_named(snoop, hda_snoop, bool, 0444);
155 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
156 #else
157 #define hda_snoop true
158 #endif
159
160
161 MODULE_LICENSE("GPL");
162 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
163 "{Intel, ICH6M},"
164 "{Intel, ICH7},"
165 "{Intel, ESB2},"
166 "{Intel, ICH8},"
167 "{Intel, ICH9},"
168 "{Intel, ICH10},"
169 "{Intel, PCH},"
170 "{Intel, CPT},"
171 "{Intel, PPT},"
172 "{Intel, LPT},"
173 "{Intel, LPT_LP},"
174 "{Intel, WPT_LP},"
175 "{Intel, HPT},"
176 "{Intel, PBG},"
177 "{Intel, SCH},"
178 "{ATI, SB450},"
179 "{ATI, SB600},"
180 "{ATI, RS600},"
181 "{ATI, RS690},"
182 "{ATI, RS780},"
183 "{ATI, R600},"
184 "{ATI, RV630},"
185 "{ATI, RV610},"
186 "{ATI, RV670},"
187 "{ATI, RV635},"
188 "{ATI, RV620},"
189 "{ATI, RV770},"
190 "{VIA, VT8251},"
191 "{VIA, VT8237A},"
192 "{SiS, SIS966},"
193 "{ULI, M5461}}");
194 MODULE_DESCRIPTION("Intel HDA driver");
195
196 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
197 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
198 #define SUPPORT_VGA_SWITCHEROO
199 #endif
200 #endif
201
202
203 /*
204 */
205
206 /* DSP lock helpers */
207 #ifdef CONFIG_SND_HDA_DSP_LOADER
208 #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
209 #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
210 #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
211 #define dsp_is_locked(dev) ((dev)->locked)
212 #else
213 #define dsp_lock_init(dev) do {} while (0)
214 #define dsp_lock(dev) do {} while (0)
215 #define dsp_unlock(dev) do {} while (0)
216 #define dsp_is_locked(dev) 0
217 #endif
218
219 #define CREATE_TRACE_POINTS
220 #include "hda_intel_trace.h"
221
222 /* driver types */
223 enum {
224 AZX_DRIVER_ICH,
225 AZX_DRIVER_PCH,
226 AZX_DRIVER_SCH,
227 AZX_DRIVER_HDMI,
228 AZX_DRIVER_ATI,
229 AZX_DRIVER_ATIHDMI,
230 AZX_DRIVER_ATIHDMI_NS,
231 AZX_DRIVER_VIA,
232 AZX_DRIVER_SIS,
233 AZX_DRIVER_ULI,
234 AZX_DRIVER_NVIDIA,
235 AZX_DRIVER_TERA,
236 AZX_DRIVER_CTX,
237 AZX_DRIVER_CTHDA,
238 AZX_DRIVER_GENERIC,
239 AZX_NUM_DRIVERS, /* keep this as last entry */
240 };
241
242 /* quirks for Intel PCH */
243 #define AZX_DCAPS_INTEL_PCH_NOPM \
244 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
245 AZX_DCAPS_COUNT_LPIB_DELAY)
246
247 #define AZX_DCAPS_INTEL_PCH \
248 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
249
250 #define AZX_DCAPS_INTEL_HASWELL \
251 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
252 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
253 AZX_DCAPS_I915_POWERWELL)
254
255 /* quirks for ATI SB / AMD Hudson */
256 #define AZX_DCAPS_PRESET_ATI_SB \
257 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
258 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
259
260 /* quirks for ATI/AMD HDMI */
261 #define AZX_DCAPS_PRESET_ATI_HDMI \
262 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
263
264 /* quirks for Nvidia */
265 #define AZX_DCAPS_PRESET_NVIDIA \
266 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
267 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
268
269 #define AZX_DCAPS_PRESET_CTHDA \
270 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
271
272 /*
273 * VGA-switcher support
274 */
275 #ifdef SUPPORT_VGA_SWITCHEROO
276 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
277 #else
278 #define use_vga_switcheroo(chip) 0
279 #endif
280
281 static char *driver_short_names[] = {
282 [AZX_DRIVER_ICH] = "HDA Intel",
283 [AZX_DRIVER_PCH] = "HDA Intel PCH",
284 [AZX_DRIVER_SCH] = "HDA Intel MID",
285 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
286 [AZX_DRIVER_ATI] = "HDA ATI SB",
287 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
288 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
289 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
290 [AZX_DRIVER_SIS] = "HDA SIS966",
291 [AZX_DRIVER_ULI] = "HDA ULI M5461",
292 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
293 [AZX_DRIVER_TERA] = "HDA Teradici",
294 [AZX_DRIVER_CTX] = "HDA Creative",
295 [AZX_DRIVER_CTHDA] = "HDA Creative",
296 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
297 };
298
299 /* for pcm support */
300 static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
301 {
302 return substream->runtime->private_data;
303 }
304
305 #ifdef CONFIG_X86
306 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
307 {
308 int pages;
309
310 if (azx_snoop(chip))
311 return;
312 if (!dmab || !dmab->area || !dmab->bytes)
313 return;
314
315 #ifdef CONFIG_SND_DMA_SGBUF
316 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
317 struct snd_sg_buf *sgbuf = dmab->private_data;
318 if (on)
319 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
320 else
321 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
322 return;
323 }
324 #endif
325
326 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
327 if (on)
328 set_memory_wc((unsigned long)dmab->area, pages);
329 else
330 set_memory_wb((unsigned long)dmab->area, pages);
331 }
332
333 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
334 bool on)
335 {
336 __mark_pages_wc(chip, buf, on);
337 }
338 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
339 struct snd_pcm_substream *substream, bool on)
340 {
341 if (azx_dev->wc_marked != on) {
342 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
343 azx_dev->wc_marked = on;
344 }
345 }
346 #else
347 /* NOP for other archs */
348 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
349 bool on)
350 {
351 }
352 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
353 struct snd_pcm_substream *substream, bool on)
354 {
355 }
356 #endif
357
358 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
359 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
360 /*
361 * Interface for HD codec
362 */
363
364 /*
365 * CORB / RIRB interface
366 */
367 static int azx_alloc_cmd_io(struct azx *chip)
368 {
369 int err;
370
371 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
372 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
373 PAGE_SIZE, &chip->rb);
374 if (err < 0)
375 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
376 return err;
377 }
378
379 static void azx_init_cmd_io(struct azx *chip)
380 {
381 int timeout;
382
383 spin_lock_irq(&chip->reg_lock);
384 /* CORB set up */
385 chip->corb.addr = chip->rb.addr;
386 chip->corb.buf = (u32 *)chip->rb.area;
387 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
388 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
389
390 /* set the corb size to 256 entries (ULI requires explicitly) */
391 azx_writeb(chip, CORBSIZE, 0x02);
392 /* set the corb write pointer to 0 */
393 azx_writew(chip, CORBWP, 0);
394
395 /* reset the corb hw read pointer */
396 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
397 for (timeout = 1000; timeout > 0; timeout--) {
398 if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST)
399 break;
400 udelay(1);
401 }
402 if (timeout <= 0)
403 dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
404 azx_readw(chip, CORBRP));
405
406 azx_writew(chip, CORBRP, 0);
407 for (timeout = 1000; timeout > 0; timeout--) {
408 if (azx_readw(chip, CORBRP) == 0)
409 break;
410 udelay(1);
411 }
412 if (timeout <= 0)
413 dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
414 azx_readw(chip, CORBRP));
415
416 /* enable corb dma */
417 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
418
419 /* RIRB set up */
420 chip->rirb.addr = chip->rb.addr + 2048;
421 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
422 chip->rirb.wp = chip->rirb.rp = 0;
423 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
424 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
425 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
426
427 /* set the rirb size to 256 entries (ULI requires explicitly) */
428 azx_writeb(chip, RIRBSIZE, 0x02);
429 /* reset the rirb hw write pointer */
430 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
431 /* set N=1, get RIRB response interrupt for new entry */
432 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
433 azx_writew(chip, RINTCNT, 0xc0);
434 else
435 azx_writew(chip, RINTCNT, 1);
436 /* enable rirb dma and response irq */
437 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
438 spin_unlock_irq(&chip->reg_lock);
439 }
440
441 static void azx_free_cmd_io(struct azx *chip)
442 {
443 spin_lock_irq(&chip->reg_lock);
444 /* disable ringbuffer DMAs */
445 azx_writeb(chip, RIRBCTL, 0);
446 azx_writeb(chip, CORBCTL, 0);
447 spin_unlock_irq(&chip->reg_lock);
448 }
449
450 static unsigned int azx_command_addr(u32 cmd)
451 {
452 unsigned int addr = cmd >> 28;
453
454 if (addr >= AZX_MAX_CODECS) {
455 snd_BUG();
456 addr = 0;
457 }
458
459 return addr;
460 }
461
462 /* send a command */
463 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
464 {
465 struct azx *chip = bus->private_data;
466 unsigned int addr = azx_command_addr(val);
467 unsigned int wp, rp;
468
469 spin_lock_irq(&chip->reg_lock);
470
471 /* add command to corb */
472 wp = azx_readw(chip, CORBWP);
473 if (wp == 0xffff) {
474 /* something wrong, controller likely turned to D3 */
475 spin_unlock_irq(&chip->reg_lock);
476 return -EIO;
477 }
478 wp++;
479 wp %= ICH6_MAX_CORB_ENTRIES;
480
481 rp = azx_readw(chip, CORBRP);
482 if (wp == rp) {
483 /* oops, it's full */
484 spin_unlock_irq(&chip->reg_lock);
485 return -EAGAIN;
486 }
487
488 chip->rirb.cmds[addr]++;
489 chip->corb.buf[wp] = cpu_to_le32(val);
490 azx_writew(chip, CORBWP, wp);
491
492 spin_unlock_irq(&chip->reg_lock);
493
494 return 0;
495 }
496
497 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
498
499 /* retrieve RIRB entry - called from interrupt handler */
500 static void azx_update_rirb(struct azx *chip)
501 {
502 unsigned int rp, wp;
503 unsigned int addr;
504 u32 res, res_ex;
505
506 wp = azx_readw(chip, RIRBWP);
507 if (wp == 0xffff) {
508 /* something wrong, controller likely turned to D3 */
509 return;
510 }
511
512 if (wp == chip->rirb.wp)
513 return;
514 chip->rirb.wp = wp;
515
516 while (chip->rirb.rp != wp) {
517 chip->rirb.rp++;
518 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
519
520 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
521 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
522 res = le32_to_cpu(chip->rirb.buf[rp]);
523 addr = res_ex & 0xf;
524 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
525 dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
526 res, res_ex,
527 chip->rirb.rp, wp);
528 snd_BUG();
529 }
530 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
531 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
532 else if (chip->rirb.cmds[addr]) {
533 chip->rirb.res[addr] = res;
534 smp_wmb();
535 chip->rirb.cmds[addr]--;
536 } else if (printk_ratelimit()) {
537 dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
538 res, res_ex,
539 chip->last_cmd[addr]);
540 }
541 }
542 }
543
544 /* receive a response */
545 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
546 unsigned int addr)
547 {
548 struct azx *chip = bus->private_data;
549 unsigned long timeout;
550 unsigned long loopcounter;
551 int do_poll = 0;
552
553 again:
554 timeout = jiffies + msecs_to_jiffies(1000);
555
556 for (loopcounter = 0;; loopcounter++) {
557 if (chip->polling_mode || do_poll) {
558 spin_lock_irq(&chip->reg_lock);
559 azx_update_rirb(chip);
560 spin_unlock_irq(&chip->reg_lock);
561 }
562 if (!chip->rirb.cmds[addr]) {
563 smp_rmb();
564 bus->rirb_error = 0;
565
566 if (!do_poll)
567 chip->poll_count = 0;
568 return chip->rirb.res[addr]; /* the last value */
569 }
570 if (time_after(jiffies, timeout))
571 break;
572 if (bus->needs_damn_long_delay || loopcounter > 3000)
573 msleep(2); /* temporary workaround */
574 else {
575 udelay(10);
576 cond_resched();
577 }
578 }
579
580 if (!bus->no_response_fallback)
581 return -1;
582
583 if (!chip->polling_mode && chip->poll_count < 2) {
584 dev_dbg(chip->card->dev,
585 "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
586 chip->last_cmd[addr]);
587 do_poll = 1;
588 chip->poll_count++;
589 goto again;
590 }
591
592
593 if (!chip->polling_mode) {
594 dev_warn(chip->card->dev,
595 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
596 chip->last_cmd[addr]);
597 chip->polling_mode = 1;
598 goto again;
599 }
600
601 if (chip->msi) {
602 dev_warn(chip->card->dev,
603 "No response from codec, disabling MSI: last cmd=0x%08x\n",
604 chip->last_cmd[addr]);
605 if (chip->ops->disable_msi_reset_irq &&
606 chip->ops->disable_msi_reset_irq(chip) < 0) {
607 bus->rirb_error = 1;
608 return -1;
609 }
610 goto again;
611 }
612
613 if (chip->probing) {
614 /* If this critical timeout happens during the codec probing
615 * phase, this is likely an access to a non-existing codec
616 * slot. Better to return an error and reset the system.
617 */
618 return -1;
619 }
620
621 /* a fatal communication error; need either to reset or to fallback
622 * to the single_cmd mode
623 */
624 bus->rirb_error = 1;
625 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
626 bus->response_reset = 1;
627 return -1; /* give a chance to retry */
628 }
629
630 dev_err(chip->card->dev,
631 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
632 chip->last_cmd[addr]);
633 chip->single_cmd = 1;
634 bus->response_reset = 0;
635 /* release CORB/RIRB */
636 azx_free_cmd_io(chip);
637 /* disable unsolicited responses */
638 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
639 return -1;
640 }
641
642 /*
643 * Use the single immediate command instead of CORB/RIRB for simplicity
644 *
645 * Note: according to Intel, this is not preferred use. The command was
646 * intended for the BIOS only, and may get confused with unsolicited
647 * responses. So, we shouldn't use it for normal operation from the
648 * driver.
649 * I left the codes, however, for debugging/testing purposes.
650 */
651
652 /* receive a response */
653 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
654 {
655 int timeout = 50;
656
657 while (timeout--) {
658 /* check IRV busy bit */
659 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
660 /* reuse rirb.res as the response return value */
661 chip->rirb.res[addr] = azx_readl(chip, IR);
662 return 0;
663 }
664 udelay(1);
665 }
666 if (printk_ratelimit())
667 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
668 azx_readw(chip, IRS));
669 chip->rirb.res[addr] = -1;
670 return -EIO;
671 }
672
673 /* send a command */
674 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
675 {
676 struct azx *chip = bus->private_data;
677 unsigned int addr = azx_command_addr(val);
678 int timeout = 50;
679
680 bus->rirb_error = 0;
681 while (timeout--) {
682 /* check ICB busy bit */
683 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
684 /* Clear IRV valid bit */
685 azx_writew(chip, IRS, azx_readw(chip, IRS) |
686 ICH6_IRS_VALID);
687 azx_writel(chip, IC, val);
688 azx_writew(chip, IRS, azx_readw(chip, IRS) |
689 ICH6_IRS_BUSY);
690 return azx_single_wait_for_response(chip, addr);
691 }
692 udelay(1);
693 }
694 if (printk_ratelimit())
695 dev_dbg(chip->card->dev,
696 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
697 azx_readw(chip, IRS), val);
698 return -EIO;
699 }
700
701 /* receive a response */
702 static unsigned int azx_single_get_response(struct hda_bus *bus,
703 unsigned int addr)
704 {
705 struct azx *chip = bus->private_data;
706 return chip->rirb.res[addr];
707 }
708
709 /*
710 * The below are the main callbacks from hda_codec.
711 *
712 * They are just the skeleton to call sub-callbacks according to the
713 * current setting of chip->single_cmd.
714 */
715
716 /* send a command */
717 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
718 {
719 struct azx *chip = bus->private_data;
720
721 if (chip->disabled)
722 return 0;
723 chip->last_cmd[azx_command_addr(val)] = val;
724 if (chip->single_cmd)
725 return azx_single_send_cmd(bus, val);
726 else
727 return azx_corb_send_cmd(bus, val);
728 }
729
730 /* get a response */
731 static unsigned int azx_get_response(struct hda_bus *bus,
732 unsigned int addr)
733 {
734 struct azx *chip = bus->private_data;
735 if (chip->disabled)
736 return 0;
737 if (chip->single_cmd)
738 return azx_single_get_response(bus, addr);
739 else
740 return azx_rirb_get_response(bus, addr);
741 }
742
743 #ifdef CONFIG_PM
744 static void azx_power_notify(struct hda_bus *bus, bool power_up);
745 #endif
746
747 #ifdef CONFIG_SND_HDA_DSP_LOADER
748 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
749 unsigned int byte_size,
750 struct snd_dma_buffer *bufp);
751 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
752 static void azx_load_dsp_cleanup(struct hda_bus *bus,
753 struct snd_dma_buffer *dmab);
754 #endif
755
756 /* enter link reset */
757 static void azx_enter_link_reset(struct azx *chip)
758 {
759 unsigned long timeout;
760
761 /* reset controller */
762 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
763
764 timeout = jiffies + msecs_to_jiffies(100);
765 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
766 time_before(jiffies, timeout))
767 usleep_range(500, 1000);
768 }
769
770 /* exit link reset */
771 static void azx_exit_link_reset(struct azx *chip)
772 {
773 unsigned long timeout;
774
775 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
776
777 timeout = jiffies + msecs_to_jiffies(100);
778 while (!azx_readb(chip, GCTL) &&
779 time_before(jiffies, timeout))
780 usleep_range(500, 1000);
781 }
782
783 /* reset codec link */
784 static int azx_reset(struct azx *chip, int full_reset)
785 {
786 if (!full_reset)
787 goto __skip;
788
789 /* clear STATESTS */
790 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
791
792 /* reset controller */
793 azx_enter_link_reset(chip);
794
795 /* delay for >= 100us for codec PLL to settle per spec
796 * Rev 0.9 section 5.5.1
797 */
798 usleep_range(500, 1000);
799
800 /* Bring controller out of reset */
801 azx_exit_link_reset(chip);
802
803 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
804 usleep_range(1000, 1200);
805
806 __skip:
807 /* check to see if controller is ready */
808 if (!azx_readb(chip, GCTL)) {
809 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
810 return -EBUSY;
811 }
812
813 /* Accept unsolicited responses */
814 if (!chip->single_cmd)
815 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
816 ICH6_GCTL_UNSOL);
817
818 /* detect codecs */
819 if (!chip->codec_mask) {
820 chip->codec_mask = azx_readw(chip, STATESTS);
821 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
822 chip->codec_mask);
823 }
824
825 return 0;
826 }
827
828
829 /*
830 * Lowlevel interface
831 */
832
833 /* enable interrupts */
834 static void azx_int_enable(struct azx *chip)
835 {
836 /* enable controller CIE and GIE */
837 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
838 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
839 }
840
841 /* disable interrupts */
842 static void azx_int_disable(struct azx *chip)
843 {
844 int i;
845
846 /* disable interrupts in stream descriptor */
847 for (i = 0; i < chip->num_streams; i++) {
848 struct azx_dev *azx_dev = &chip->azx_dev[i];
849 azx_sd_writeb(chip, azx_dev, SD_CTL,
850 azx_sd_readb(chip, azx_dev, SD_CTL) &
851 ~SD_INT_MASK);
852 }
853
854 /* disable SIE for all streams */
855 azx_writeb(chip, INTCTL, 0);
856
857 /* disable controller CIE and GIE */
858 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
859 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
860 }
861
862 /* clear interrupts */
863 static void azx_int_clear(struct azx *chip)
864 {
865 int i;
866
867 /* clear stream status */
868 for (i = 0; i < chip->num_streams; i++) {
869 struct azx_dev *azx_dev = &chip->azx_dev[i];
870 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
871 }
872
873 /* clear STATESTS */
874 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
875
876 /* clear rirb status */
877 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
878
879 /* clear int status */
880 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
881 }
882
883 /* start a stream */
884 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
885 {
886 /*
887 * Before stream start, initialize parameter
888 */
889 azx_dev->insufficient = 1;
890
891 /* enable SIE */
892 azx_writel(chip, INTCTL,
893 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
894 /* set DMA start and interrupt mask */
895 azx_sd_writeb(chip, azx_dev, SD_CTL,
896 azx_sd_readb(chip, azx_dev, SD_CTL) |
897 SD_CTL_DMA_START | SD_INT_MASK);
898 }
899
900 /* stop DMA */
901 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
902 {
903 azx_sd_writeb(chip, azx_dev, SD_CTL,
904 azx_sd_readb(chip, azx_dev, SD_CTL) &
905 ~(SD_CTL_DMA_START | SD_INT_MASK));
906 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
907 }
908
909 /* stop a stream */
910 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
911 {
912 azx_stream_clear(chip, azx_dev);
913 /* disable SIE */
914 azx_writel(chip, INTCTL,
915 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
916 }
917
918
919 /*
920 * reset and start the controller registers
921 */
922 static void azx_init_chip(struct azx *chip, int full_reset)
923 {
924 if (chip->initialized)
925 return;
926
927 /* reset controller */
928 azx_reset(chip, full_reset);
929
930 /* initialize interrupts */
931 azx_int_clear(chip);
932 azx_int_enable(chip);
933
934 /* initialize the codec command I/O */
935 if (!chip->single_cmd)
936 azx_init_cmd_io(chip);
937
938 /* program the position buffer */
939 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
940 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
941
942 chip->initialized = 1;
943 }
944
945 /*
946 * initialize the PCI registers
947 */
948 /* update bits in a PCI register byte */
949 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
950 unsigned char mask, unsigned char val)
951 {
952 unsigned char data;
953
954 pci_read_config_byte(pci, reg, &data);
955 data &= ~mask;
956 data |= (val & mask);
957 pci_write_config_byte(pci, reg, data);
958 }
959
960 static void azx_init_pci(struct azx *chip)
961 {
962 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
963 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
964 * Ensuring these bits are 0 clears playback static on some HD Audio
965 * codecs.
966 * The PCI register TCSEL is defined in the Intel manuals.
967 */
968 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
969 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
970 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
971 }
972
973 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
974 * we need to enable snoop.
975 */
976 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
977 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
978 azx_snoop(chip));
979 update_pci_byte(chip->pci,
980 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
981 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
982 }
983
984 /* For NVIDIA HDA, enable snoop */
985 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
986 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
987 azx_snoop(chip));
988 update_pci_byte(chip->pci,
989 NVIDIA_HDA_TRANSREG_ADDR,
990 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
991 update_pci_byte(chip->pci,
992 NVIDIA_HDA_ISTRM_COH,
993 0x01, NVIDIA_HDA_ENABLE_COHBIT);
994 update_pci_byte(chip->pci,
995 NVIDIA_HDA_OSTRM_COH,
996 0x01, NVIDIA_HDA_ENABLE_COHBIT);
997 }
998
999 /* Enable SCH/PCH snoop if needed */
1000 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1001 unsigned short snoop;
1002 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1003 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1004 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1005 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1006 if (!azx_snoop(chip))
1007 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1008 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1009 pci_read_config_word(chip->pci,
1010 INTEL_SCH_HDA_DEVC, &snoop);
1011 }
1012 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
1013 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
1014 "Disabled" : "Enabled");
1015 }
1016 }
1017
1018
1019 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1020
1021 /*
1022 * interrupt handler
1023 */
1024 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1025 {
1026 struct azx *chip = dev_id;
1027 struct azx_dev *azx_dev;
1028 u32 status;
1029 u8 sd_status;
1030 int i, ok;
1031
1032 #ifdef CONFIG_PM_RUNTIME
1033 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1034 if (chip->card->dev->power.runtime_status != RPM_ACTIVE)
1035 return IRQ_NONE;
1036 #endif
1037
1038 spin_lock(&chip->reg_lock);
1039
1040 if (chip->disabled) {
1041 spin_unlock(&chip->reg_lock);
1042 return IRQ_NONE;
1043 }
1044
1045 status = azx_readl(chip, INTSTS);
1046 if (status == 0 || status == 0xffffffff) {
1047 spin_unlock(&chip->reg_lock);
1048 return IRQ_NONE;
1049 }
1050
1051 for (i = 0; i < chip->num_streams; i++) {
1052 azx_dev = &chip->azx_dev[i];
1053 if (status & azx_dev->sd_int_sta_mask) {
1054 sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
1055 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1056 if (!azx_dev->substream || !azx_dev->running ||
1057 !(sd_status & SD_INT_COMPLETE))
1058 continue;
1059 /* check whether this IRQ is really acceptable */
1060 ok = azx_position_ok(chip, azx_dev);
1061 if (ok == 1) {
1062 azx_dev->irq_pending = 0;
1063 spin_unlock(&chip->reg_lock);
1064 snd_pcm_period_elapsed(azx_dev->substream);
1065 spin_lock(&chip->reg_lock);
1066 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1067 /* bogus IRQ, process it later */
1068 azx_dev->irq_pending = 1;
1069 queue_work(chip->bus->workq,
1070 &chip->irq_pending_work);
1071 }
1072 }
1073 }
1074
1075 /* clear rirb int */
1076 status = azx_readb(chip, RIRBSTS);
1077 if (status & RIRB_INT_MASK) {
1078 if (status & RIRB_INT_RESPONSE) {
1079 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1080 udelay(80);
1081 azx_update_rirb(chip);
1082 }
1083 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1084 }
1085
1086 spin_unlock(&chip->reg_lock);
1087
1088 return IRQ_HANDLED;
1089 }
1090
1091
1092 /*
1093 * set up a BDL entry
1094 */
1095 static int setup_bdle(struct azx *chip,
1096 struct snd_dma_buffer *dmab,
1097 struct azx_dev *azx_dev, u32 **bdlp,
1098 int ofs, int size, int with_ioc)
1099 {
1100 u32 *bdl = *bdlp;
1101
1102 while (size > 0) {
1103 dma_addr_t addr;
1104 int chunk;
1105
1106 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1107 return -EINVAL;
1108
1109 addr = snd_sgbuf_get_addr(dmab, ofs);
1110 /* program the address field of the BDL entry */
1111 bdl[0] = cpu_to_le32((u32)addr);
1112 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1113 /* program the size field of the BDL entry */
1114 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1115 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1116 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1117 u32 remain = 0x1000 - (ofs & 0xfff);
1118 if (chunk > remain)
1119 chunk = remain;
1120 }
1121 bdl[2] = cpu_to_le32(chunk);
1122 /* program the IOC to enable interrupt
1123 * only when the whole fragment is processed
1124 */
1125 size -= chunk;
1126 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1127 bdl += 4;
1128 azx_dev->frags++;
1129 ofs += chunk;
1130 }
1131 *bdlp = bdl;
1132 return ofs;
1133 }
1134
1135 /*
1136 * set up BDL entries
1137 */
1138 static int azx_setup_periods(struct azx *chip,
1139 struct snd_pcm_substream *substream,
1140 struct azx_dev *azx_dev)
1141 {
1142 u32 *bdl;
1143 int i, ofs, periods, period_bytes;
1144 int pos_adj = 0;
1145
1146 /* reset BDL address */
1147 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1148 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1149
1150 period_bytes = azx_dev->period_bytes;
1151 periods = azx_dev->bufsize / period_bytes;
1152
1153 /* program the initial BDL entries */
1154 bdl = (u32 *)azx_dev->bdl.area;
1155 ofs = 0;
1156 azx_dev->frags = 0;
1157
1158 if (chip->bdl_pos_adj)
1159 pos_adj = chip->bdl_pos_adj[chip->dev_index];
1160 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1161 struct snd_pcm_runtime *runtime = substream->runtime;
1162 int pos_align = pos_adj;
1163 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1164 if (!pos_adj)
1165 pos_adj = pos_align;
1166 else
1167 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1168 pos_align;
1169 pos_adj = frames_to_bytes(runtime, pos_adj);
1170 if (pos_adj >= period_bytes) {
1171 dev_warn(chip->card->dev,"Too big adjustment %d\n",
1172 pos_adj);
1173 pos_adj = 0;
1174 } else {
1175 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1176 azx_dev,
1177 &bdl, ofs, pos_adj, true);
1178 if (ofs < 0)
1179 goto error;
1180 }
1181 } else
1182 pos_adj = 0;
1183
1184 for (i = 0; i < periods; i++) {
1185 if (i == periods - 1 && pos_adj)
1186 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1187 azx_dev, &bdl, ofs,
1188 period_bytes - pos_adj, 0);
1189 else
1190 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1191 azx_dev, &bdl, ofs,
1192 period_bytes,
1193 !azx_dev->no_period_wakeup);
1194 if (ofs < 0)
1195 goto error;
1196 }
1197 return 0;
1198
1199 error:
1200 dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
1201 azx_dev->bufsize, period_bytes);
1202 return -EINVAL;
1203 }
1204
1205 /* reset stream */
1206 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1207 {
1208 unsigned char val;
1209 int timeout;
1210
1211 azx_stream_clear(chip, azx_dev);
1212
1213 azx_sd_writeb(chip, azx_dev, SD_CTL,
1214 azx_sd_readb(chip, azx_dev, SD_CTL) |
1215 SD_CTL_STREAM_RESET);
1216 udelay(3);
1217 timeout = 300;
1218 while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
1219 SD_CTL_STREAM_RESET) && --timeout)
1220 ;
1221 val &= ~SD_CTL_STREAM_RESET;
1222 azx_sd_writeb(chip, azx_dev, SD_CTL, val);
1223 udelay(3);
1224
1225 timeout = 300;
1226 /* waiting for hardware to report that the stream is out of reset */
1227 while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
1228 SD_CTL_STREAM_RESET) && --timeout)
1229 ;
1230
1231 /* reset first position - may not be synced with hw at this time */
1232 *azx_dev->posbuf = 0;
1233 }
1234
1235 /*
1236 * set up the SD for streaming
1237 */
1238 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1239 {
1240 unsigned int val;
1241 /* make sure the run bit is zero for SD */
1242 azx_stream_clear(chip, azx_dev);
1243 /* program the stream_tag */
1244 val = azx_sd_readl(chip, azx_dev, SD_CTL);
1245 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1246 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1247 if (!azx_snoop(chip))
1248 val |= SD_CTL_TRAFFIC_PRIO;
1249 azx_sd_writel(chip, azx_dev, SD_CTL, val);
1250
1251 /* program the length of samples in cyclic buffer */
1252 azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
1253
1254 /* program the stream format */
1255 /* this value needs to be the same as the one programmed */
1256 azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
1257
1258 /* program the stream LVI (last valid index) of the BDL */
1259 azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
1260
1261 /* program the BDL address */
1262 /* lower BDL address */
1263 azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1264 /* upper BDL address */
1265 azx_sd_writel(chip, azx_dev, SD_BDLPU,
1266 upper_32_bits(azx_dev->bdl.addr));
1267
1268 /* enable the position buffer */
1269 if (chip->position_fix[0] != POS_FIX_LPIB ||
1270 chip->position_fix[1] != POS_FIX_LPIB) {
1271 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1272 azx_writel(chip, DPLBASE,
1273 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1274 }
1275
1276 /* set the interrupt enable bits in the descriptor control register */
1277 azx_sd_writel(chip, azx_dev, SD_CTL,
1278 azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
1279
1280 return 0;
1281 }
1282
1283 /*
1284 * Probe the given codec address
1285 */
1286 static int probe_codec(struct azx *chip, int addr)
1287 {
1288 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1289 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1290 unsigned int res;
1291
1292 mutex_lock(&chip->bus->cmd_mutex);
1293 chip->probing = 1;
1294 azx_send_cmd(chip->bus, cmd);
1295 res = azx_get_response(chip->bus, addr);
1296 chip->probing = 0;
1297 mutex_unlock(&chip->bus->cmd_mutex);
1298 if (res == -1)
1299 return -EIO;
1300 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1301 return 0;
1302 }
1303
1304 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1305 struct hda_pcm *cpcm);
1306 static void azx_stop_chip(struct azx *chip);
1307
1308 static void azx_bus_reset(struct hda_bus *bus)
1309 {
1310 struct azx *chip = bus->private_data;
1311
1312 bus->in_reset = 1;
1313 azx_stop_chip(chip);
1314 azx_init_chip(chip, 1);
1315 #ifdef CONFIG_PM
1316 if (chip->initialized) {
1317 struct azx_pcm *p;
1318 list_for_each_entry(p, &chip->pcm_list, list)
1319 snd_pcm_suspend_all(p->pcm);
1320 snd_hda_suspend(chip->bus);
1321 snd_hda_resume(chip->bus);
1322 }
1323 #endif
1324 bus->in_reset = 0;
1325 }
1326
1327 static int get_jackpoll_interval(struct azx *chip)
1328 {
1329 int i;
1330 unsigned int j;
1331
1332 if (!chip->jackpoll_ms)
1333 return 0;
1334
1335 i = chip->jackpoll_ms[chip->dev_index];
1336 if (i == 0)
1337 return 0;
1338 if (i < 50 || i > 60000)
1339 j = 0;
1340 else
1341 j = msecs_to_jiffies(i);
1342 if (j == 0)
1343 dev_warn(chip->card->dev,
1344 "jackpoll_ms value out of range: %d\n", i);
1345 return j;
1346 }
1347
1348 /*
1349 * Codec initialization
1350 */
1351
1352 static int azx_codec_create(struct azx *chip, const char *model,
1353 unsigned int max_slots,
1354 int *power_save_to)
1355 {
1356 struct hda_bus_template bus_temp;
1357 int c, codecs, err;
1358
1359 memset(&bus_temp, 0, sizeof(bus_temp));
1360 bus_temp.private_data = chip;
1361 bus_temp.modelname = model;
1362 bus_temp.pci = chip->pci;
1363 bus_temp.ops.command = azx_send_cmd;
1364 bus_temp.ops.get_response = azx_get_response;
1365 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1366 bus_temp.ops.bus_reset = azx_bus_reset;
1367 #ifdef CONFIG_PM
1368 bus_temp.power_save = power_save_to;
1369 bus_temp.ops.pm_notify = azx_power_notify;
1370 #endif
1371 #ifdef CONFIG_SND_HDA_DSP_LOADER
1372 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1373 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1374 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1375 #endif
1376
1377 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1378 if (err < 0)
1379 return err;
1380
1381 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1382 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1383 chip->bus->needs_damn_long_delay = 1;
1384 }
1385
1386 codecs = 0;
1387 if (!max_slots)
1388 max_slots = AZX_DEFAULT_CODECS;
1389
1390 /* First try to probe all given codec slots */
1391 for (c = 0; c < max_slots; c++) {
1392 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1393 if (probe_codec(chip, c) < 0) {
1394 /* Some BIOSen give you wrong codec addresses
1395 * that don't exist
1396 */
1397 dev_warn(chip->card->dev,
1398 "Codec #%d probe error; disabling it...\n", c);
1399 chip->codec_mask &= ~(1 << c);
1400 /* More badly, accessing to a non-existing
1401 * codec often screws up the controller chip,
1402 * and disturbs the further communications.
1403 * Thus if an error occurs during probing,
1404 * better to reset the controller chip to
1405 * get back to the sanity state.
1406 */
1407 azx_stop_chip(chip);
1408 azx_init_chip(chip, 1);
1409 }
1410 }
1411 }
1412
1413 /* AMD chipsets often cause the communication stalls upon certain
1414 * sequence like the pin-detection. It seems that forcing the synced
1415 * access works around the stall. Grrr...
1416 */
1417 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1418 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1419 chip->bus->sync_write = 1;
1420 chip->bus->allow_bus_reset = 1;
1421 }
1422
1423 /* Then create codec instances */
1424 for (c = 0; c < max_slots; c++) {
1425 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1426 struct hda_codec *codec;
1427 err = snd_hda_codec_new(chip->bus, c, &codec);
1428 if (err < 0)
1429 continue;
1430 codec->jackpoll_interval = get_jackpoll_interval(chip);
1431 codec->beep_mode = chip->beep_mode;
1432 codecs++;
1433 }
1434 }
1435 if (!codecs) {
1436 dev_err(chip->card->dev, "no codecs initialized\n");
1437 return -ENXIO;
1438 }
1439 return 0;
1440 }
1441
1442 /* configure each codec instance */
1443 static int azx_codec_configure(struct azx *chip)
1444 {
1445 struct hda_codec *codec;
1446 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1447 snd_hda_codec_configure(codec);
1448 }
1449 return 0;
1450 }
1451
1452
1453 /*
1454 * PCM support
1455 */
1456
1457 /* assign a stream for the PCM */
1458 static inline struct azx_dev *
1459 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1460 {
1461 int dev, i, nums;
1462 struct azx_dev *res = NULL;
1463 /* make a non-zero unique key for the substream */
1464 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1465 (substream->stream + 1);
1466
1467 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1468 dev = chip->playback_index_offset;
1469 nums = chip->playback_streams;
1470 } else {
1471 dev = chip->capture_index_offset;
1472 nums = chip->capture_streams;
1473 }
1474 for (i = 0; i < nums; i++, dev++) {
1475 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1476 dsp_lock(azx_dev);
1477 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1478 res = azx_dev;
1479 if (res->assigned_key == key) {
1480 res->opened = 1;
1481 res->assigned_key = key;
1482 dsp_unlock(azx_dev);
1483 return azx_dev;
1484 }
1485 }
1486 dsp_unlock(azx_dev);
1487 }
1488 if (res) {
1489 dsp_lock(res);
1490 res->opened = 1;
1491 res->assigned_key = key;
1492 dsp_unlock(res);
1493 }
1494 return res;
1495 }
1496
1497 /* release the assigned stream */
1498 static inline void azx_release_device(struct azx_dev *azx_dev)
1499 {
1500 azx_dev->opened = 0;
1501 }
1502
1503 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1504 {
1505 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1506 struct snd_pcm_substream *substream = azx_dev->substream;
1507 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1508 struct azx *chip = apcm->chip;
1509
1510 return azx_readl(chip, WALLCLK);
1511 }
1512
1513 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1514 bool force, cycle_t last)
1515 {
1516 struct azx_dev *azx_dev = get_azx_dev(substream);
1517 struct timecounter *tc = &azx_dev->azx_tc;
1518 struct cyclecounter *cc = &azx_dev->azx_cc;
1519 u64 nsec;
1520
1521 cc->read = azx_cc_read;
1522 cc->mask = CLOCKSOURCE_MASK(32);
1523
1524 /*
1525 * Converting from 24 MHz to ns means applying a 125/3 factor.
1526 * To avoid any saturation issues in intermediate operations,
1527 * the 125 factor is applied first. The division is applied
1528 * last after reading the timecounter value.
1529 * Applying the 1/3 factor as part of the multiplication
1530 * requires at least 20 bits for a decent precision, however
1531 * overflows occur after about 4 hours or less, not a option.
1532 */
1533
1534 cc->mult = 125; /* saturation after 195 years */
1535 cc->shift = 0;
1536
1537 nsec = 0; /* audio time is elapsed time since trigger */
1538 timecounter_init(tc, cc, nsec);
1539 if (force)
1540 /*
1541 * force timecounter to use predefined value,
1542 * used for synchronized starts
1543 */
1544 tc->cycle_last = last;
1545 }
1546
1547 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1548 u64 nsec)
1549 {
1550 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1551 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1552 u64 codec_frames, codec_nsecs;
1553
1554 if (!hinfo->ops.get_delay)
1555 return nsec;
1556
1557 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1558 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1559 substream->runtime->rate);
1560
1561 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1562 return nsec + codec_nsecs;
1563
1564 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1565 }
1566
1567 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1568 struct timespec *ts)
1569 {
1570 struct azx_dev *azx_dev = get_azx_dev(substream);
1571 u64 nsec;
1572
1573 nsec = timecounter_read(&azx_dev->azx_tc);
1574 nsec = div_u64(nsec, 3); /* can be optimized */
1575 nsec = azx_adjust_codec_delay(substream, nsec);
1576
1577 *ts = ns_to_timespec(nsec);
1578
1579 return 0;
1580 }
1581
1582 static struct snd_pcm_hardware azx_pcm_hw = {
1583 .info = (SNDRV_PCM_INFO_MMAP |
1584 SNDRV_PCM_INFO_INTERLEAVED |
1585 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1586 SNDRV_PCM_INFO_MMAP_VALID |
1587 /* No full-resume yet implemented */
1588 /* SNDRV_PCM_INFO_RESUME |*/
1589 SNDRV_PCM_INFO_PAUSE |
1590 SNDRV_PCM_INFO_SYNC_START |
1591 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1592 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1593 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1594 .rates = SNDRV_PCM_RATE_48000,
1595 .rate_min = 48000,
1596 .rate_max = 48000,
1597 .channels_min = 2,
1598 .channels_max = 2,
1599 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1600 .period_bytes_min = 128,
1601 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1602 .periods_min = 2,
1603 .periods_max = AZX_MAX_FRAG,
1604 .fifo_size = 0,
1605 };
1606
1607 static int azx_pcm_open(struct snd_pcm_substream *substream)
1608 {
1609 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1610 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1611 struct azx *chip = apcm->chip;
1612 struct azx_dev *azx_dev;
1613 struct snd_pcm_runtime *runtime = substream->runtime;
1614 unsigned long flags;
1615 int err;
1616 int buff_step;
1617
1618 mutex_lock(&chip->open_mutex);
1619 azx_dev = azx_assign_device(chip, substream);
1620 if (azx_dev == NULL) {
1621 mutex_unlock(&chip->open_mutex);
1622 return -EBUSY;
1623 }
1624 runtime->hw = azx_pcm_hw;
1625 runtime->hw.channels_min = hinfo->channels_min;
1626 runtime->hw.channels_max = hinfo->channels_max;
1627 runtime->hw.formats = hinfo->formats;
1628 runtime->hw.rates = hinfo->rates;
1629 snd_pcm_limit_hw_rates(runtime);
1630 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1631
1632 /* avoid wrap-around with wall-clock */
1633 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1634 20,
1635 178000000);
1636
1637 if (chip->align_buffer_size)
1638 /* constrain buffer sizes to be multiple of 128
1639 bytes. This is more efficient in terms of memory
1640 access but isn't required by the HDA spec and
1641 prevents users from specifying exact period/buffer
1642 sizes. For example for 44.1kHz, a period size set
1643 to 20ms will be rounded to 19.59ms. */
1644 buff_step = 128;
1645 else
1646 /* Don't enforce steps on buffer sizes, still need to
1647 be multiple of 4 bytes (HDA spec). Tested on Intel
1648 HDA controllers, may not work on all devices where
1649 option needs to be disabled */
1650 buff_step = 4;
1651
1652 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1653 buff_step);
1654 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1655 buff_step);
1656 snd_hda_power_up_d3wait(apcm->codec);
1657 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1658 if (err < 0) {
1659 azx_release_device(azx_dev);
1660 snd_hda_power_down(apcm->codec);
1661 mutex_unlock(&chip->open_mutex);
1662 return err;
1663 }
1664 snd_pcm_limit_hw_rates(runtime);
1665 /* sanity check */
1666 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1667 snd_BUG_ON(!runtime->hw.channels_max) ||
1668 snd_BUG_ON(!runtime->hw.formats) ||
1669 snd_BUG_ON(!runtime->hw.rates)) {
1670 azx_release_device(azx_dev);
1671 hinfo->ops.close(hinfo, apcm->codec, substream);
1672 snd_hda_power_down(apcm->codec);
1673 mutex_unlock(&chip->open_mutex);
1674 return -EINVAL;
1675 }
1676
1677 /* disable WALLCLOCK timestamps for capture streams
1678 until we figure out how to handle digital inputs */
1679 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1680 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1681
1682 spin_lock_irqsave(&chip->reg_lock, flags);
1683 azx_dev->substream = substream;
1684 azx_dev->running = 0;
1685 spin_unlock_irqrestore(&chip->reg_lock, flags);
1686
1687 runtime->private_data = azx_dev;
1688 snd_pcm_set_sync(substream);
1689 mutex_unlock(&chip->open_mutex);
1690 return 0;
1691 }
1692
1693 static int azx_pcm_close(struct snd_pcm_substream *substream)
1694 {
1695 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1696 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1697 struct azx *chip = apcm->chip;
1698 struct azx_dev *azx_dev = get_azx_dev(substream);
1699 unsigned long flags;
1700
1701 mutex_lock(&chip->open_mutex);
1702 spin_lock_irqsave(&chip->reg_lock, flags);
1703 azx_dev->substream = NULL;
1704 azx_dev->running = 0;
1705 spin_unlock_irqrestore(&chip->reg_lock, flags);
1706 azx_release_device(azx_dev);
1707 hinfo->ops.close(hinfo, apcm->codec, substream);
1708 snd_hda_power_down(apcm->codec);
1709 mutex_unlock(&chip->open_mutex);
1710 return 0;
1711 }
1712
1713 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1714 struct snd_pcm_hw_params *hw_params)
1715 {
1716 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1717 struct azx *chip = apcm->chip;
1718 int ret;
1719
1720 dsp_lock(get_azx_dev(substream));
1721 if (dsp_is_locked(get_azx_dev(substream))) {
1722 ret = -EBUSY;
1723 goto unlock;
1724 }
1725
1726 ret = chip->ops->substream_alloc_pages(chip, substream,
1727 params_buffer_bytes(hw_params));
1728 unlock:
1729 dsp_unlock(get_azx_dev(substream));
1730 return ret;
1731 }
1732
1733 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1734 {
1735 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1736 struct azx_dev *azx_dev = get_azx_dev(substream);
1737 struct azx *chip = apcm->chip;
1738 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1739 int err;
1740
1741 /* reset BDL address */
1742 dsp_lock(azx_dev);
1743 if (!dsp_is_locked(azx_dev)) {
1744 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1745 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1746 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
1747 azx_dev->bufsize = 0;
1748 azx_dev->period_bytes = 0;
1749 azx_dev->format_val = 0;
1750 }
1751
1752 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1753
1754 err = chip->ops->substream_free_pages(chip, substream);
1755 azx_dev->prepared = 0;
1756 dsp_unlock(azx_dev);
1757 return err;
1758 }
1759
1760 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1761 {
1762 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1763 struct azx *chip = apcm->chip;
1764 struct azx_dev *azx_dev = get_azx_dev(substream);
1765 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1766 struct snd_pcm_runtime *runtime = substream->runtime;
1767 unsigned int bufsize, period_bytes, format_val, stream_tag;
1768 int err;
1769 struct hda_spdif_out *spdif =
1770 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1771 unsigned short ctls = spdif ? spdif->ctls : 0;
1772
1773 dsp_lock(azx_dev);
1774 if (dsp_is_locked(azx_dev)) {
1775 err = -EBUSY;
1776 goto unlock;
1777 }
1778
1779 azx_stream_reset(chip, azx_dev);
1780 format_val = snd_hda_calc_stream_format(runtime->rate,
1781 runtime->channels,
1782 runtime->format,
1783 hinfo->maxbps,
1784 ctls);
1785 if (!format_val) {
1786 dev_err(chip->card->dev,
1787 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1788 runtime->rate, runtime->channels, runtime->format);
1789 err = -EINVAL;
1790 goto unlock;
1791 }
1792
1793 bufsize = snd_pcm_lib_buffer_bytes(substream);
1794 period_bytes = snd_pcm_lib_period_bytes(substream);
1795
1796 dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1797 bufsize, format_val);
1798
1799 if (bufsize != azx_dev->bufsize ||
1800 period_bytes != azx_dev->period_bytes ||
1801 format_val != azx_dev->format_val ||
1802 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
1803 azx_dev->bufsize = bufsize;
1804 azx_dev->period_bytes = period_bytes;
1805 azx_dev->format_val = format_val;
1806 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
1807 err = azx_setup_periods(chip, substream, azx_dev);
1808 if (err < 0)
1809 goto unlock;
1810 }
1811
1812 /* when LPIB delay correction gives a small negative value,
1813 * we ignore it; currently set the threshold statically to
1814 * 64 frames
1815 */
1816 if (runtime->period_size > 64)
1817 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
1818 else
1819 azx_dev->delay_negative_threshold = 0;
1820
1821 /* wallclk has 24Mhz clock source */
1822 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1823 runtime->rate) * 1000);
1824 azx_setup_controller(chip, azx_dev);
1825 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1826 azx_dev->fifo_size =
1827 azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
1828 else
1829 azx_dev->fifo_size = 0;
1830
1831 stream_tag = azx_dev->stream_tag;
1832 /* CA-IBG chips need the playback stream starting from 1 */
1833 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1834 stream_tag > chip->capture_streams)
1835 stream_tag -= chip->capture_streams;
1836 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1837 azx_dev->format_val, substream);
1838
1839 unlock:
1840 if (!err)
1841 azx_dev->prepared = 1;
1842 dsp_unlock(azx_dev);
1843 return err;
1844 }
1845
1846 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1847 {
1848 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1849 struct azx *chip = apcm->chip;
1850 struct azx_dev *azx_dev;
1851 struct snd_pcm_substream *s;
1852 int rstart = 0, start, nsync = 0, sbits = 0;
1853 int nwait, timeout;
1854
1855 azx_dev = get_azx_dev(substream);
1856 trace_azx_pcm_trigger(chip, azx_dev, cmd);
1857
1858 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
1859 return -EPIPE;
1860
1861 switch (cmd) {
1862 case SNDRV_PCM_TRIGGER_START:
1863 rstart = 1;
1864 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1865 case SNDRV_PCM_TRIGGER_RESUME:
1866 start = 1;
1867 break;
1868 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1869 case SNDRV_PCM_TRIGGER_SUSPEND:
1870 case SNDRV_PCM_TRIGGER_STOP:
1871 start = 0;
1872 break;
1873 default:
1874 return -EINVAL;
1875 }
1876
1877 snd_pcm_group_for_each_entry(s, substream) {
1878 if (s->pcm->card != substream->pcm->card)
1879 continue;
1880 azx_dev = get_azx_dev(s);
1881 sbits |= 1 << azx_dev->index;
1882 nsync++;
1883 snd_pcm_trigger_done(s, substream);
1884 }
1885
1886 spin_lock(&chip->reg_lock);
1887
1888 /* first, set SYNC bits of corresponding streams */
1889 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1890 azx_writel(chip, OLD_SSYNC,
1891 azx_readl(chip, OLD_SSYNC) | sbits);
1892 else
1893 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1894
1895 snd_pcm_group_for_each_entry(s, substream) {
1896 if (s->pcm->card != substream->pcm->card)
1897 continue;
1898 azx_dev = get_azx_dev(s);
1899 if (start) {
1900 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1901 if (!rstart)
1902 azx_dev->start_wallclk -=
1903 azx_dev->period_wallclk;
1904 azx_stream_start(chip, azx_dev);
1905 } else {
1906 azx_stream_stop(chip, azx_dev);
1907 }
1908 azx_dev->running = start;
1909 }
1910 spin_unlock(&chip->reg_lock);
1911 if (start) {
1912 /* wait until all FIFOs get ready */
1913 for (timeout = 5000; timeout; timeout--) {
1914 nwait = 0;
1915 snd_pcm_group_for_each_entry(s, substream) {
1916 if (s->pcm->card != substream->pcm->card)
1917 continue;
1918 azx_dev = get_azx_dev(s);
1919 if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
1920 SD_STS_FIFO_READY))
1921 nwait++;
1922 }
1923 if (!nwait)
1924 break;
1925 cpu_relax();
1926 }
1927 } else {
1928 /* wait until all RUN bits are cleared */
1929 for (timeout = 5000; timeout; timeout--) {
1930 nwait = 0;
1931 snd_pcm_group_for_each_entry(s, substream) {
1932 if (s->pcm->card != substream->pcm->card)
1933 continue;
1934 azx_dev = get_azx_dev(s);
1935 if (azx_sd_readb(chip, azx_dev, SD_CTL) &
1936 SD_CTL_DMA_START)
1937 nwait++;
1938 }
1939 if (!nwait)
1940 break;
1941 cpu_relax();
1942 }
1943 }
1944 spin_lock(&chip->reg_lock);
1945 /* reset SYNC bits */
1946 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1947 azx_writel(chip, OLD_SSYNC,
1948 azx_readl(chip, OLD_SSYNC) & ~sbits);
1949 else
1950 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1951 if (start) {
1952 azx_timecounter_init(substream, 0, 0);
1953 if (nsync > 1) {
1954 cycle_t cycle_last;
1955
1956 /* same start cycle for master and group */
1957 azx_dev = get_azx_dev(substream);
1958 cycle_last = azx_dev->azx_tc.cycle_last;
1959
1960 snd_pcm_group_for_each_entry(s, substream) {
1961 if (s->pcm->card != substream->pcm->card)
1962 continue;
1963 azx_timecounter_init(s, 1, cycle_last);
1964 }
1965 }
1966 }
1967 spin_unlock(&chip->reg_lock);
1968 return 0;
1969 }
1970
1971 /* get the current DMA position with correction on VIA chips */
1972 static unsigned int azx_via_get_position(struct azx *chip,
1973 struct azx_dev *azx_dev)
1974 {
1975 unsigned int link_pos, mini_pos, bound_pos;
1976 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1977 unsigned int fifo_size;
1978
1979 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
1980 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1981 /* Playback, no problem using link position */
1982 return link_pos;
1983 }
1984
1985 /* Capture */
1986 /* For new chipset,
1987 * use mod to get the DMA position just like old chipset
1988 */
1989 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1990 mod_dma_pos %= azx_dev->period_bytes;
1991
1992 /* azx_dev->fifo_size can't get FIFO size of in stream.
1993 * Get from base address + offset.
1994 */
1995 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1996
1997 if (azx_dev->insufficient) {
1998 /* Link position never gather than FIFO size */
1999 if (link_pos <= fifo_size)
2000 return 0;
2001
2002 azx_dev->insufficient = 0;
2003 }
2004
2005 if (link_pos <= fifo_size)
2006 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2007 else
2008 mini_pos = link_pos - fifo_size;
2009
2010 /* Find nearest previous boudary */
2011 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2012 mod_link_pos = link_pos % azx_dev->period_bytes;
2013 if (mod_link_pos >= fifo_size)
2014 bound_pos = link_pos - mod_link_pos;
2015 else if (mod_dma_pos >= mod_mini_pos)
2016 bound_pos = mini_pos - mod_mini_pos;
2017 else {
2018 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2019 if (bound_pos >= azx_dev->bufsize)
2020 bound_pos = 0;
2021 }
2022
2023 /* Calculate real DMA position we want */
2024 return bound_pos + mod_dma_pos;
2025 }
2026
2027 static unsigned int azx_get_position(struct azx *chip,
2028 struct azx_dev *azx_dev,
2029 bool with_check)
2030 {
2031 struct snd_pcm_substream *substream = azx_dev->substream;
2032 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2033 unsigned int pos;
2034 int stream = substream->stream;
2035 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2036 int delay = 0;
2037
2038 switch (chip->position_fix[stream]) {
2039 case POS_FIX_LPIB:
2040 /* read LPIB */
2041 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2042 break;
2043 case POS_FIX_VIACOMBO:
2044 pos = azx_via_get_position(chip, azx_dev);
2045 break;
2046 default:
2047 /* use the position buffer */
2048 pos = le32_to_cpu(*azx_dev->posbuf);
2049 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2050 if (!pos || pos == (u32)-1) {
2051 dev_info(chip->card->dev,
2052 "Invalid position buffer, using LPIB read method instead.\n");
2053 chip->position_fix[stream] = POS_FIX_LPIB;
2054 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2055 } else
2056 chip->position_fix[stream] = POS_FIX_POSBUF;
2057 }
2058 break;
2059 }
2060
2061 if (pos >= azx_dev->bufsize)
2062 pos = 0;
2063
2064 /* calculate runtime delay from LPIB */
2065 if (substream->runtime &&
2066 chip->position_fix[stream] == POS_FIX_POSBUF &&
2067 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2068 unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2069 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2070 delay = pos - lpib_pos;
2071 else
2072 delay = lpib_pos - pos;
2073 if (delay < 0) {
2074 if (delay >= azx_dev->delay_negative_threshold)
2075 delay = 0;
2076 else
2077 delay += azx_dev->bufsize;
2078 }
2079 if (delay >= azx_dev->period_bytes) {
2080 dev_info(chip->card->dev,
2081 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
2082 delay, azx_dev->period_bytes);
2083 delay = 0;
2084 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2085 }
2086 delay = bytes_to_frames(substream->runtime, delay);
2087 }
2088
2089 if (substream->runtime) {
2090 if (hinfo->ops.get_delay)
2091 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2092 substream);
2093 substream->runtime->delay = delay;
2094 }
2095
2096 trace_azx_get_position(chip, azx_dev, pos, delay);
2097 return pos;
2098 }
2099
2100 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2101 {
2102 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2103 struct azx *chip = apcm->chip;
2104 struct azx_dev *azx_dev = get_azx_dev(substream);
2105 return bytes_to_frames(substream->runtime,
2106 azx_get_position(chip, azx_dev, false));
2107 }
2108
2109 /*
2110 * Check whether the current DMA position is acceptable for updating
2111 * periods. Returns non-zero if it's OK.
2112 *
2113 * Many HD-audio controllers appear pretty inaccurate about
2114 * the update-IRQ timing. The IRQ is issued before actually the
2115 * data is processed. So, we need to process it afterwords in a
2116 * workqueue.
2117 */
2118 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2119 {
2120 u32 wallclk;
2121 unsigned int pos;
2122
2123 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2124 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2125 return -1; /* bogus (too early) interrupt */
2126
2127 pos = azx_get_position(chip, azx_dev, true);
2128
2129 if (WARN_ONCE(!azx_dev->period_bytes,
2130 "hda-intel: zero azx_dev->period_bytes"))
2131 return -1; /* this shouldn't happen! */
2132 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2133 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2134 /* NG - it's below the first next period boundary */
2135 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
2136 azx_dev->start_wallclk += wallclk;
2137 return 1; /* OK, it's fine */
2138 }
2139
2140 /*
2141 * The work for pending PCM period updates.
2142 */
2143 static void azx_irq_pending_work(struct work_struct *work)
2144 {
2145 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2146 int i, pending, ok;
2147
2148 if (!chip->irq_pending_warned) {
2149 dev_info(chip->card->dev,
2150 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
2151 chip->card->number);
2152 chip->irq_pending_warned = 1;
2153 }
2154
2155 for (;;) {
2156 pending = 0;
2157 spin_lock_irq(&chip->reg_lock);
2158 for (i = 0; i < chip->num_streams; i++) {
2159 struct azx_dev *azx_dev = &chip->azx_dev[i];
2160 if (!azx_dev->irq_pending ||
2161 !azx_dev->substream ||
2162 !azx_dev->running)
2163 continue;
2164 ok = azx_position_ok(chip, azx_dev);
2165 if (ok > 0) {
2166 azx_dev->irq_pending = 0;
2167 spin_unlock(&chip->reg_lock);
2168 snd_pcm_period_elapsed(azx_dev->substream);
2169 spin_lock(&chip->reg_lock);
2170 } else if (ok < 0) {
2171 pending = 0; /* too early */
2172 } else
2173 pending++;
2174 }
2175 spin_unlock_irq(&chip->reg_lock);
2176 if (!pending)
2177 return;
2178 msleep(1);
2179 }
2180 }
2181
2182 /* clear irq_pending flags and assure no on-going workq */
2183 static void azx_clear_irq_pending(struct azx *chip)
2184 {
2185 int i;
2186
2187 spin_lock_irq(&chip->reg_lock);
2188 for (i = 0; i < chip->num_streams; i++)
2189 chip->azx_dev[i].irq_pending = 0;
2190 spin_unlock_irq(&chip->reg_lock);
2191 }
2192
2193 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2194 struct vm_area_struct *area)
2195 {
2196 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2197 struct azx *chip = apcm->chip;
2198 if (chip->ops->pcm_mmap_prepare)
2199 chip->ops->pcm_mmap_prepare(substream, area);
2200 return snd_pcm_lib_default_mmap(substream, area);
2201 }
2202
2203 static struct snd_pcm_ops azx_pcm_ops = {
2204 .open = azx_pcm_open,
2205 .close = azx_pcm_close,
2206 .ioctl = snd_pcm_lib_ioctl,
2207 .hw_params = azx_pcm_hw_params,
2208 .hw_free = azx_pcm_hw_free,
2209 .prepare = azx_pcm_prepare,
2210 .trigger = azx_pcm_trigger,
2211 .pointer = azx_pcm_pointer,
2212 .wall_clock = azx_get_wallclock_tstamp,
2213 .mmap = azx_pcm_mmap,
2214 .page = snd_pcm_sgbuf_ops_page,
2215 };
2216
2217 static void azx_pcm_free(struct snd_pcm *pcm)
2218 {
2219 struct azx_pcm *apcm = pcm->private_data;
2220 if (apcm) {
2221 list_del(&apcm->list);
2222 kfree(apcm);
2223 }
2224 }
2225
2226 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2227
2228 static int
2229 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2230 struct hda_pcm *cpcm)
2231 {
2232 struct azx *chip = bus->private_data;
2233 struct snd_pcm *pcm;
2234 struct azx_pcm *apcm;
2235 int pcm_dev = cpcm->device;
2236 unsigned int size;
2237 int s, err;
2238
2239 list_for_each_entry(apcm, &chip->pcm_list, list) {
2240 if (apcm->pcm->device == pcm_dev) {
2241 dev_err(chip->card->dev, "PCM %d already exists\n",
2242 pcm_dev);
2243 return -EBUSY;
2244 }
2245 }
2246 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2247 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2248 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2249 &pcm);
2250 if (err < 0)
2251 return err;
2252 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2253 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2254 if (apcm == NULL)
2255 return -ENOMEM;
2256 apcm->chip = chip;
2257 apcm->pcm = pcm;
2258 apcm->codec = codec;
2259 pcm->private_data = apcm;
2260 pcm->private_free = azx_pcm_free;
2261 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2262 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2263 list_add_tail(&apcm->list, &chip->pcm_list);
2264 cpcm->pcm = pcm;
2265 for (s = 0; s < 2; s++) {
2266 apcm->hinfo[s] = &cpcm->stream[s];
2267 if (cpcm->stream[s].substreams)
2268 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2269 }
2270 /* buffer pre-allocation */
2271 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2272 if (size > MAX_PREALLOC_SIZE)
2273 size = MAX_PREALLOC_SIZE;
2274 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2275 chip->card->dev,
2276 size, MAX_PREALLOC_SIZE);
2277 /* link to codec */
2278 pcm->dev = &codec->dev;
2279 return 0;
2280 }
2281
2282 /*
2283 * mixer creation - all stuff is implemented in hda module
2284 */
2285 static int azx_mixer_create(struct azx *chip)
2286 {
2287 return snd_hda_build_controls(chip->bus);
2288 }
2289
2290
2291 /*
2292 * initialize SD streams
2293 */
2294 static int azx_init_stream(struct azx *chip)
2295 {
2296 int i;
2297
2298 /* initialize each stream (aka device)
2299 * assign the starting bdl address to each stream (device)
2300 * and initialize
2301 */
2302 for (i = 0; i < chip->num_streams; i++) {
2303 struct azx_dev *azx_dev = &chip->azx_dev[i];
2304 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2305 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2306 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2307 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2308 azx_dev->sd_int_sta_mask = 1 << i;
2309 /* stream tag: must be non-zero and unique */
2310 azx_dev->index = i;
2311 azx_dev->stream_tag = i + 1;
2312 }
2313
2314 return 0;
2315 }
2316
2317 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2318 {
2319 if (request_irq(chip->pci->irq, azx_interrupt,
2320 chip->msi ? 0 : IRQF_SHARED,
2321 KBUILD_MODNAME, chip)) {
2322 dev_err(chip->card->dev,
2323 "unable to grab IRQ %d, disabling device\n",
2324 chip->pci->irq);
2325 if (do_disconnect)
2326 snd_card_disconnect(chip->card);
2327 return -1;
2328 }
2329 chip->irq = chip->pci->irq;
2330 pci_intx(chip->pci, !chip->msi);
2331 return 0;
2332 }
2333
2334
2335 static void azx_stop_chip(struct azx *chip)
2336 {
2337 if (!chip->initialized)
2338 return;
2339
2340 /* disable interrupts */
2341 azx_int_disable(chip);
2342 azx_int_clear(chip);
2343
2344 /* disable CORB/RIRB */
2345 azx_free_cmd_io(chip);
2346
2347 /* disable position buffer */
2348 azx_writel(chip, DPLBASE, 0);
2349 azx_writel(chip, DPUBASE, 0);
2350
2351 chip->initialized = 0;
2352 }
2353
2354 #ifdef CONFIG_SND_HDA_DSP_LOADER
2355 /*
2356 * DSP loading code (e.g. for CA0132)
2357 */
2358
2359 /* use the first stream for loading DSP */
2360 static struct azx_dev *
2361 azx_get_dsp_loader_dev(struct azx *chip)
2362 {
2363 return &chip->azx_dev[chip->playback_index_offset];
2364 }
2365
2366 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2367 unsigned int byte_size,
2368 struct snd_dma_buffer *bufp)
2369 {
2370 u32 *bdl;
2371 struct azx *chip = bus->private_data;
2372 struct azx_dev *azx_dev;
2373 int err;
2374
2375 azx_dev = azx_get_dsp_loader_dev(chip);
2376
2377 dsp_lock(azx_dev);
2378 spin_lock_irq(&chip->reg_lock);
2379 if (azx_dev->running || azx_dev->locked) {
2380 spin_unlock_irq(&chip->reg_lock);
2381 err = -EBUSY;
2382 goto unlock;
2383 }
2384 azx_dev->prepared = 0;
2385 chip->saved_azx_dev = *azx_dev;
2386 azx_dev->locked = 1;
2387 spin_unlock_irq(&chip->reg_lock);
2388
2389 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG,
2390 byte_size, bufp);
2391 if (err < 0)
2392 goto err_alloc;
2393
2394 azx_dev->bufsize = byte_size;
2395 azx_dev->period_bytes = byte_size;
2396 azx_dev->format_val = format;
2397
2398 azx_stream_reset(chip, azx_dev);
2399
2400 /* reset BDL address */
2401 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
2402 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
2403
2404 azx_dev->frags = 0;
2405 bdl = (u32 *)azx_dev->bdl.area;
2406 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2407 if (err < 0)
2408 goto error;
2409
2410 azx_setup_controller(chip, azx_dev);
2411 dsp_unlock(azx_dev);
2412 return azx_dev->stream_tag;
2413
2414 error:
2415 chip->ops->dma_free_pages(chip, bufp);
2416 err_alloc:
2417 spin_lock_irq(&chip->reg_lock);
2418 if (azx_dev->opened)
2419 *azx_dev = chip->saved_azx_dev;
2420 azx_dev->locked = 0;
2421 spin_unlock_irq(&chip->reg_lock);
2422 unlock:
2423 dsp_unlock(azx_dev);
2424 return err;
2425 }
2426
2427 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2428 {
2429 struct azx *chip = bus->private_data;
2430 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2431
2432 if (start)
2433 azx_stream_start(chip, azx_dev);
2434 else
2435 azx_stream_stop(chip, azx_dev);
2436 azx_dev->running = start;
2437 }
2438
2439 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2440 struct snd_dma_buffer *dmab)
2441 {
2442 struct azx *chip = bus->private_data;
2443 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2444
2445 if (!dmab->area || !azx_dev->locked)
2446 return;
2447
2448 dsp_lock(azx_dev);
2449 /* reset BDL address */
2450 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
2451 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
2452 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
2453 azx_dev->bufsize = 0;
2454 azx_dev->period_bytes = 0;
2455 azx_dev->format_val = 0;
2456
2457 chip->ops->dma_free_pages(chip, dmab);
2458 dmab->area = NULL;
2459
2460 spin_lock_irq(&chip->reg_lock);
2461 if (azx_dev->opened)
2462 *azx_dev = chip->saved_azx_dev;
2463 azx_dev->locked = 0;
2464 spin_unlock_irq(&chip->reg_lock);
2465 dsp_unlock(azx_dev);
2466 }
2467 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2468
2469 #ifdef CONFIG_PM
2470 /* power-up/down the controller */
2471 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2472 {
2473 struct azx *chip = bus->private_data;
2474
2475 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2476 return;
2477
2478 if (power_up)
2479 pm_runtime_get_sync(chip->card->dev);
2480 else
2481 pm_runtime_put_sync(chip->card->dev);
2482 }
2483
2484 static DEFINE_MUTEX(card_list_lock);
2485 static LIST_HEAD(card_list);
2486
2487 static void azx_add_card_list(struct azx *chip)
2488 {
2489 mutex_lock(&card_list_lock);
2490 list_add(&chip->list, &card_list);
2491 mutex_unlock(&card_list_lock);
2492 }
2493
2494 static void azx_del_card_list(struct azx *chip)
2495 {
2496 mutex_lock(&card_list_lock);
2497 list_del_init(&chip->list);
2498 mutex_unlock(&card_list_lock);
2499 }
2500
2501 /* trigger power-save check at writing parameter */
2502 static int param_set_xint(const char *val, const struct kernel_param *kp)
2503 {
2504 struct azx *chip;
2505 struct hda_codec *c;
2506 int prev = power_save;
2507 int ret = param_set_int(val, kp);
2508
2509 if (ret || prev == power_save)
2510 return ret;
2511
2512 mutex_lock(&card_list_lock);
2513 list_for_each_entry(chip, &card_list, list) {
2514 if (!chip->bus || chip->disabled)
2515 continue;
2516 list_for_each_entry(c, &chip->bus->codec_list, list)
2517 snd_hda_power_sync(c);
2518 }
2519 mutex_unlock(&card_list_lock);
2520 return 0;
2521 }
2522 #else
2523 #define azx_add_card_list(chip) /* NOP */
2524 #define azx_del_card_list(chip) /* NOP */
2525 #endif /* CONFIG_PM */
2526
2527 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2528 /*
2529 * power management
2530 */
2531 static int azx_suspend(struct device *dev)
2532 {
2533 struct pci_dev *pci = to_pci_dev(dev);
2534 struct snd_card *card = dev_get_drvdata(dev);
2535 struct azx *chip = card->private_data;
2536 struct azx_pcm *p;
2537
2538 if (chip->disabled)
2539 return 0;
2540
2541 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2542 azx_clear_irq_pending(chip);
2543 list_for_each_entry(p, &chip->pcm_list, list)
2544 snd_pcm_suspend_all(p->pcm);
2545 if (chip->initialized)
2546 snd_hda_suspend(chip->bus);
2547 azx_stop_chip(chip);
2548 azx_enter_link_reset(chip);
2549 if (chip->irq >= 0) {
2550 free_irq(chip->irq, chip);
2551 chip->irq = -1;
2552 }
2553 if (chip->msi)
2554 pci_disable_msi(chip->pci);
2555 pci_disable_device(pci);
2556 pci_save_state(pci);
2557 pci_set_power_state(pci, PCI_D3hot);
2558 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2559 hda_display_power(false);
2560 return 0;
2561 }
2562
2563 static int azx_resume(struct device *dev)
2564 {
2565 struct pci_dev *pci = to_pci_dev(dev);
2566 struct snd_card *card = dev_get_drvdata(dev);
2567 struct azx *chip = card->private_data;
2568
2569 if (chip->disabled)
2570 return 0;
2571
2572 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2573 hda_display_power(true);
2574 pci_set_power_state(pci, PCI_D0);
2575 pci_restore_state(pci);
2576 if (pci_enable_device(pci) < 0) {
2577 dev_err(chip->card->dev,
2578 "pci_enable_device failed, disabling device\n");
2579 snd_card_disconnect(card);
2580 return -EIO;
2581 }
2582 pci_set_master(pci);
2583 if (chip->msi)
2584 if (pci_enable_msi(pci) < 0)
2585 chip->msi = 0;
2586 if (azx_acquire_irq(chip, 1) < 0)
2587 return -EIO;
2588 azx_init_pci(chip);
2589
2590 azx_init_chip(chip, 1);
2591
2592 snd_hda_resume(chip->bus);
2593 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2594 return 0;
2595 }
2596 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2597
2598 #ifdef CONFIG_PM_RUNTIME
2599 static int azx_runtime_suspend(struct device *dev)
2600 {
2601 struct snd_card *card = dev_get_drvdata(dev);
2602 struct azx *chip = card->private_data;
2603
2604 if (chip->disabled)
2605 return 0;
2606
2607 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2608 return 0;
2609
2610 /* enable controller wake up event */
2611 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
2612 STATESTS_INT_MASK);
2613
2614 azx_stop_chip(chip);
2615 azx_enter_link_reset(chip);
2616 azx_clear_irq_pending(chip);
2617 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2618 hda_display_power(false);
2619 return 0;
2620 }
2621
2622 static int azx_runtime_resume(struct device *dev)
2623 {
2624 struct snd_card *card = dev_get_drvdata(dev);
2625 struct azx *chip = card->private_data;
2626 struct hda_bus *bus;
2627 struct hda_codec *codec;
2628 int status;
2629
2630 if (chip->disabled)
2631 return 0;
2632
2633 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2634 return 0;
2635
2636 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2637 hda_display_power(true);
2638
2639 /* Read STATESTS before controller reset */
2640 status = azx_readw(chip, STATESTS);
2641
2642 azx_init_pci(chip);
2643 azx_init_chip(chip, 1);
2644
2645 bus = chip->bus;
2646 if (status && bus) {
2647 list_for_each_entry(codec, &bus->codec_list, list)
2648 if (status & (1 << codec->addr))
2649 queue_delayed_work(codec->bus->workq,
2650 &codec->jackpoll_work, codec->jackpoll_interval);
2651 }
2652
2653 /* disable controller Wake Up event*/
2654 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
2655 ~STATESTS_INT_MASK);
2656
2657 return 0;
2658 }
2659
2660 static int azx_runtime_idle(struct device *dev)
2661 {
2662 struct snd_card *card = dev_get_drvdata(dev);
2663 struct azx *chip = card->private_data;
2664
2665 if (chip->disabled)
2666 return 0;
2667
2668 if (!power_save_controller ||
2669 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2670 return -EBUSY;
2671
2672 return 0;
2673 }
2674
2675 #endif /* CONFIG_PM_RUNTIME */
2676
2677 #ifdef CONFIG_PM
2678 static const struct dev_pm_ops azx_pm = {
2679 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2680 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2681 };
2682
2683 #define AZX_PM_OPS &azx_pm
2684 #else
2685 #define AZX_PM_OPS NULL
2686 #endif /* CONFIG_PM */
2687
2688
2689 /*
2690 * reboot notifier for hang-up problem at power-down
2691 */
2692 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2693 {
2694 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2695 snd_hda_bus_reboot_notify(chip->bus);
2696 azx_stop_chip(chip);
2697 return NOTIFY_OK;
2698 }
2699
2700 static void azx_notifier_register(struct azx *chip)
2701 {
2702 chip->reboot_notifier.notifier_call = azx_halt;
2703 register_reboot_notifier(&chip->reboot_notifier);
2704 }
2705
2706 static void azx_notifier_unregister(struct azx *chip)
2707 {
2708 if (chip->reboot_notifier.notifier_call)
2709 unregister_reboot_notifier(&chip->reboot_notifier);
2710 }
2711
2712 static int azx_probe_continue(struct azx *chip);
2713
2714 #ifdef SUPPORT_VGA_SWITCHEROO
2715 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2716
2717 static void azx_vs_set_state(struct pci_dev *pci,
2718 enum vga_switcheroo_state state)
2719 {
2720 struct snd_card *card = pci_get_drvdata(pci);
2721 struct azx *chip = card->private_data;
2722 bool disabled;
2723
2724 wait_for_completion(&chip->probe_wait);
2725 if (chip->init_failed)
2726 return;
2727
2728 disabled = (state == VGA_SWITCHEROO_OFF);
2729 if (chip->disabled == disabled)
2730 return;
2731
2732 if (!chip->bus) {
2733 chip->disabled = disabled;
2734 if (!disabled) {
2735 dev_info(chip->card->dev,
2736 "Start delayed initialization\n");
2737 if (azx_probe_continue(chip) < 0) {
2738 dev_err(chip->card->dev, "initialization error\n");
2739 chip->init_failed = true;
2740 }
2741 }
2742 } else {
2743 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
2744 disabled ? "Disabling" : "Enabling");
2745 if (disabled) {
2746 pm_runtime_put_sync_suspend(card->dev);
2747 azx_suspend(card->dev);
2748 /* when we get suspended by vga switcheroo we end up in D3cold,
2749 * however we have no ACPI handle, so pci/acpi can't put us there,
2750 * put ourselves there */
2751 pci->current_state = PCI_D3cold;
2752 chip->disabled = true;
2753 if (snd_hda_lock_devices(chip->bus))
2754 dev_warn(chip->card->dev,
2755 "Cannot lock devices!\n");
2756 } else {
2757 snd_hda_unlock_devices(chip->bus);
2758 pm_runtime_get_noresume(card->dev);
2759 chip->disabled = false;
2760 azx_resume(card->dev);
2761 }
2762 }
2763 }
2764
2765 static bool azx_vs_can_switch(struct pci_dev *pci)
2766 {
2767 struct snd_card *card = pci_get_drvdata(pci);
2768 struct azx *chip = card->private_data;
2769
2770 wait_for_completion(&chip->probe_wait);
2771 if (chip->init_failed)
2772 return false;
2773 if (chip->disabled || !chip->bus)
2774 return true;
2775 if (snd_hda_lock_devices(chip->bus))
2776 return false;
2777 snd_hda_unlock_devices(chip->bus);
2778 return true;
2779 }
2780
2781 static void init_vga_switcheroo(struct azx *chip)
2782 {
2783 struct pci_dev *p = get_bound_vga(chip->pci);
2784 if (p) {
2785 dev_info(chip->card->dev,
2786 "Handle VGA-switcheroo audio client\n");
2787 chip->use_vga_switcheroo = 1;
2788 pci_dev_put(p);
2789 }
2790 }
2791
2792 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2793 .set_gpu_state = azx_vs_set_state,
2794 .can_switch = azx_vs_can_switch,
2795 };
2796
2797 static int register_vga_switcheroo(struct azx *chip)
2798 {
2799 int err;
2800
2801 if (!chip->use_vga_switcheroo)
2802 return 0;
2803 /* FIXME: currently only handling DIS controller
2804 * is there any machine with two switchable HDMI audio controllers?
2805 */
2806 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2807 VGA_SWITCHEROO_DIS,
2808 chip->bus != NULL);
2809 if (err < 0)
2810 return err;
2811 chip->vga_switcheroo_registered = 1;
2812
2813 /* register as an optimus hdmi audio power domain */
2814 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
2815 &chip->hdmi_pm_domain);
2816 return 0;
2817 }
2818 #else
2819 #define init_vga_switcheroo(chip) /* NOP */
2820 #define register_vga_switcheroo(chip) 0
2821 #define check_hdmi_disabled(pci) false
2822 #endif /* SUPPORT_VGA_SWITCHER */
2823
2824 /*
2825 * destructor
2826 */
2827 static int azx_free(struct azx *chip)
2828 {
2829 struct pci_dev *pci = chip->pci;
2830 int i;
2831
2832 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
2833 && chip->running)
2834 pm_runtime_get_noresume(&pci->dev);
2835
2836 azx_del_card_list(chip);
2837
2838 azx_notifier_unregister(chip);
2839
2840 chip->init_failed = 1; /* to be sure */
2841 complete_all(&chip->probe_wait);
2842
2843 if (use_vga_switcheroo(chip)) {
2844 if (chip->disabled && chip->bus)
2845 snd_hda_unlock_devices(chip->bus);
2846 if (chip->vga_switcheroo_registered)
2847 vga_switcheroo_unregister_client(chip->pci);
2848 }
2849
2850 if (chip->initialized) {
2851 azx_clear_irq_pending(chip);
2852 for (i = 0; i < chip->num_streams; i++)
2853 azx_stream_stop(chip, &chip->azx_dev[i]);
2854 azx_stop_chip(chip);
2855 }
2856
2857 if (chip->irq >= 0)
2858 free_irq(chip->irq, (void*)chip);
2859 if (chip->msi)
2860 pci_disable_msi(chip->pci);
2861 if (chip->remap_addr)
2862 iounmap(chip->remap_addr);
2863
2864 if (chip->azx_dev) {
2865 for (i = 0; i < chip->num_streams; i++)
2866 if (chip->azx_dev[i].bdl.area)
2867 chip->ops->dma_free_pages(
2868 chip, &chip->azx_dev[i].bdl);
2869 }
2870 if (chip->rb.area)
2871 chip->ops->dma_free_pages(chip, &chip->rb);
2872 if (chip->posbuf.area)
2873 chip->ops->dma_free_pages(chip, &chip->posbuf);
2874 if (chip->region_requested)
2875 pci_release_regions(chip->pci);
2876 pci_disable_device(chip->pci);
2877 kfree(chip->azx_dev);
2878 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2879 if (chip->fw)
2880 release_firmware(chip->fw);
2881 #endif
2882 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2883 hda_display_power(false);
2884 hda_i915_exit();
2885 }
2886 kfree(chip);
2887
2888 return 0;
2889 }
2890
2891 static int azx_dev_free(struct snd_device *device)
2892 {
2893 return azx_free(device->device_data);
2894 }
2895
2896 #ifdef SUPPORT_VGA_SWITCHEROO
2897 /*
2898 * Check of disabled HDMI controller by vga-switcheroo
2899 */
2900 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
2901 {
2902 struct pci_dev *p;
2903
2904 /* check only discrete GPU */
2905 switch (pci->vendor) {
2906 case PCI_VENDOR_ID_ATI:
2907 case PCI_VENDOR_ID_AMD:
2908 case PCI_VENDOR_ID_NVIDIA:
2909 if (pci->devfn == 1) {
2910 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2911 pci->bus->number, 0);
2912 if (p) {
2913 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2914 return p;
2915 pci_dev_put(p);
2916 }
2917 }
2918 break;
2919 }
2920 return NULL;
2921 }
2922
2923 static bool check_hdmi_disabled(struct pci_dev *pci)
2924 {
2925 bool vga_inactive = false;
2926 struct pci_dev *p = get_bound_vga(pci);
2927
2928 if (p) {
2929 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2930 vga_inactive = true;
2931 pci_dev_put(p);
2932 }
2933 return vga_inactive;
2934 }
2935 #endif /* SUPPORT_VGA_SWITCHEROO */
2936
2937 /*
2938 * white/black-listing for position_fix
2939 */
2940 static struct snd_pci_quirk position_fix_list[] = {
2941 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2942 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2943 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2944 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2945 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2946 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2947 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2948 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2949 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2950 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2951 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2952 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2953 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2954 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2955 {}
2956 };
2957
2958 static int check_position_fix(struct azx *chip, int fix)
2959 {
2960 const struct snd_pci_quirk *q;
2961
2962 switch (fix) {
2963 case POS_FIX_AUTO:
2964 case POS_FIX_LPIB:
2965 case POS_FIX_POSBUF:
2966 case POS_FIX_VIACOMBO:
2967 case POS_FIX_COMBO:
2968 return fix;
2969 }
2970
2971 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2972 if (q) {
2973 dev_info(chip->card->dev,
2974 "position_fix set to %d for device %04x:%04x\n",
2975 q->value, q->subvendor, q->subdevice);
2976 return q->value;
2977 }
2978
2979 /* Check VIA/ATI HD Audio Controller exist */
2980 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2981 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
2982 return POS_FIX_VIACOMBO;
2983 }
2984 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2985 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
2986 return POS_FIX_LPIB;
2987 }
2988 return POS_FIX_AUTO;
2989 }
2990
2991 /*
2992 * black-lists for probe_mask
2993 */
2994 static struct snd_pci_quirk probe_mask_list[] = {
2995 /* Thinkpad often breaks the controller communication when accessing
2996 * to the non-working (or non-existing) modem codec slot.
2997 */
2998 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2999 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3000 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3001 /* broken BIOS */
3002 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3003 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3004 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3005 /* forced codec slots */
3006 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3007 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3008 /* WinFast VP200 H (Teradici) user reported broken communication */
3009 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3010 {}
3011 };
3012
3013 #define AZX_FORCE_CODEC_MASK 0x100
3014
3015 static void check_probe_mask(struct azx *chip, int dev)
3016 {
3017 const struct snd_pci_quirk *q;
3018
3019 chip->codec_probe_mask = probe_mask[dev];
3020 if (chip->codec_probe_mask == -1) {
3021 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3022 if (q) {
3023 dev_info(chip->card->dev,
3024 "probe_mask set to 0x%x for device %04x:%04x\n",
3025 q->value, q->subvendor, q->subdevice);
3026 chip->codec_probe_mask = q->value;
3027 }
3028 }
3029
3030 /* check forced option */
3031 if (chip->codec_probe_mask != -1 &&
3032 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3033 chip->codec_mask = chip->codec_probe_mask & 0xff;
3034 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
3035 chip->codec_mask);
3036 }
3037 }
3038
3039 /*
3040 * white/black-list for enable_msi
3041 */
3042 static struct snd_pci_quirk msi_black_list[] = {
3043 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
3044 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
3045 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
3046 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
3047 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3048 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3049 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3050 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
3051 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3052 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3053 {}
3054 };
3055
3056 static void check_msi(struct azx *chip)
3057 {
3058 const struct snd_pci_quirk *q;
3059
3060 if (enable_msi >= 0) {
3061 chip->msi = !!enable_msi;
3062 return;
3063 }
3064 chip->msi = 1; /* enable MSI as default */
3065 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3066 if (q) {
3067 dev_info(chip->card->dev,
3068 "msi for device %04x:%04x set to %d\n",
3069 q->subvendor, q->subdevice, q->value);
3070 chip->msi = q->value;
3071 return;
3072 }
3073
3074 /* NVidia chipsets seem to cause troubles with MSI */
3075 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3076 dev_info(chip->card->dev, "Disabling MSI\n");
3077 chip->msi = 0;
3078 }
3079 }
3080
3081 /* check the snoop mode availability */
3082 static void azx_check_snoop_available(struct azx *chip)
3083 {
3084 bool snoop = chip->snoop;
3085
3086 switch (chip->driver_type) {
3087 case AZX_DRIVER_VIA:
3088 /* force to non-snoop mode for a new VIA controller
3089 * when BIOS is set
3090 */
3091 if (snoop) {
3092 u8 val;
3093 pci_read_config_byte(chip->pci, 0x42, &val);
3094 if (!(val & 0x80) && chip->pci->revision == 0x30)
3095 snoop = false;
3096 }
3097 break;
3098 case AZX_DRIVER_ATIHDMI_NS:
3099 /* new ATI HDMI requires non-snoop */
3100 snoop = false;
3101 break;
3102 case AZX_DRIVER_CTHDA:
3103 snoop = false;
3104 break;
3105 }
3106
3107 if (snoop != chip->snoop) {
3108 dev_info(chip->card->dev, "Force to %s mode\n",
3109 snoop ? "snoop" : "non-snoop");
3110 chip->snoop = snoop;
3111 }
3112 }
3113
3114 static void azx_probe_work(struct work_struct *work)
3115 {
3116 azx_probe_continue(container_of(work, struct azx, probe_work));
3117 }
3118
3119 /*
3120 * constructor
3121 */
3122 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3123 int dev, unsigned int driver_caps,
3124 const struct hda_controller_ops *hda_ops,
3125 struct azx **rchip)
3126 {
3127 static struct snd_device_ops ops = {
3128 .dev_free = azx_dev_free,
3129 };
3130 struct azx *chip;
3131 int err;
3132
3133 *rchip = NULL;
3134
3135 err = pci_enable_device(pci);
3136 if (err < 0)
3137 return err;
3138
3139 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3140 if (!chip) {
3141 dev_err(card->dev, "Cannot allocate chip\n");
3142 pci_disable_device(pci);
3143 return -ENOMEM;
3144 }
3145
3146 spin_lock_init(&chip->reg_lock);
3147 mutex_init(&chip->open_mutex);
3148 chip->card = card;
3149 chip->pci = pci;
3150 chip->ops = hda_ops;
3151 chip->irq = -1;
3152 chip->driver_caps = driver_caps;
3153 chip->driver_type = driver_caps & 0xff;
3154 check_msi(chip);
3155 chip->dev_index = dev;
3156 chip->jackpoll_ms = jackpoll_ms;
3157 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3158 INIT_LIST_HEAD(&chip->pcm_list);
3159 INIT_LIST_HEAD(&chip->list);
3160 init_vga_switcheroo(chip);
3161 init_completion(&chip->probe_wait);
3162
3163 chip->position_fix[0] = chip->position_fix[1] =
3164 check_position_fix(chip, position_fix[dev]);
3165 /* combo mode uses LPIB for playback */
3166 if (chip->position_fix[0] == POS_FIX_COMBO) {
3167 chip->position_fix[0] = POS_FIX_LPIB;
3168 chip->position_fix[1] = POS_FIX_AUTO;
3169 }
3170
3171 check_probe_mask(chip, dev);
3172
3173 chip->single_cmd = single_cmd;
3174 chip->snoop = hda_snoop;
3175 azx_check_snoop_available(chip);
3176
3177 if (bdl_pos_adj[dev] < 0) {
3178 switch (chip->driver_type) {
3179 case AZX_DRIVER_ICH:
3180 case AZX_DRIVER_PCH:
3181 bdl_pos_adj[dev] = 1;
3182 break;
3183 default:
3184 bdl_pos_adj[dev] = 32;
3185 break;
3186 }
3187 }
3188 chip->bdl_pos_adj = bdl_pos_adj;
3189
3190 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3191 if (err < 0) {
3192 dev_err(card->dev, "Error creating device [card]!\n");
3193 azx_free(chip);
3194 return err;
3195 }
3196
3197 /* continue probing in work context as may trigger request module */
3198 INIT_WORK(&chip->probe_work, azx_probe_work);
3199
3200 *rchip = chip;
3201
3202 return 0;
3203 }
3204
3205 static int azx_first_init(struct azx *chip)
3206 {
3207 int dev = chip->dev_index;
3208 struct pci_dev *pci = chip->pci;
3209 struct snd_card *card = chip->card;
3210 int i, err;
3211 unsigned short gcap;
3212
3213 #if BITS_PER_LONG != 64
3214 /* Fix up base address on ULI M5461 */
3215 if (chip->driver_type == AZX_DRIVER_ULI) {
3216 u16 tmp3;
3217 pci_read_config_word(pci, 0x40, &tmp3);
3218 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3219 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3220 }
3221 #endif
3222
3223 err = pci_request_regions(pci, "ICH HD audio");
3224 if (err < 0)
3225 return err;
3226 chip->region_requested = 1;
3227
3228 chip->addr = pci_resource_start(pci, 0);
3229 chip->remap_addr = pci_ioremap_bar(pci, 0);
3230 if (chip->remap_addr == NULL) {
3231 dev_err(card->dev, "ioremap error\n");
3232 return -ENXIO;
3233 }
3234
3235 if (chip->msi)
3236 if (pci_enable_msi(pci) < 0)
3237 chip->msi = 0;
3238
3239 if (azx_acquire_irq(chip, 0) < 0)
3240 return -EBUSY;
3241
3242 pci_set_master(pci);
3243 synchronize_irq(chip->irq);
3244
3245 gcap = azx_readw(chip, GCAP);
3246 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
3247
3248 /* disable SB600 64bit support for safety */
3249 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3250 struct pci_dev *p_smbus;
3251 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3252 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3253 NULL);
3254 if (p_smbus) {
3255 if (p_smbus->revision < 0x30)
3256 gcap &= ~ICH6_GCAP_64OK;
3257 pci_dev_put(p_smbus);
3258 }
3259 }
3260
3261 /* disable 64bit DMA address on some devices */
3262 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3263 dev_dbg(card->dev, "Disabling 64bit DMA\n");
3264 gcap &= ~ICH6_GCAP_64OK;
3265 }
3266
3267 /* disable buffer size rounding to 128-byte multiples if supported */
3268 if (align_buffer_size >= 0)
3269 chip->align_buffer_size = !!align_buffer_size;
3270 else {
3271 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3272 chip->align_buffer_size = 0;
3273 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3274 chip->align_buffer_size = 1;
3275 else
3276 chip->align_buffer_size = 1;
3277 }
3278
3279 /* allow 64bit DMA address if supported by H/W */
3280 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3281 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3282 else {
3283 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3284 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3285 }
3286
3287 /* read number of streams from GCAP register instead of using
3288 * hardcoded value
3289 */
3290 chip->capture_streams = (gcap >> 8) & 0x0f;
3291 chip->playback_streams = (gcap >> 12) & 0x0f;
3292 if (!chip->playback_streams && !chip->capture_streams) {
3293 /* gcap didn't give any info, switching to old method */
3294
3295 switch (chip->driver_type) {
3296 case AZX_DRIVER_ULI:
3297 chip->playback_streams = ULI_NUM_PLAYBACK;
3298 chip->capture_streams = ULI_NUM_CAPTURE;
3299 break;
3300 case AZX_DRIVER_ATIHDMI:
3301 case AZX_DRIVER_ATIHDMI_NS:
3302 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3303 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3304 break;
3305 case AZX_DRIVER_GENERIC:
3306 default:
3307 chip->playback_streams = ICH6_NUM_PLAYBACK;
3308 chip->capture_streams = ICH6_NUM_CAPTURE;
3309 break;
3310 }
3311 }
3312 chip->capture_index_offset = 0;
3313 chip->playback_index_offset = chip->capture_streams;
3314 chip->num_streams = chip->playback_streams + chip->capture_streams;
3315 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3316 GFP_KERNEL);
3317 if (!chip->azx_dev) {
3318 dev_err(card->dev, "cannot malloc azx_dev\n");
3319 return -ENOMEM;
3320 }
3321
3322 for (i = 0; i < chip->num_streams; i++) {
3323 dsp_lock_init(&chip->azx_dev[i]);
3324 /* allocate memory for the BDL for each stream */
3325 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
3326 BDL_SIZE,
3327 &chip->azx_dev[i].bdl);
3328 if (err < 0) {
3329 dev_err(card->dev, "cannot allocate BDL\n");
3330 return -ENOMEM;
3331 }
3332 }
3333 /* allocate memory for the position buffer */
3334 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
3335 chip->num_streams * 8, &chip->posbuf);
3336 if (err < 0) {
3337 dev_err(card->dev, "cannot allocate posbuf\n");
3338 return -ENOMEM;
3339 }
3340 /* allocate CORB/RIRB */
3341 err = azx_alloc_cmd_io(chip);
3342 if (err < 0)
3343 return err;
3344
3345 /* initialize streams */
3346 azx_init_stream(chip);
3347
3348 /* initialize chip */
3349 azx_init_pci(chip);
3350 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3351
3352 /* codec detection */
3353 if (!chip->codec_mask) {
3354 dev_err(card->dev, "no codecs found!\n");
3355 return -ENODEV;
3356 }
3357
3358 strcpy(card->driver, "HDA-Intel");
3359 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3360 sizeof(card->shortname));
3361 snprintf(card->longname, sizeof(card->longname),
3362 "%s at 0x%lx irq %i",
3363 card->shortname, chip->addr, chip->irq);
3364
3365 return 0;
3366 }
3367
3368 static void power_down_all_codecs(struct azx *chip)
3369 {
3370 #ifdef CONFIG_PM
3371 /* The codecs were powered up in snd_hda_codec_new().
3372 * Now all initialization done, so turn them down if possible
3373 */
3374 struct hda_codec *codec;
3375 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3376 snd_hda_power_down(codec);
3377 }
3378 #endif
3379 }
3380
3381 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3382 /* callback from request_firmware_nowait() */
3383 static void azx_firmware_cb(const struct firmware *fw, void *context)
3384 {
3385 struct snd_card *card = context;
3386 struct azx *chip = card->private_data;
3387 struct pci_dev *pci = chip->pci;
3388
3389 if (!fw) {
3390 dev_err(card->dev, "Cannot load firmware, aborting\n");
3391 goto error;
3392 }
3393
3394 chip->fw = fw;
3395 if (!chip->disabled) {
3396 /* continue probing */
3397 if (azx_probe_continue(chip))
3398 goto error;
3399 }
3400 return; /* OK */
3401
3402 error:
3403 snd_card_free(card);
3404 pci_set_drvdata(pci, NULL);
3405 }
3406 #endif
3407
3408 /*
3409 * HDA controller ops.
3410 */
3411
3412 /* PCI register access. */
3413 static void pci_azx_writel(u32 value, u32 *addr)
3414 {
3415 writel(value, addr);
3416 }
3417
3418 static u32 pci_azx_readl(u32 *addr)
3419 {
3420 return readl(addr);
3421 }
3422
3423 static void pci_azx_writew(u16 value, u16 *addr)
3424 {
3425 writew(value, addr);
3426 }
3427
3428 static u16 pci_azx_readw(u16 *addr)
3429 {
3430 return readw(addr);
3431 }
3432
3433 static void pci_azx_writeb(u8 value, u8 *addr)
3434 {
3435 writeb(value, addr);
3436 }
3437
3438 static u8 pci_azx_readb(u8 *addr)
3439 {
3440 return readb(addr);
3441 }
3442
3443 static int disable_msi_reset_irq(struct azx *chip)
3444 {
3445 int err;
3446
3447 free_irq(chip->irq, chip);
3448 chip->irq = -1;
3449 pci_disable_msi(chip->pci);
3450 chip->msi = 0;
3451 err = azx_acquire_irq(chip, 1);
3452 if (err < 0)
3453 return err;
3454
3455 return 0;
3456 }
3457
3458 /* DMA page allocation helpers. */
3459 static int dma_alloc_pages(struct azx *chip,
3460 int type,
3461 size_t size,
3462 struct snd_dma_buffer *buf)
3463 {
3464 int err;
3465
3466 err = snd_dma_alloc_pages(type,
3467 chip->card->dev,
3468 size, buf);
3469 if (err < 0)
3470 return err;
3471 mark_pages_wc(chip, buf, true);
3472 return 0;
3473 }
3474
3475 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
3476 {
3477 mark_pages_wc(chip, buf, false);
3478 snd_dma_free_pages(buf);
3479 }
3480
3481 static int substream_alloc_pages(struct azx *chip,
3482 struct snd_pcm_substream *substream,
3483 size_t size)
3484 {
3485 struct azx_dev *azx_dev = get_azx_dev(substream);
3486 int ret;
3487
3488 mark_runtime_wc(chip, azx_dev, substream, false);
3489 azx_dev->bufsize = 0;
3490 azx_dev->period_bytes = 0;
3491 azx_dev->format_val = 0;
3492 ret = snd_pcm_lib_malloc_pages(substream, size);
3493 if (ret < 0)
3494 return ret;
3495 mark_runtime_wc(chip, azx_dev, substream, true);
3496 return 0;
3497 }
3498
3499 static int substream_free_pages(struct azx *chip,
3500 struct snd_pcm_substream *substream)
3501 {
3502 struct azx_dev *azx_dev = get_azx_dev(substream);
3503 mark_runtime_wc(chip, azx_dev, substream, false);
3504 return snd_pcm_lib_free_pages(substream);
3505 }
3506
3507 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
3508 struct vm_area_struct *area)
3509 {
3510 #ifdef CONFIG_X86
3511 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
3512 struct azx *chip = apcm->chip;
3513 if (!azx_snoop(chip))
3514 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
3515 #endif
3516 }
3517
3518 static const struct hda_controller_ops pci_hda_ops = {
3519 .writel = pci_azx_writel,
3520 .readl = pci_azx_readl,
3521 .writew = pci_azx_writew,
3522 .readw = pci_azx_readw,
3523 .writeb = pci_azx_writeb,
3524 .readb = pci_azx_readb,
3525 .disable_msi_reset_irq = disable_msi_reset_irq,
3526 .dma_alloc_pages = dma_alloc_pages,
3527 .dma_free_pages = dma_free_pages,
3528 .substream_alloc_pages = substream_alloc_pages,
3529 .substream_free_pages = substream_free_pages,
3530 .pcm_mmap_prepare = pcm_mmap_prepare,
3531 };
3532
3533 static int azx_probe(struct pci_dev *pci,
3534 const struct pci_device_id *pci_id)
3535 {
3536 static int dev;
3537 struct snd_card *card;
3538 struct azx *chip;
3539 bool schedule_probe;
3540 int err;
3541
3542 if (dev >= SNDRV_CARDS)
3543 return -ENODEV;
3544 if (!enable[dev]) {
3545 dev++;
3546 return -ENOENT;
3547 }
3548
3549 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3550 0, &card);
3551 if (err < 0) {
3552 dev_err(&pci->dev, "Error creating card!\n");
3553 return err;
3554 }
3555
3556 err = azx_create(card, pci, dev, pci_id->driver_data,
3557 &pci_hda_ops, &chip);
3558 if (err < 0)
3559 goto out_free;
3560 card->private_data = chip;
3561
3562 pci_set_drvdata(pci, card);
3563
3564 err = register_vga_switcheroo(chip);
3565 if (err < 0) {
3566 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
3567 goto out_free;
3568 }
3569
3570 if (check_hdmi_disabled(pci)) {
3571 dev_info(card->dev, "VGA controller is disabled\n");
3572 dev_info(card->dev, "Delaying initialization\n");
3573 chip->disabled = true;
3574 }
3575
3576 schedule_probe = !chip->disabled;
3577
3578 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3579 if (patch[dev] && *patch[dev]) {
3580 dev_info(card->dev, "Applying patch firmware '%s'\n",
3581 patch[dev]);
3582 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3583 &pci->dev, GFP_KERNEL, card,
3584 azx_firmware_cb);
3585 if (err < 0)
3586 goto out_free;
3587 schedule_probe = false; /* continued in azx_firmware_cb() */
3588 }
3589 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3590
3591 #ifndef CONFIG_SND_HDA_I915
3592 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3593 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
3594 #endif
3595
3596 if (schedule_probe)
3597 schedule_work(&chip->probe_work);
3598
3599 dev++;
3600 if (chip->disabled)
3601 complete_all(&chip->probe_wait);
3602 return 0;
3603
3604 out_free:
3605 snd_card_free(card);
3606 return err;
3607 }
3608
3609 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
3610 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
3611 [AZX_DRIVER_NVIDIA] = 8,
3612 [AZX_DRIVER_TERA] = 1,
3613 };
3614
3615 static int azx_probe_continue(struct azx *chip)
3616 {
3617 struct pci_dev *pci = chip->pci;
3618 int dev = chip->dev_index;
3619 int err;
3620
3621 /* Request power well for Haswell HDA controller and codec */
3622 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3623 #ifdef CONFIG_SND_HDA_I915
3624 err = hda_i915_init();
3625 if (err < 0) {
3626 dev_err(chip->card->dev,
3627 "Error request power-well from i915\n");
3628 goto out_free;
3629 }
3630 #endif
3631 hda_display_power(true);
3632 }
3633
3634 err = azx_first_init(chip);
3635 if (err < 0)
3636 goto out_free;
3637
3638 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3639 chip->beep_mode = beep_mode[dev];
3640 #endif
3641
3642 /* create codec instances */
3643 err = azx_codec_create(chip, model[dev],
3644 azx_max_codecs[chip->driver_type],
3645 power_save_addr);
3646
3647 if (err < 0)
3648 goto out_free;
3649 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3650 if (chip->fw) {
3651 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3652 chip->fw->data);
3653 if (err < 0)
3654 goto out_free;
3655 #ifndef CONFIG_PM
3656 release_firmware(chip->fw); /* no longer needed */
3657 chip->fw = NULL;
3658 #endif
3659 }
3660 #endif
3661 if ((probe_only[dev] & 1) == 0) {
3662 err = azx_codec_configure(chip);
3663 if (err < 0)
3664 goto out_free;
3665 }
3666
3667 /* create PCM streams */
3668 err = snd_hda_build_pcms(chip->bus);
3669 if (err < 0)
3670 goto out_free;
3671
3672 /* create mixer controls */
3673 err = azx_mixer_create(chip);
3674 if (err < 0)
3675 goto out_free;
3676
3677 err = snd_card_register(chip->card);
3678 if (err < 0)
3679 goto out_free;
3680
3681 chip->running = 1;
3682 power_down_all_codecs(chip);
3683 azx_notifier_register(chip);
3684 azx_add_card_list(chip);
3685 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
3686 pm_runtime_put_noidle(&pci->dev);
3687
3688 out_free:
3689 if (err < 0)
3690 chip->init_failed = 1;
3691 complete_all(&chip->probe_wait);
3692 return err;
3693 }
3694
3695 static void azx_remove(struct pci_dev *pci)
3696 {
3697 struct snd_card *card = pci_get_drvdata(pci);
3698
3699 if (card)
3700 snd_card_free(card);
3701 }
3702
3703 /* PCI IDs */
3704 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3705 /* CPT */
3706 { PCI_DEVICE(0x8086, 0x1c20),
3707 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3708 /* PBG */
3709 { PCI_DEVICE(0x8086, 0x1d20),
3710 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3711 /* Panther Point */
3712 { PCI_DEVICE(0x8086, 0x1e20),
3713 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3714 /* Lynx Point */
3715 { PCI_DEVICE(0x8086, 0x8c20),
3716 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3717 /* Wellsburg */
3718 { PCI_DEVICE(0x8086, 0x8d20),
3719 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3720 { PCI_DEVICE(0x8086, 0x8d21),
3721 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3722 /* Lynx Point-LP */
3723 { PCI_DEVICE(0x8086, 0x9c20),
3724 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3725 /* Lynx Point-LP */
3726 { PCI_DEVICE(0x8086, 0x9c21),
3727 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3728 /* Wildcat Point-LP */
3729 { PCI_DEVICE(0x8086, 0x9ca0),
3730 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3731 /* Haswell */
3732 { PCI_DEVICE(0x8086, 0x0a0c),
3733 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3734 { PCI_DEVICE(0x8086, 0x0c0c),
3735 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3736 { PCI_DEVICE(0x8086, 0x0d0c),
3737 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3738 /* Broadwell */
3739 { PCI_DEVICE(0x8086, 0x160c),
3740 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3741 /* 5 Series/3400 */
3742 { PCI_DEVICE(0x8086, 0x3b56),
3743 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3744 /* Poulsbo */
3745 { PCI_DEVICE(0x8086, 0x811b),
3746 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3747 /* Oaktrail */
3748 { PCI_DEVICE(0x8086, 0x080a),
3749 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3750 /* BayTrail */
3751 { PCI_DEVICE(0x8086, 0x0f04),
3752 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3753 /* ICH */
3754 { PCI_DEVICE(0x8086, 0x2668),
3755 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3756 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3757 { PCI_DEVICE(0x8086, 0x27d8),
3758 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3759 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3760 { PCI_DEVICE(0x8086, 0x269a),
3761 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3762 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3763 { PCI_DEVICE(0x8086, 0x284b),
3764 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3765 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3766 { PCI_DEVICE(0x8086, 0x293e),
3767 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3768 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3769 { PCI_DEVICE(0x8086, 0x293f),
3770 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3771 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3772 { PCI_DEVICE(0x8086, 0x3a3e),
3773 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3774 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3775 { PCI_DEVICE(0x8086, 0x3a6e),
3776 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3777 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3778 /* Generic Intel */
3779 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3780 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3781 .class_mask = 0xffffff,
3782 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3783 /* ATI SB 450/600/700/800/900 */
3784 { PCI_DEVICE(0x1002, 0x437b),
3785 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3786 { PCI_DEVICE(0x1002, 0x4383),
3787 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3788 /* AMD Hudson */
3789 { PCI_DEVICE(0x1022, 0x780d),
3790 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3791 /* ATI HDMI */
3792 { PCI_DEVICE(0x1002, 0x793b),
3793 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3794 { PCI_DEVICE(0x1002, 0x7919),
3795 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3796 { PCI_DEVICE(0x1002, 0x960f),
3797 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3798 { PCI_DEVICE(0x1002, 0x970f),
3799 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3800 { PCI_DEVICE(0x1002, 0xaa00),
3801 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3802 { PCI_DEVICE(0x1002, 0xaa08),
3803 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3804 { PCI_DEVICE(0x1002, 0xaa10),
3805 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3806 { PCI_DEVICE(0x1002, 0xaa18),
3807 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3808 { PCI_DEVICE(0x1002, 0xaa20),
3809 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3810 { PCI_DEVICE(0x1002, 0xaa28),
3811 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3812 { PCI_DEVICE(0x1002, 0xaa30),
3813 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3814 { PCI_DEVICE(0x1002, 0xaa38),
3815 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3816 { PCI_DEVICE(0x1002, 0xaa40),
3817 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3818 { PCI_DEVICE(0x1002, 0xaa48),
3819 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3820 { PCI_DEVICE(0x1002, 0xaa50),
3821 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3822 { PCI_DEVICE(0x1002, 0xaa58),
3823 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3824 { PCI_DEVICE(0x1002, 0xaa60),
3825 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3826 { PCI_DEVICE(0x1002, 0xaa68),
3827 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3828 { PCI_DEVICE(0x1002, 0xaa80),
3829 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3830 { PCI_DEVICE(0x1002, 0xaa88),
3831 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3832 { PCI_DEVICE(0x1002, 0xaa90),
3833 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3834 { PCI_DEVICE(0x1002, 0xaa98),
3835 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3836 { PCI_DEVICE(0x1002, 0x9902),
3837 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3838 { PCI_DEVICE(0x1002, 0xaaa0),
3839 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3840 { PCI_DEVICE(0x1002, 0xaaa8),
3841 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3842 { PCI_DEVICE(0x1002, 0xaab0),
3843 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3844 /* VIA VT8251/VT8237A */
3845 { PCI_DEVICE(0x1106, 0x3288),
3846 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3847 /* VIA GFX VT7122/VX900 */
3848 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3849 /* VIA GFX VT6122/VX11 */
3850 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3851 /* SIS966 */
3852 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3853 /* ULI M5461 */
3854 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3855 /* NVIDIA MCP */
3856 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3857 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3858 .class_mask = 0xffffff,
3859 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3860 /* Teradici */
3861 { PCI_DEVICE(0x6549, 0x1200),
3862 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3863 { PCI_DEVICE(0x6549, 0x2200),
3864 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3865 /* Creative X-Fi (CA0110-IBG) */
3866 /* CTHDA chips */
3867 { PCI_DEVICE(0x1102, 0x0010),
3868 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3869 { PCI_DEVICE(0x1102, 0x0012),
3870 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3871 #if !IS_ENABLED(CONFIG_SND_CTXFI)
3872 /* the following entry conflicts with snd-ctxfi driver,
3873 * as ctxfi driver mutates from HD-audio to native mode with
3874 * a special command sequence.
3875 */
3876 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3877 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3878 .class_mask = 0xffffff,
3879 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3880 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3881 #else
3882 /* this entry seems still valid -- i.e. without emu20kx chip */
3883 { PCI_DEVICE(0x1102, 0x0009),
3884 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3885 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3886 #endif
3887 /* Vortex86MX */
3888 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3889 /* VMware HDAudio */
3890 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3891 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3892 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3893 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3894 .class_mask = 0xffffff,
3895 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3896 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3897 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3898 .class_mask = 0xffffff,
3899 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3900 { 0, }
3901 };
3902 MODULE_DEVICE_TABLE(pci, azx_ids);
3903
3904 /* pci_driver definition */
3905 static struct pci_driver azx_driver = {
3906 .name = KBUILD_MODNAME,
3907 .id_table = azx_ids,
3908 .probe = azx_probe,
3909 .remove = azx_remove,
3910 .driver = {
3911 .pm = AZX_PM_OPS,
3912 },
3913 };
3914
3915 module_pci_driver(azx_driver);
Linux with added FPC-III support