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V4L/DVB (10353): gspca - some subdrivers: Don't get the control values from the webcam.
[linux/fpc-iii.git] / drivers / net / tg3.c
blobf7efcecc4108f44e8fcdb26a83bb653a17660a36
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0 0
59 #define BAR_2 2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.98"
72 #define DRV_MODULE_RELDATE "February 25, 2009"
73
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90 #define TG3_TX_TIMEOUT (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
133
134 #define TG3_RAW_IP_ALIGN 2
135
136 /* number of ETHTOOL_GSTATS u64's */
137 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
139 #define TG3_NUM_TEST 6
140
141 #define FIRMWARE_TG3 "tigon/tg3.bin"
142 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
144
145 static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_MODULE_VERSION);
152 MODULE_FIRMWARE(FIRMWARE_TG3);
153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
156
157 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158 module_param(tg3_debug, int, 0);
159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161 static struct pci_device_id tg3_pci_tbl[] = {
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234 {}
235 };
236
237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
239 static const struct {
240 const char string[ETH_GSTRING_LEN];
241 } ethtool_stats_keys[TG3_NUM_STATS] = {
242 { "rx_octets" },
243 { "rx_fragments" },
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
247 { "rx_fcs_errors" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
254 { "rx_jabbers" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
268
269 { "tx_octets" },
270 { "tx_collisions" },
271
272 { "tx_xon_sent" },
273 { "tx_xoff_sent" },
274 { "tx_flow_control" },
275 { "tx_mac_errors" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
278 { "tx_deferred" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
299 { "tx_discards" },
300 { "tx_errors" },
301
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
304 { "rxbds_empty" },
305 { "rx_discards" },
306 { "rx_errors" },
307 { "rx_threshold_hit" },
308
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
312
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
315 { "nic_irqs" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
318 };
319
320 static const struct {
321 const char string[ETH_GSTRING_LEN];
322 } ethtool_test_keys[TG3_NUM_TEST] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
329 };
330
331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332 {
333 writel(val, tp->regs + off);
334 }
335
336 static u32 tg3_read32(struct tg3 *tp, u32 off)
337 {
338 return (readl(tp->regs + off));
339 }
340
341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342 {
343 writel(val, tp->aperegs + off);
344 }
345
346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347 {
348 return (readl(tp->aperegs + off));
349 }
350
351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352 {
353 unsigned long flags;
354
355 spin_lock_irqsave(&tp->indirect_lock, flags);
356 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
358 spin_unlock_irqrestore(&tp->indirect_lock, flags);
359 }
360
361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362 {
363 writel(val, tp->regs + off);
364 readl(tp->regs + off);
365 }
366
367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
368 {
369 unsigned long flags;
370 u32 val;
371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
376 return val;
377 }
378
379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380 {
381 unsigned long flags;
382
383 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385 TG3_64BIT_REG_LOW, val);
386 return;
387 }
388 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390 TG3_64BIT_REG_LOW, val);
391 return;
392 }
393
394 spin_lock_irqsave(&tp->indirect_lock, flags);
395 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397 spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
401 */
402 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403 (val == 0x1)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406 }
407 }
408
409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410 {
411 unsigned long flags;
412 u32 val;
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418 return val;
419 }
420
421 /* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425 */
426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
427 {
428 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 /* Non-posted methods */
431 tp->write32(tp, off, val);
432 else {
433 /* Posted method */
434 tg3_write32(tp, off, val);
435 if (usec_wait)
436 udelay(usec_wait);
437 tp->read32(tp, off);
438 }
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
441 */
442 if (usec_wait)
443 udelay(usec_wait);
444 }
445
446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447 {
448 tp->write32_mbox(tp, off, val);
449 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451 tp->read32_mbox(tp, off);
452 }
453
454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
455 {
456 void __iomem *mbox = tp->regs + off;
457 writel(val, mbox);
458 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459 writel(val, mbox);
460 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461 readl(mbox);
462 }
463
464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465 {
466 return (readl(tp->regs + off + GRCMBOX_BASE));
467 }
468
469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470 {
471 writel(val, tp->regs + off + GRCMBOX_BASE);
472 }
473
474 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
475 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
476 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
478 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
479
480 #define tw32(reg,val) tp->write32(tp, reg, val)
481 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
483 #define tr32(reg) tp->read32(tp, reg)
484
485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486 {
487 unsigned long flags;
488
489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491 return;
492
493 spin_lock_irqsave(&tp->indirect_lock, flags);
494 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
497
498 /* Always leave this as zero. */
499 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500 } else {
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502 tw32_f(TG3PCI_MEM_WIN_DATA, val);
503
504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 }
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
508 }
509
510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511 {
512 unsigned long flags;
513
514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516 *val = 0;
517 return;
518 }
519
520 spin_lock_irqsave(&tp->indirect_lock, flags);
521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
524
525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
535 }
536
537 static void tg3_ape_lock_init(struct tg3 *tp)
538 {
539 int i;
540
541 /* Make sure the driver hasn't any stale locks. */
542 for (i = 0; i < 8; i++)
543 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544 APE_LOCK_GRANT_DRIVER);
545 }
546
547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
548 {
549 int i, off;
550 int ret = 0;
551 u32 status;
552
553 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554 return 0;
555
556 switch (locknum) {
557 case TG3_APE_LOCK_GRC:
558 case TG3_APE_LOCK_MEM:
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 off = 4 * locknum;
565
566 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i = 0; i < 100; i++) {
570 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571 if (status == APE_LOCK_GRANT_DRIVER)
572 break;
573 udelay(10);
574 }
575
576 if (status != APE_LOCK_GRANT_DRIVER) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579 APE_LOCK_GRANT_DRIVER);
580
581 ret = -EBUSY;
582 }
583
584 return ret;
585 }
586
587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588 {
589 int off;
590
591 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592 return;
593
594 switch (locknum) {
595 case TG3_APE_LOCK_GRC:
596 case TG3_APE_LOCK_MEM:
597 break;
598 default:
599 return;
600 }
601
602 off = 4 * locknum;
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604 }
605
606 static void tg3_disable_ints(struct tg3 *tp)
607 {
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
611 }
612
613 static inline void tg3_cond_int(struct tg3 *tp)
614 {
615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616 (tp->hw_status->status & SD_STATUS_UPDATED))
617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
618 else
619 tw32(HOSTCC_MODE, tp->coalesce_mode |
620 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
621 }
622
623 static void tg3_enable_ints(struct tg3 *tp)
624 {
625 tp->irq_sync = 0;
626 wmb();
627
628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
630 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631 (tp->last_tag << 24));
632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634 (tp->last_tag << 24));
635 tg3_cond_int(tp);
636 }
637
638 static inline unsigned int tg3_has_work(struct tg3 *tp)
639 {
640 struct tg3_hw_status *sblk = tp->hw_status;
641 unsigned int work_exists = 0;
642
643 /* check for phy events */
644 if (!(tp->tg3_flags &
645 (TG3_FLAG_USE_LINKCHG_REG |
646 TG3_FLAG_POLL_SERDES))) {
647 if (sblk->status & SD_STATUS_LINK_CHG)
648 work_exists = 1;
649 }
650 /* check for RX/TX work to do */
651 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653 work_exists = 1;
654
655 return work_exists;
656 }
657
658 /* tg3_restart_ints
659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
661 * which reenables interrupts
662 */
663 static void tg3_restart_ints(struct tg3 *tp)
664 {
665 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666 tp->last_tag << 24);
667 mmiowb();
668
669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
672 */
673 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674 tg3_has_work(tp))
675 tw32(HOSTCC_MODE, tp->coalesce_mode |
676 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
677 }
678
679 static inline void tg3_netif_stop(struct tg3 *tp)
680 {
681 tp->dev->trans_start = jiffies; /* prevent tx timeout */
682 napi_disable(&tp->napi);
683 netif_tx_disable(tp->dev);
684 }
685
686 static inline void tg3_netif_start(struct tg3 *tp)
687 {
688 netif_wake_queue(tp->dev);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
692 */
693 napi_enable(&tp->napi);
694 tp->hw_status->status |= SD_STATUS_UPDATED;
695 tg3_enable_ints(tp);
696 }
697
698 static void tg3_switch_clocks(struct tg3 *tp)
699 {
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701 u32 orig_clock_ctrl;
702
703 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
705 return;
706
707 orig_clock_ctrl = clock_ctrl;
708 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709 CLOCK_CTRL_CLKRUN_OENABLE |
710 0x1f);
711 tp->pci_clock_ctrl = clock_ctrl;
712
713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
715 tw32_wait_f(TG3PCI_CLOCK_CTRL,
716 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
717 }
718 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
719 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720 clock_ctrl |
721 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722 40);
723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | (CLOCK_CTRL_ALTCLK),
725 40);
726 }
727 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
728 }
729
730 #define PHY_BUSY_LOOPS 5000
731
732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733 {
734 u32 frame_val;
735 unsigned int loops;
736 int ret;
737
738 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739 tw32_f(MAC_MI_MODE,
740 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741 udelay(80);
742 }
743
744 *val = 0x0;
745
746 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747 MI_COM_PHY_ADDR_MASK);
748 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749 MI_COM_REG_ADDR_MASK);
750 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
751
752 tw32_f(MAC_MI_COM, frame_val);
753
754 loops = PHY_BUSY_LOOPS;
755 while (loops != 0) {
756 udelay(10);
757 frame_val = tr32(MAC_MI_COM);
758
759 if ((frame_val & MI_COM_BUSY) == 0) {
760 udelay(5);
761 frame_val = tr32(MAC_MI_COM);
762 break;
763 }
764 loops -= 1;
765 }
766
767 ret = -EBUSY;
768 if (loops != 0) {
769 *val = frame_val & MI_COM_DATA_MASK;
770 ret = 0;
771 }
772
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE, tp->mi_mode);
775 udelay(80);
776 }
777
778 return ret;
779 }
780
781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782 {
783 u32 frame_val;
784 unsigned int loops;
785 int ret;
786
787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789 return 0;
790
791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 tw32_f(MAC_MI_MODE,
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 udelay(80);
795 }
796
797 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (val & MI_COM_DATA_MASK);
802 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
803
804 tw32_f(MAC_MI_COM, frame_val);
805
806 loops = PHY_BUSY_LOOPS;
807 while (loops != 0) {
808 udelay(10);
809 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
811 udelay(5);
812 frame_val = tr32(MAC_MI_COM);
813 break;
814 }
815 loops -= 1;
816 }
817
818 ret = -EBUSY;
819 if (loops != 0)
820 ret = 0;
821
822 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823 tw32_f(MAC_MI_MODE, tp->mi_mode);
824 udelay(80);
825 }
826
827 return ret;
828 }
829
830 static int tg3_bmcr_reset(struct tg3 *tp)
831 {
832 u32 phy_control;
833 int limit, err;
834
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
837 */
838 phy_control = BMCR_RESET;
839 err = tg3_writephy(tp, MII_BMCR, phy_control);
840 if (err != 0)
841 return -EBUSY;
842
843 limit = 5000;
844 while (limit--) {
845 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846 if (err != 0)
847 return -EBUSY;
848
849 if ((phy_control & BMCR_RESET) == 0) {
850 udelay(40);
851 break;
852 }
853 udelay(10);
854 }
855 if (limit < 0)
856 return -EBUSY;
857
858 return 0;
859 }
860
861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862 {
863 struct tg3 *tp = bp->priv;
864 u32 val;
865
866 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867 return -EAGAIN;
868
869 if (tg3_readphy(tp, reg, &val))
870 return -EIO;
871
872 return val;
873 }
874
875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876 {
877 struct tg3 *tp = bp->priv;
878
879 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880 return -EAGAIN;
881
882 if (tg3_writephy(tp, reg, val))
883 return -EIO;
884
885 return 0;
886 }
887
888 static int tg3_mdio_reset(struct mii_bus *bp)
889 {
890 return 0;
891 }
892
893 static void tg3_mdio_config_5785(struct tg3 *tp)
894 {
895 u32 val;
896 struct phy_device *phydev;
897
898 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900 case TG3_PHY_ID_BCM50610:
901 val = MAC_PHYCFG2_50610_LED_MODES;
902 break;
903 case TG3_PHY_ID_BCMAC131:
904 val = MAC_PHYCFG2_AC131_LED_MODES;
905 break;
906 case TG3_PHY_ID_RTL8211C:
907 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908 break;
909 case TG3_PHY_ID_RTL8201E:
910 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911 break;
912 default:
913 return;
914 }
915
916 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917 tw32(MAC_PHYCFG2, val);
918
919 val = tr32(MAC_PHYCFG1);
920 val &= ~MAC_PHYCFG1_RGMII_INT;
921 tw32(MAC_PHYCFG1, val);
922
923 return;
924 }
925
926 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928 MAC_PHYCFG2_FMODE_MASK_MASK |
929 MAC_PHYCFG2_GMODE_MASK_MASK |
930 MAC_PHYCFG2_ACT_MASK_MASK |
931 MAC_PHYCFG2_QUAL_MASK_MASK |
932 MAC_PHYCFG2_INBAND_ENABLE;
933
934 tw32(MAC_PHYCFG2, val);
935
936 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937 MAC_PHYCFG1_RGMII_SND_STAT_EN);
938 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943 }
944 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
946 val = tr32(MAC_EXT_RGMII_MODE);
947 val &= ~(MAC_RGMII_MODE_RX_INT_B |
948 MAC_RGMII_MODE_RX_QUALITY |
949 MAC_RGMII_MODE_RX_ACTIVITY |
950 MAC_RGMII_MODE_RX_ENG_DET |
951 MAC_RGMII_MODE_TX_ENABLE |
952 MAC_RGMII_MODE_TX_LOWPWR |
953 MAC_RGMII_MODE_TX_RESET);
954 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
955 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956 val |= MAC_RGMII_MODE_RX_INT_B |
957 MAC_RGMII_MODE_RX_QUALITY |
958 MAC_RGMII_MODE_RX_ACTIVITY |
959 MAC_RGMII_MODE_RX_ENG_DET;
960 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961 val |= MAC_RGMII_MODE_TX_ENABLE |
962 MAC_RGMII_MODE_TX_LOWPWR |
963 MAC_RGMII_MODE_TX_RESET;
964 }
965 tw32(MAC_EXT_RGMII_MODE, val);
966 }
967
968 static void tg3_mdio_start(struct tg3 *tp)
969 {
970 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
971 mutex_lock(&tp->mdio_bus->mdio_lock);
972 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
973 mutex_unlock(&tp->mdio_bus->mdio_lock);
974 }
975
976 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977 tw32_f(MAC_MI_MODE, tp->mi_mode);
978 udelay(80);
979
980 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982 tg3_mdio_config_5785(tp);
983 }
984
985 static void tg3_mdio_stop(struct tg3 *tp)
986 {
987 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
988 mutex_lock(&tp->mdio_bus->mdio_lock);
989 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
990 mutex_unlock(&tp->mdio_bus->mdio_lock);
991 }
992 }
993
994 static int tg3_mdio_init(struct tg3 *tp)
995 {
996 int i;
997 u32 reg;
998 struct phy_device *phydev;
999
1000 tg3_mdio_start(tp);
1001
1002 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004 return 0;
1005
1006 tp->mdio_bus = mdiobus_alloc();
1007 if (tp->mdio_bus == NULL)
1008 return -ENOMEM;
1009
1010 tp->mdio_bus->name = "tg3 mdio bus";
1011 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1012 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1013 tp->mdio_bus->priv = tp;
1014 tp->mdio_bus->parent = &tp->pdev->dev;
1015 tp->mdio_bus->read = &tg3_mdio_read;
1016 tp->mdio_bus->write = &tg3_mdio_write;
1017 tp->mdio_bus->reset = &tg3_mdio_reset;
1018 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019 tp->mdio_bus->irq = &tp->mdio_irq[0];
1020
1021 for (i = 0; i < PHY_MAX_ADDR; i++)
1022 tp->mdio_bus->irq[i] = PHY_POLL;
1023
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1028 */
1029 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030 tg3_bmcr_reset(tp);
1031
1032 i = mdiobus_register(tp->mdio_bus);
1033 if (i) {
1034 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035 tp->dev->name, i);
1036 mdiobus_free(tp->mdio_bus);
1037 return i;
1038 }
1039
1040 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1041
1042 if (!phydev || !phydev->drv) {
1043 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044 mdiobus_unregister(tp->mdio_bus);
1045 mdiobus_free(tp->mdio_bus);
1046 return -ENODEV;
1047 }
1048
1049 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1050 case TG3_PHY_ID_BCM57780:
1051 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052 break;
1053 case TG3_PHY_ID_BCM50610:
1054 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1060 /* fallthru */
1061 case TG3_PHY_ID_RTL8211C:
1062 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1063 break;
1064 case TG3_PHY_ID_RTL8201E:
1065 case TG3_PHY_ID_BCMAC131:
1066 phydev->interface = PHY_INTERFACE_MODE_MII;
1067 break;
1068 }
1069
1070 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073 tg3_mdio_config_5785(tp);
1074
1075 return 0;
1076 }
1077
1078 static void tg3_mdio_fini(struct tg3 *tp)
1079 {
1080 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1082 mdiobus_unregister(tp->mdio_bus);
1083 mdiobus_free(tp->mdio_bus);
1084 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085 }
1086 }
1087
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3 *tp)
1090 {
1091 u32 val;
1092
1093 val = tr32(GRC_RX_CPU_EVENT);
1094 val |= GRC_RX_CPU_DRIVER_EVENT;
1095 tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097 tp->last_event_jiffies = jiffies;
1098 }
1099
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3 *tp)
1104 {
1105 int i;
1106 unsigned int delay_cnt;
1107 long time_remain;
1108
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain = (long)(tp->last_event_jiffies + 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112 (long)jiffies;
1113 if (time_remain < 0)
1114 return;
1115
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt = jiffies_to_usecs(time_remain);
1118 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120 delay_cnt = (delay_cnt >> 3) + 1;
1121
1122 for (i = 0; i < delay_cnt; i++) {
1123 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124 break;
1125 udelay(8);
1126 }
1127 }
1128
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3 *tp)
1131 {
1132 u32 reg;
1133 u32 val;
1134
1135 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1137 return;
1138
1139 tg3_wait_for_event_ack(tp);
1140
1141 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_BMCR, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_BMSR, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152 val = 0;
1153 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154 val = reg << 16;
1155 if (!tg3_readphy(tp, MII_LPA, &reg))
1156 val |= (reg & 0xffff);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159 val = 0;
1160 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162 val = reg << 16;
1163 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164 val |= (reg & 0xffff);
1165 }
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169 val = reg << 16;
1170 else
1171 val = 0;
1172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
1174 tg3_generate_fw_event(tp);
1175 }
1176
1177 static void tg3_link_report(struct tg3 *tp)
1178 {
1179 if (!netif_carrier_ok(tp->dev)) {
1180 if (netif_msg_link(tp))
1181 printk(KERN_INFO PFX "%s: Link is down.\n",
1182 tp->dev->name);
1183 tg3_ump_link_report(tp);
1184 } else if (netif_msg_link(tp)) {
1185 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186 tp->dev->name,
1187 (tp->link_config.active_speed == SPEED_1000 ?
1188 1000 :
1189 (tp->link_config.active_speed == SPEED_100 ?
1190 100 : 10)),
1191 (tp->link_config.active_duplex == DUPLEX_FULL ?
1192 "full" : "half"));
1193
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1196 tp->dev->name,
1197 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1198 "on" : "off",
1199 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1200 "on" : "off");
1201 tg3_ump_link_report(tp);
1202 }
1203 }
1204
1205 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206 {
1207 u16 miireg;
1208
1209 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1210 miireg = ADVERTISE_PAUSE_CAP;
1211 else if (flow_ctrl & FLOW_CTRL_TX)
1212 miireg = ADVERTISE_PAUSE_ASYM;
1213 else if (flow_ctrl & FLOW_CTRL_RX)
1214 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215 else
1216 miireg = 0;
1217
1218 return miireg;
1219 }
1220
1221 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222 {
1223 u16 miireg;
1224
1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226 miireg = ADVERTISE_1000XPAUSE;
1227 else if (flow_ctrl & FLOW_CTRL_TX)
1228 miireg = ADVERTISE_1000XPSE_ASYM;
1229 else if (flow_ctrl & FLOW_CTRL_RX)
1230 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235 }
1236
1237 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238 {
1239 u8 cap = 0;
1240
1241 if (lcladv & ADVERTISE_1000XPAUSE) {
1242 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243 if (rmtadv & LPA_1000XPAUSE)
1244 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1245 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1246 cap = FLOW_CTRL_RX;
1247 } else {
1248 if (rmtadv & LPA_1000XPAUSE)
1249 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1250 }
1251 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1253 cap = FLOW_CTRL_TX;
1254 }
1255
1256 return cap;
1257 }
1258
1259 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1260 {
1261 u8 autoneg;
1262 u8 flowctrl = 0;
1263 u32 old_rx_mode = tp->rx_mode;
1264 u32 old_tx_mode = tp->tx_mode;
1265
1266 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1267 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1268 else
1269 autoneg = tp->link_config.autoneg;
1270
1271 if (autoneg == AUTONEG_ENABLE &&
1272 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1274 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1275 else
1276 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1277 } else
1278 flowctrl = tp->link_config.flowctrl;
1279
1280 tp->link_config.active_flowctrl = flowctrl;
1281
1282 if (flowctrl & FLOW_CTRL_RX)
1283 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284 else
1285 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
1287 if (old_rx_mode != tp->rx_mode)
1288 tw32_f(MAC_RX_MODE, tp->rx_mode);
1289
1290 if (flowctrl & FLOW_CTRL_TX)
1291 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292 else
1293 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
1295 if (old_tx_mode != tp->tx_mode)
1296 tw32_f(MAC_TX_MODE, tp->tx_mode);
1297 }
1298
1299 static void tg3_adjust_link(struct net_device *dev)
1300 {
1301 u8 oldflowctrl, linkmesg = 0;
1302 u32 mac_mode, lcl_adv, rmt_adv;
1303 struct tg3 *tp = netdev_priv(dev);
1304 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1305
1306 spin_lock(&tp->lock);
1307
1308 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309 MAC_MODE_HALF_DUPLEX);
1310
1311 oldflowctrl = tp->link_config.active_flowctrl;
1312
1313 if (phydev->link) {
1314 lcl_adv = 0;
1315 rmt_adv = 0;
1316
1317 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318 mac_mode |= MAC_MODE_PORT_MODE_MII;
1319 else
1320 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322 if (phydev->duplex == DUPLEX_HALF)
1323 mac_mode |= MAC_MODE_HALF_DUPLEX;
1324 else {
1325 lcl_adv = tg3_advert_flowctrl_1000T(
1326 tp->link_config.flowctrl);
1327
1328 if (phydev->pause)
1329 rmt_adv = LPA_PAUSE_CAP;
1330 if (phydev->asym_pause)
1331 rmt_adv |= LPA_PAUSE_ASYM;
1332 }
1333
1334 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335 } else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (mac_mode != tp->mac_mode) {
1339 tp->mac_mode = mac_mode;
1340 tw32_f(MAC_MODE, tp->mac_mode);
1341 udelay(40);
1342 }
1343
1344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345 if (phydev->speed == SPEED_10)
1346 tw32(MAC_MI_STAT,
1347 MAC_MI_STAT_10MBPS_MODE |
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349 else
1350 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351 }
1352
1353 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354 tw32(MAC_TX_LENGTHS,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356 (6 << TX_LENGTHS_IPG_SHIFT) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358 else
1359 tw32(MAC_TX_LENGTHS,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361 (6 << TX_LENGTHS_IPG_SHIFT) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366 phydev->speed != tp->link_config.active_speed ||
1367 phydev->duplex != tp->link_config.active_duplex ||
1368 oldflowctrl != tp->link_config.active_flowctrl)
1369 linkmesg = 1;
1370
1371 tp->link_config.active_speed = phydev->speed;
1372 tp->link_config.active_duplex = phydev->duplex;
1373
1374 spin_unlock(&tp->lock);
1375
1376 if (linkmesg)
1377 tg3_link_report(tp);
1378 }
1379
1380 static int tg3_phy_init(struct tg3 *tp)
1381 {
1382 struct phy_device *phydev;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385 return 0;
1386
1387 /* Bring the PHY back to a known state. */
1388 tg3_bmcr_reset(tp);
1389
1390 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1391
1392 /* Attach the MAC to the PHY. */
1393 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1394 phydev->dev_flags, phydev->interface);
1395 if (IS_ERR(phydev)) {
1396 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397 return PTR_ERR(phydev);
1398 }
1399
1400 /* Mask with MAC supported features. */
1401 switch (phydev->interface) {
1402 case PHY_INTERFACE_MODE_GMII:
1403 case PHY_INTERFACE_MODE_RGMII:
1404 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405 phydev->supported &= (PHY_GBIT_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 }
1410 /* fallthru */
1411 case PHY_INTERFACE_MODE_MII:
1412 phydev->supported &= (PHY_BASIC_FEATURES |
1413 SUPPORTED_Pause |
1414 SUPPORTED_Asym_Pause);
1415 break;
1416 default:
1417 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418 return -EINVAL;
1419 }
1420
1421 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1422
1423 phydev->advertising = phydev->supported;
1424
1425 return 0;
1426 }
1427
1428 static void tg3_phy_start(struct tg3 *tp)
1429 {
1430 struct phy_device *phydev;
1431
1432 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433 return;
1434
1435 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1436
1437 if (tp->link_config.phy_is_low_power) {
1438 tp->link_config.phy_is_low_power = 0;
1439 phydev->speed = tp->link_config.orig_speed;
1440 phydev->duplex = tp->link_config.orig_duplex;
1441 phydev->autoneg = tp->link_config.orig_autoneg;
1442 phydev->advertising = tp->link_config.orig_advertising;
1443 }
1444
1445 phy_start(phydev);
1446
1447 phy_start_aneg(phydev);
1448 }
1449
1450 static void tg3_phy_stop(struct tg3 *tp)
1451 {
1452 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453 return;
1454
1455 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1456 }
1457
1458 static void tg3_phy_fini(struct tg3 *tp)
1459 {
1460 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1461 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1462 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463 }
1464 }
1465
1466 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467 {
1468 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470 }
1471
1472 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473 {
1474 u32 reg;
1475
1476 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1478 return;
1479
1480 reg = MII_TG3_MISC_SHDW_WREN |
1481 MII_TG3_MISC_SHDW_SCR5_SEL |
1482 MII_TG3_MISC_SHDW_SCR5_LPED |
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484 MII_TG3_MISC_SHDW_SCR5_SDTL |
1485 MII_TG3_MISC_SHDW_SCR5_C125OE;
1486 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492 reg = MII_TG3_MISC_SHDW_WREN |
1493 MII_TG3_MISC_SHDW_APD_SEL |
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495 if (enable)
1496 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499 }
1500
1501 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502 {
1503 u32 phy;
1504
1505 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507 return;
1508
1509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510 u32 ephy;
1511
1512 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514 ephy | MII_TG3_EPHY_SHADOW_EN);
1515 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516 if (enable)
1517 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518 else
1519 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521 }
1522 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523 }
1524 } else {
1525 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526 MII_TG3_AUXCTL_SHDWSEL_MISC;
1527 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531 else
1532 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533 phy |= MII_TG3_AUXCTL_MISC_WREN;
1534 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535 }
1536 }
1537 }
1538
1539 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540 {
1541 u32 val;
1542
1543 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544 return;
1545
1546 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549 (val | (1 << 15) | (1 << 4)));
1550 }
1551
1552 static void tg3_phy_apply_otp(struct tg3 *tp)
1553 {
1554 u32 otp, phy;
1555
1556 if (!tp->phy_otp)
1557 return;
1558
1559 otp = tp->phy_otp;
1560
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564 MII_TG3_AUXCTL_ACTL_TX_6DB;
1565 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589 /* Turn off SM_DSP clock. */
1590 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591 MII_TG3_AUXCTL_ACTL_TX_6DB;
1592 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593 }
1594
1595 static int tg3_wait_macro_done(struct tg3 *tp)
1596 {
1597 int limit = 100;
1598
1599 while (limit--) {
1600 u32 tmp32;
1601
1602 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603 if ((tmp32 & 0x1000) == 0)
1604 break;
1605 }
1606 }
1607 if (limit < 0)
1608 return -EBUSY;
1609
1610 return 0;
1611 }
1612
1613 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614 {
1615 static const u32 test_pat[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620 };
1621 int chan;
1622
1623 for (chan = 0; chan < 4; chan++) {
1624 int i;
1625
1626 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627 (chan * 0x2000) | 0x0200);
1628 tg3_writephy(tp, 0x16, 0x0002);
1629
1630 for (i = 0; i < 6; i++)
1631 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632 test_pat[chan][i]);
1633
1634 tg3_writephy(tp, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp)) {
1636 *resetp = 1;
1637 return -EBUSY;
1638 }
1639
1640 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641 (chan * 0x2000) | 0x0200);
1642 tg3_writephy(tp, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp)) {
1644 *resetp = 1;
1645 return -EBUSY;
1646 }
1647
1648 tg3_writephy(tp, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp)) {
1650 *resetp = 1;
1651 return -EBUSY;
1652 }
1653
1654 for (i = 0; i < 6; i += 2) {
1655 u32 low, high;
1656
1657 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659 tg3_wait_macro_done(tp)) {
1660 *resetp = 1;
1661 return -EBUSY;
1662 }
1663 low &= 0x7fff;
1664 high &= 0x000f;
1665 if (low != test_pat[chan][i] ||
1666 high != test_pat[chan][i+1]) {
1667 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671 return -EBUSY;
1672 }
1673 }
1674 }
1675
1676 return 0;
1677 }
1678
1679 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680 {
1681 int chan;
1682
1683 for (chan = 0; chan < 4; chan++) {
1684 int i;
1685
1686 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687 (chan * 0x2000) | 0x0200);
1688 tg3_writephy(tp, 0x16, 0x0002);
1689 for (i = 0; i < 6; i++)
1690 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691 tg3_writephy(tp, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp))
1693 return -EBUSY;
1694 }
1695
1696 return 0;
1697 }
1698
1699 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700 {
1701 u32 reg32, phy9_orig;
1702 int retries, do_phy_reset, err;
1703
1704 retries = 10;
1705 do_phy_reset = 1;
1706 do {
1707 if (do_phy_reset) {
1708 err = tg3_bmcr_reset(tp);
1709 if (err)
1710 return err;
1711 do_phy_reset = 0;
1712 }
1713
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716 continue;
1717
1718 reg32 |= 0x3000;
1719 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp, MII_BMCR,
1723 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727 continue;
1728
1729 tg3_writephy(tp, MII_TG3_CTRL,
1730 (MII_TG3_CTRL_AS_MASTER |
1731 MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741 if (!err)
1742 break;
1743 } while (--retries);
1744
1745 err = tg3_phy_reset_chanpat(tp);
1746 if (err)
1747 return err;
1748
1749 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753 tg3_writephy(tp, 0x16, 0x0000);
1754
1755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759 }
1760 else {
1761 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762 }
1763
1764 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767 reg32 &= ~0x3000;
1768 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769 } else if (!err)
1770 err = -EBUSY;
1771
1772 return err;
1773 }
1774
1775 /* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1777 */
1778 static int tg3_phy_reset(struct tg3 *tp)
1779 {
1780 u32 cpmuctrl;
1781 u32 phy_status;
1782 int err;
1783
1784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785 u32 val;
1786
1787 val = tr32(GRC_MISC_CFG);
1788 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789 udelay(40);
1790 }
1791 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1792 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793 if (err != 0)
1794 return -EBUSY;
1795
1796 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797 netif_carrier_off(tp->dev);
1798 tg3_link_report(tp);
1799 }
1800
1801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804 err = tg3_phy_reset_5703_4_5(tp);
1805 if (err)
1806 return err;
1807 goto out;
1808 }
1809
1810 cpmuctrl = 0;
1811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815 tw32(TG3_CPMU_CTRL,
1816 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817 }
1818
1819 err = tg3_bmcr_reset(tp);
1820 if (err)
1821 return err;
1822
1823 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824 u32 phy;
1825
1826 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830 }
1831
1832 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1834 u32 val;
1835
1836 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5) {
1839 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840 udelay(40);
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842 }
1843 }
1844
1845 tg3_phy_apply_otp(tp);
1846
1847 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848 tg3_phy_toggle_apd(tp, true);
1849 else
1850 tg3_phy_toggle_apd(tp, false);
1851
1852 out:
1853 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860 }
1861 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862 tg3_writephy(tp, 0x1c, 0x8d68);
1863 tg3_writephy(tp, 0x1c, 0x8d68);
1864 }
1865 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874 }
1875 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1878 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880 tg3_writephy(tp, MII_TG3_TEST1,
1881 MII_TG3_TEST1_TRIM_EN | 0x4);
1882 } else
1883 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1884 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885 }
1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1891 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1892 u32 phy_reg;
1893
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898 }
1899
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1902 */
1903 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1904 u32 phy_reg;
1905
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909 }
1910
1911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1912 /* adjust output voltage */
1913 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1914 }
1915
1916 tg3_phy_toggle_automdix(tp, 1);
1917 tg3_phy_set_wirespeed(tp);
1918 return 0;
1919 }
1920
1921 static void tg3_frob_aux_power(struct tg3 *tp)
1922 {
1923 struct tg3 *tp_peer = tp;
1924
1925 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1926 return;
1927
1928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930 struct net_device *dev_peer;
1931
1932 dev_peer = pci_get_drvdata(tp->pdev_peer);
1933 /* remove_one() may have been run on the peer. */
1934 if (!dev_peer)
1935 tp_peer = tp;
1936 else
1937 tp_peer = netdev_priv(dev_peer);
1938 }
1939
1940 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1941 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1946 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947 (GRC_LCLCTRL_GPIO_OE0 |
1948 GRC_LCLCTRL_GPIO_OE1 |
1949 GRC_LCLCTRL_GPIO_OE2 |
1950 GRC_LCLCTRL_GPIO_OUTPUT0 |
1951 GRC_LCLCTRL_GPIO_OUTPUT1),
1952 100);
1953 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1954 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1955 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1956 GRC_LCLCTRL_GPIO_OE1 |
1957 GRC_LCLCTRL_GPIO_OE2 |
1958 GRC_LCLCTRL_GPIO_OUTPUT0 |
1959 GRC_LCLCTRL_GPIO_OUTPUT1 |
1960 tp->grc_local_ctrl;
1961 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1962
1963 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1964 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1965
1966 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1967 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1968 } else {
1969 u32 no_gpio2;
1970 u32 grc_local_ctrl = 0;
1971
1972 if (tp_peer != tp &&
1973 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1974 return;
1975
1976 /* Workaround to prevent overdrawing Amps. */
1977 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1978 ASIC_REV_5714) {
1979 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1980 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1981 grc_local_ctrl, 100);
1982 }
1983
1984 /* On 5753 and variants, GPIO2 cannot be used. */
1985 no_gpio2 = tp->nic_sram_data_cfg &
1986 NIC_SRAM_DATA_CFG_NO_GPIO2;
1987
1988 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1989 GRC_LCLCTRL_GPIO_OE1 |
1990 GRC_LCLCTRL_GPIO_OE2 |
1991 GRC_LCLCTRL_GPIO_OUTPUT1 |
1992 GRC_LCLCTRL_GPIO_OUTPUT2;
1993 if (no_gpio2) {
1994 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1995 GRC_LCLCTRL_GPIO_OUTPUT2);
1996 }
1997 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1998 grc_local_ctrl, 100);
1999
2000 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2001
2002 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2003 grc_local_ctrl, 100);
2004
2005 if (!no_gpio2) {
2006 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2007 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2008 grc_local_ctrl, 100);
2009 }
2010 }
2011 } else {
2012 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2013 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2014 if (tp_peer != tp &&
2015 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2016 return;
2017
2018 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2019 (GRC_LCLCTRL_GPIO_OE1 |
2020 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2021
2022 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2023 GRC_LCLCTRL_GPIO_OE1, 100);
2024
2025 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2026 (GRC_LCLCTRL_GPIO_OE1 |
2027 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2028 }
2029 }
2030 }
2031
2032 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2033 {
2034 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2035 return 1;
2036 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2037 if (speed != SPEED_10)
2038 return 1;
2039 } else if (speed == SPEED_10)
2040 return 1;
2041
2042 return 0;
2043 }
2044
2045 static int tg3_setup_phy(struct tg3 *, int);
2046
2047 #define RESET_KIND_SHUTDOWN 0
2048 #define RESET_KIND_INIT 1
2049 #define RESET_KIND_SUSPEND 2
2050
2051 static void tg3_write_sig_post_reset(struct tg3 *, int);
2052 static int tg3_halt_cpu(struct tg3 *, u32);
2053
2054 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2055 {
2056 u32 val;
2057
2058 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2060 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2061 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2062
2063 sg_dig_ctrl |=
2064 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2065 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2066 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2067 }
2068 return;
2069 }
2070
2071 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2072 tg3_bmcr_reset(tp);
2073 val = tr32(GRC_MISC_CFG);
2074 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2075 udelay(40);
2076 return;
2077 } else if (do_low_power) {
2078 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2079 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2080
2081 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2082 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2083 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2084 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2085 MII_TG3_AUXCTL_PCTL_VREG_11V);
2086 }
2087
2088 /* The PHY should not be powered down on some chips because
2089 * of bugs.
2090 */
2091 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2093 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2094 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2095 return;
2096
2097 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2098 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2099 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2100 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2101 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2102 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2103 }
2104
2105 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2106 }
2107
2108 /* tp->lock is held. */
2109 static int tg3_nvram_lock(struct tg3 *tp)
2110 {
2111 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2112 int i;
2113
2114 if (tp->nvram_lock_cnt == 0) {
2115 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2116 for (i = 0; i < 8000; i++) {
2117 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2118 break;
2119 udelay(20);
2120 }
2121 if (i == 8000) {
2122 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2123 return -ENODEV;
2124 }
2125 }
2126 tp->nvram_lock_cnt++;
2127 }
2128 return 0;
2129 }
2130
2131 /* tp->lock is held. */
2132 static void tg3_nvram_unlock(struct tg3 *tp)
2133 {
2134 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2135 if (tp->nvram_lock_cnt > 0)
2136 tp->nvram_lock_cnt--;
2137 if (tp->nvram_lock_cnt == 0)
2138 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2139 }
2140 }
2141
2142 /* tp->lock is held. */
2143 static void tg3_enable_nvram_access(struct tg3 *tp)
2144 {
2145 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2146 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2147 u32 nvaccess = tr32(NVRAM_ACCESS);
2148
2149 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2150 }
2151 }
2152
2153 /* tp->lock is held. */
2154 static void tg3_disable_nvram_access(struct tg3 *tp)
2155 {
2156 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2157 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2158 u32 nvaccess = tr32(NVRAM_ACCESS);
2159
2160 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2161 }
2162 }
2163
2164 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2165 u32 offset, u32 *val)
2166 {
2167 u32 tmp;
2168 int i;
2169
2170 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2171 return -EINVAL;
2172
2173 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2174 EEPROM_ADDR_DEVID_MASK |
2175 EEPROM_ADDR_READ);
2176 tw32(GRC_EEPROM_ADDR,
2177 tmp |
2178 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2179 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2180 EEPROM_ADDR_ADDR_MASK) |
2181 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2182
2183 for (i = 0; i < 1000; i++) {
2184 tmp = tr32(GRC_EEPROM_ADDR);
2185
2186 if (tmp & EEPROM_ADDR_COMPLETE)
2187 break;
2188 msleep(1);
2189 }
2190 if (!(tmp & EEPROM_ADDR_COMPLETE))
2191 return -EBUSY;
2192
2193 *val = tr32(GRC_EEPROM_DATA);
2194 return 0;
2195 }
2196
2197 #define NVRAM_CMD_TIMEOUT 10000
2198
2199 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2200 {
2201 int i;
2202
2203 tw32(NVRAM_CMD, nvram_cmd);
2204 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2205 udelay(10);
2206 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2207 udelay(10);
2208 break;
2209 }
2210 }
2211
2212 if (i == NVRAM_CMD_TIMEOUT)
2213 return -EBUSY;
2214
2215 return 0;
2216 }
2217
2218 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2219 {
2220 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2221 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2222 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2223 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2224 (tp->nvram_jedecnum == JEDEC_ATMEL))
2225
2226 addr = ((addr / tp->nvram_pagesize) <<
2227 ATMEL_AT45DB0X1B_PAGE_POS) +
2228 (addr % tp->nvram_pagesize);
2229
2230 return addr;
2231 }
2232
2233 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2234 {
2235 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2236 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2237 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2238 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2239 (tp->nvram_jedecnum == JEDEC_ATMEL))
2240
2241 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2242 tp->nvram_pagesize) +
2243 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2244
2245 return addr;
2246 }
2247
2248 /* NOTE: Data read in from NVRAM is byteswapped according to
2249 * the byteswapping settings for all other register accesses.
2250 * tg3 devices are BE devices, so on a BE machine, the data
2251 * returned will be exactly as it is seen in NVRAM. On a LE
2252 * machine, the 32-bit value will be byteswapped.
2253 */
2254 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2255 {
2256 int ret;
2257
2258 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2259 return tg3_nvram_read_using_eeprom(tp, offset, val);
2260
2261 offset = tg3_nvram_phys_addr(tp, offset);
2262
2263 if (offset > NVRAM_ADDR_MSK)
2264 return -EINVAL;
2265
2266 ret = tg3_nvram_lock(tp);
2267 if (ret)
2268 return ret;
2269
2270 tg3_enable_nvram_access(tp);
2271
2272 tw32(NVRAM_ADDR, offset);
2273 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2274 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2275
2276 if (ret == 0)
2277 *val = tr32(NVRAM_RDDATA);
2278
2279 tg3_disable_nvram_access(tp);
2280
2281 tg3_nvram_unlock(tp);
2282
2283 return ret;
2284 }
2285
2286 /* Ensures NVRAM data is in bytestream format. */
2287 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2288 {
2289 u32 v;
2290 int res = tg3_nvram_read(tp, offset, &v);
2291 if (!res)
2292 *val = cpu_to_be32(v);
2293 return res;
2294 }
2295
2296 /* tp->lock is held. */
2297 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2298 {
2299 u32 addr_high, addr_low;
2300 int i;
2301
2302 addr_high = ((tp->dev->dev_addr[0] << 8) |
2303 tp->dev->dev_addr[1]);
2304 addr_low = ((tp->dev->dev_addr[2] << 24) |
2305 (tp->dev->dev_addr[3] << 16) |
2306 (tp->dev->dev_addr[4] << 8) |
2307 (tp->dev->dev_addr[5] << 0));
2308 for (i = 0; i < 4; i++) {
2309 if (i == 1 && skip_mac_1)
2310 continue;
2311 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2312 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2313 }
2314
2315 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2316 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2317 for (i = 0; i < 12; i++) {
2318 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2319 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2320 }
2321 }
2322
2323 addr_high = (tp->dev->dev_addr[0] +
2324 tp->dev->dev_addr[1] +
2325 tp->dev->dev_addr[2] +
2326 tp->dev->dev_addr[3] +
2327 tp->dev->dev_addr[4] +
2328 tp->dev->dev_addr[5]) &
2329 TX_BACKOFF_SEED_MASK;
2330 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2331 }
2332
2333 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2334 {
2335 u32 misc_host_ctrl;
2336 bool device_should_wake, do_low_power;
2337
2338 /* Make sure register accesses (indirect or otherwise)
2339 * will function correctly.
2340 */
2341 pci_write_config_dword(tp->pdev,
2342 TG3PCI_MISC_HOST_CTRL,
2343 tp->misc_host_ctrl);
2344
2345 switch (state) {
2346 case PCI_D0:
2347 pci_enable_wake(tp->pdev, state, false);
2348 pci_set_power_state(tp->pdev, PCI_D0);
2349
2350 /* Switch out of Vaux if it is a NIC */
2351 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2352 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2353
2354 return 0;
2355
2356 case PCI_D1:
2357 case PCI_D2:
2358 case PCI_D3hot:
2359 break;
2360
2361 default:
2362 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2363 tp->dev->name, state);
2364 return -EINVAL;
2365 }
2366
2367 /* Restore the CLKREQ setting. */
2368 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2369 u16 lnkctl;
2370
2371 pci_read_config_word(tp->pdev,
2372 tp->pcie_cap + PCI_EXP_LNKCTL,
2373 &lnkctl);
2374 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2375 pci_write_config_word(tp->pdev,
2376 tp->pcie_cap + PCI_EXP_LNKCTL,
2377 lnkctl);
2378 }
2379
2380 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2381 tw32(TG3PCI_MISC_HOST_CTRL,
2382 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2383
2384 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2385 device_may_wakeup(&tp->pdev->dev) &&
2386 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2387
2388 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2389 do_low_power = false;
2390 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2391 !tp->link_config.phy_is_low_power) {
2392 struct phy_device *phydev;
2393 u32 phyid, advertising;
2394
2395 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2396
2397 tp->link_config.phy_is_low_power = 1;
2398
2399 tp->link_config.orig_speed = phydev->speed;
2400 tp->link_config.orig_duplex = phydev->duplex;
2401 tp->link_config.orig_autoneg = phydev->autoneg;
2402 tp->link_config.orig_advertising = phydev->advertising;
2403
2404 advertising = ADVERTISED_TP |
2405 ADVERTISED_Pause |
2406 ADVERTISED_Autoneg |
2407 ADVERTISED_10baseT_Half;
2408
2409 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2410 device_should_wake) {
2411 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2412 advertising |=
2413 ADVERTISED_100baseT_Half |
2414 ADVERTISED_100baseT_Full |
2415 ADVERTISED_10baseT_Full;
2416 else
2417 advertising |= ADVERTISED_10baseT_Full;
2418 }
2419
2420 phydev->advertising = advertising;
2421
2422 phy_start_aneg(phydev);
2423
2424 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2425 if (phyid != TG3_PHY_ID_BCMAC131) {
2426 phyid &= TG3_PHY_OUI_MASK;
2427 if (phyid == TG3_PHY_OUI_1 ||
2428 phyid == TG3_PHY_OUI_2 ||
2429 phyid == TG3_PHY_OUI_3)
2430 do_low_power = true;
2431 }
2432 }
2433 } else {
2434 do_low_power = true;
2435
2436 if (tp->link_config.phy_is_low_power == 0) {
2437 tp->link_config.phy_is_low_power = 1;
2438 tp->link_config.orig_speed = tp->link_config.speed;
2439 tp->link_config.orig_duplex = tp->link_config.duplex;
2440 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2441 }
2442
2443 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2444 tp->link_config.speed = SPEED_10;
2445 tp->link_config.duplex = DUPLEX_HALF;
2446 tp->link_config.autoneg = AUTONEG_ENABLE;
2447 tg3_setup_phy(tp, 0);
2448 }
2449 }
2450
2451 __tg3_set_mac_addr(tp, 0);
2452
2453 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2454 u32 val;
2455
2456 val = tr32(GRC_VCPU_EXT_CTRL);
2457 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2458 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2459 int i;
2460 u32 val;
2461
2462 for (i = 0; i < 200; i++) {
2463 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2464 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2465 break;
2466 msleep(1);
2467 }
2468 }
2469 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2470 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2471 WOL_DRV_STATE_SHUTDOWN |
2472 WOL_DRV_WOL |
2473 WOL_SET_MAGIC_PKT);
2474
2475 if (device_should_wake) {
2476 u32 mac_mode;
2477
2478 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2479 if (do_low_power) {
2480 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2481 udelay(40);
2482 }
2483
2484 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2485 mac_mode = MAC_MODE_PORT_MODE_GMII;
2486 else
2487 mac_mode = MAC_MODE_PORT_MODE_MII;
2488
2489 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2490 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2491 ASIC_REV_5700) {
2492 u32 speed = (tp->tg3_flags &
2493 TG3_FLAG_WOL_SPEED_100MB) ?
2494 SPEED_100 : SPEED_10;
2495 if (tg3_5700_link_polarity(tp, speed))
2496 mac_mode |= MAC_MODE_LINK_POLARITY;
2497 else
2498 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2499 }
2500 } else {
2501 mac_mode = MAC_MODE_PORT_MODE_TBI;
2502 }
2503
2504 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2505 tw32(MAC_LED_CTRL, tp->led_ctrl);
2506
2507 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2508 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2509 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2510 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2511 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2512 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2513
2514 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2515 mac_mode |= tp->mac_mode &
2516 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2517 if (mac_mode & MAC_MODE_APE_TX_EN)
2518 mac_mode |= MAC_MODE_TDE_ENABLE;
2519 }
2520
2521 tw32_f(MAC_MODE, mac_mode);
2522 udelay(100);
2523
2524 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2525 udelay(10);
2526 }
2527
2528 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2529 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2531 u32 base_val;
2532
2533 base_val = tp->pci_clock_ctrl;
2534 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2535 CLOCK_CTRL_TXCLK_DISABLE);
2536
2537 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2538 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2539 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2540 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2541 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2542 /* do nothing */
2543 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2544 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2545 u32 newbits1, newbits2;
2546
2547 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2548 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2549 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2550 CLOCK_CTRL_TXCLK_DISABLE |
2551 CLOCK_CTRL_ALTCLK);
2552 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2553 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2554 newbits1 = CLOCK_CTRL_625_CORE;
2555 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2556 } else {
2557 newbits1 = CLOCK_CTRL_ALTCLK;
2558 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2559 }
2560
2561 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2562 40);
2563
2564 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2565 40);
2566
2567 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2568 u32 newbits3;
2569
2570 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2571 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2572 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2573 CLOCK_CTRL_TXCLK_DISABLE |
2574 CLOCK_CTRL_44MHZ_CORE);
2575 } else {
2576 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2577 }
2578
2579 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2580 tp->pci_clock_ctrl | newbits3, 40);
2581 }
2582 }
2583
2584 if (!(device_should_wake) &&
2585 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2586 tg3_power_down_phy(tp, do_low_power);
2587
2588 tg3_frob_aux_power(tp);
2589
2590 /* Workaround for unstable PLL clock */
2591 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2592 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2593 u32 val = tr32(0x7d00);
2594
2595 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2596 tw32(0x7d00, val);
2597 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2598 int err;
2599
2600 err = tg3_nvram_lock(tp);
2601 tg3_halt_cpu(tp, RX_CPU_BASE);
2602 if (!err)
2603 tg3_nvram_unlock(tp);
2604 }
2605 }
2606
2607 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2608
2609 if (device_should_wake)
2610 pci_enable_wake(tp->pdev, state, true);
2611
2612 /* Finally, set the new power state. */
2613 pci_set_power_state(tp->pdev, state);
2614
2615 return 0;
2616 }
2617
2618 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2619 {
2620 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2621 case MII_TG3_AUX_STAT_10HALF:
2622 *speed = SPEED_10;
2623 *duplex = DUPLEX_HALF;
2624 break;
2625
2626 case MII_TG3_AUX_STAT_10FULL:
2627 *speed = SPEED_10;
2628 *duplex = DUPLEX_FULL;
2629 break;
2630
2631 case MII_TG3_AUX_STAT_100HALF:
2632 *speed = SPEED_100;
2633 *duplex = DUPLEX_HALF;
2634 break;
2635
2636 case MII_TG3_AUX_STAT_100FULL:
2637 *speed = SPEED_100;
2638 *duplex = DUPLEX_FULL;
2639 break;
2640
2641 case MII_TG3_AUX_STAT_1000HALF:
2642 *speed = SPEED_1000;
2643 *duplex = DUPLEX_HALF;
2644 break;
2645
2646 case MII_TG3_AUX_STAT_1000FULL:
2647 *speed = SPEED_1000;
2648 *duplex = DUPLEX_FULL;
2649 break;
2650
2651 default:
2652 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2653 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2654 SPEED_10;
2655 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2656 DUPLEX_HALF;
2657 break;
2658 }
2659 *speed = SPEED_INVALID;
2660 *duplex = DUPLEX_INVALID;
2661 break;
2662 }
2663 }
2664
2665 static void tg3_phy_copper_begin(struct tg3 *tp)
2666 {
2667 u32 new_adv;
2668 int i;
2669
2670 if (tp->link_config.phy_is_low_power) {
2671 /* Entering low power mode. Disable gigabit and
2672 * 100baseT advertisements.
2673 */
2674 tg3_writephy(tp, MII_TG3_CTRL, 0);
2675
2676 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2677 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2678 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2679 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2680
2681 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2682 } else if (tp->link_config.speed == SPEED_INVALID) {
2683 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2684 tp->link_config.advertising &=
2685 ~(ADVERTISED_1000baseT_Half |
2686 ADVERTISED_1000baseT_Full);
2687
2688 new_adv = ADVERTISE_CSMA;
2689 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2690 new_adv |= ADVERTISE_10HALF;
2691 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2692 new_adv |= ADVERTISE_10FULL;
2693 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2694 new_adv |= ADVERTISE_100HALF;
2695 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2696 new_adv |= ADVERTISE_100FULL;
2697
2698 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2699
2700 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2701
2702 if (tp->link_config.advertising &
2703 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2704 new_adv = 0;
2705 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2706 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2707 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2708 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2709 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2710 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2711 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2712 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2713 MII_TG3_CTRL_ENABLE_AS_MASTER);
2714 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2715 } else {
2716 tg3_writephy(tp, MII_TG3_CTRL, 0);
2717 }
2718 } else {
2719 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2720 new_adv |= ADVERTISE_CSMA;
2721
2722 /* Asking for a specific link mode. */
2723 if (tp->link_config.speed == SPEED_1000) {
2724 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2725
2726 if (tp->link_config.duplex == DUPLEX_FULL)
2727 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2728 else
2729 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2730 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2731 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2732 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2733 MII_TG3_CTRL_ENABLE_AS_MASTER);
2734 } else {
2735 if (tp->link_config.speed == SPEED_100) {
2736 if (tp->link_config.duplex == DUPLEX_FULL)
2737 new_adv |= ADVERTISE_100FULL;
2738 else
2739 new_adv |= ADVERTISE_100HALF;
2740 } else {
2741 if (tp->link_config.duplex == DUPLEX_FULL)
2742 new_adv |= ADVERTISE_10FULL;
2743 else
2744 new_adv |= ADVERTISE_10HALF;
2745 }
2746 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2747
2748 new_adv = 0;
2749 }
2750
2751 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2752 }
2753
2754 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2755 tp->link_config.speed != SPEED_INVALID) {
2756 u32 bmcr, orig_bmcr;
2757
2758 tp->link_config.active_speed = tp->link_config.speed;
2759 tp->link_config.active_duplex = tp->link_config.duplex;
2760
2761 bmcr = 0;
2762 switch (tp->link_config.speed) {
2763 default:
2764 case SPEED_10:
2765 break;
2766
2767 case SPEED_100:
2768 bmcr |= BMCR_SPEED100;
2769 break;
2770
2771 case SPEED_1000:
2772 bmcr |= TG3_BMCR_SPEED1000;
2773 break;
2774 }
2775
2776 if (tp->link_config.duplex == DUPLEX_FULL)
2777 bmcr |= BMCR_FULLDPLX;
2778
2779 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2780 (bmcr != orig_bmcr)) {
2781 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2782 for (i = 0; i < 1500; i++) {
2783 u32 tmp;
2784
2785 udelay(10);
2786 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2787 tg3_readphy(tp, MII_BMSR, &tmp))
2788 continue;
2789 if (!(tmp & BMSR_LSTATUS)) {
2790 udelay(40);
2791 break;
2792 }
2793 }
2794 tg3_writephy(tp, MII_BMCR, bmcr);
2795 udelay(40);
2796 }
2797 } else {
2798 tg3_writephy(tp, MII_BMCR,
2799 BMCR_ANENABLE | BMCR_ANRESTART);
2800 }
2801 }
2802
2803 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2804 {
2805 int err;
2806
2807 /* Turn off tap power management. */
2808 /* Set Extended packet length bit */
2809 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2810
2811 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2812 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2813
2814 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2815 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2816
2817 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2818 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2819
2820 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2821 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2822
2823 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2824 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2825
2826 udelay(40);
2827
2828 return err;
2829 }
2830
2831 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2832 {
2833 u32 adv_reg, all_mask = 0;
2834
2835 if (mask & ADVERTISED_10baseT_Half)
2836 all_mask |= ADVERTISE_10HALF;
2837 if (mask & ADVERTISED_10baseT_Full)
2838 all_mask |= ADVERTISE_10FULL;
2839 if (mask & ADVERTISED_100baseT_Half)
2840 all_mask |= ADVERTISE_100HALF;
2841 if (mask & ADVERTISED_100baseT_Full)
2842 all_mask |= ADVERTISE_100FULL;
2843
2844 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2845 return 0;
2846
2847 if ((adv_reg & all_mask) != all_mask)
2848 return 0;
2849 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2850 u32 tg3_ctrl;
2851
2852 all_mask = 0;
2853 if (mask & ADVERTISED_1000baseT_Half)
2854 all_mask |= ADVERTISE_1000HALF;
2855 if (mask & ADVERTISED_1000baseT_Full)
2856 all_mask |= ADVERTISE_1000FULL;
2857
2858 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2859 return 0;
2860
2861 if ((tg3_ctrl & all_mask) != all_mask)
2862 return 0;
2863 }
2864 return 1;
2865 }
2866
2867 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2868 {
2869 u32 curadv, reqadv;
2870
2871 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2872 return 1;
2873
2874 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2875 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2876
2877 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2878 if (curadv != reqadv)
2879 return 0;
2880
2881 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2882 tg3_readphy(tp, MII_LPA, rmtadv);
2883 } else {
2884 /* Reprogram the advertisement register, even if it
2885 * does not affect the current link. If the link
2886 * gets renegotiated in the future, we can save an
2887 * additional renegotiation cycle by advertising
2888 * it correctly in the first place.
2889 */
2890 if (curadv != reqadv) {
2891 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2892 ADVERTISE_PAUSE_ASYM);
2893 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2894 }
2895 }
2896
2897 return 1;
2898 }
2899
2900 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2901 {
2902 int current_link_up;
2903 u32 bmsr, dummy;
2904 u32 lcl_adv, rmt_adv;
2905 u16 current_speed;
2906 u8 current_duplex;
2907 int i, err;
2908
2909 tw32(MAC_EVENT, 0);
2910
2911 tw32_f(MAC_STATUS,
2912 (MAC_STATUS_SYNC_CHANGED |
2913 MAC_STATUS_CFG_CHANGED |
2914 MAC_STATUS_MI_COMPLETION |
2915 MAC_STATUS_LNKSTATE_CHANGED));
2916 udelay(40);
2917
2918 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2919 tw32_f(MAC_MI_MODE,
2920 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2921 udelay(80);
2922 }
2923
2924 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2925
2926 /* Some third-party PHYs need to be reset on link going
2927 * down.
2928 */
2929 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2931 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2932 netif_carrier_ok(tp->dev)) {
2933 tg3_readphy(tp, MII_BMSR, &bmsr);
2934 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2935 !(bmsr & BMSR_LSTATUS))
2936 force_reset = 1;
2937 }
2938 if (force_reset)
2939 tg3_phy_reset(tp);
2940
2941 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2942 tg3_readphy(tp, MII_BMSR, &bmsr);
2943 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2944 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2945 bmsr = 0;
2946
2947 if (!(bmsr & BMSR_LSTATUS)) {
2948 err = tg3_init_5401phy_dsp(tp);
2949 if (err)
2950 return err;
2951
2952 tg3_readphy(tp, MII_BMSR, &bmsr);
2953 for (i = 0; i < 1000; i++) {
2954 udelay(10);
2955 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2956 (bmsr & BMSR_LSTATUS)) {
2957 udelay(40);
2958 break;
2959 }
2960 }
2961
2962 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2963 !(bmsr & BMSR_LSTATUS) &&
2964 tp->link_config.active_speed == SPEED_1000) {
2965 err = tg3_phy_reset(tp);
2966 if (!err)
2967 err = tg3_init_5401phy_dsp(tp);
2968 if (err)
2969 return err;
2970 }
2971 }
2972 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2973 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2974 /* 5701 {A0,B0} CRC bug workaround */
2975 tg3_writephy(tp, 0x15, 0x0a75);
2976 tg3_writephy(tp, 0x1c, 0x8c68);
2977 tg3_writephy(tp, 0x1c, 0x8d68);
2978 tg3_writephy(tp, 0x1c, 0x8c68);
2979 }
2980
2981 /* Clear pending interrupts... */
2982 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2983 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2984
2985 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2986 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2987 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2988 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2989
2990 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2992 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2993 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2994 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2995 else
2996 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2997 }
2998
2999 current_link_up = 0;
3000 current_speed = SPEED_INVALID;
3001 current_duplex = DUPLEX_INVALID;
3002
3003 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3004 u32 val;
3005
3006 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3007 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3008 if (!(val & (1 << 10))) {
3009 val |= (1 << 10);
3010 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3011 goto relink;
3012 }
3013 }
3014
3015 bmsr = 0;
3016 for (i = 0; i < 100; i++) {
3017 tg3_readphy(tp, MII_BMSR, &bmsr);
3018 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3019 (bmsr & BMSR_LSTATUS))
3020 break;
3021 udelay(40);
3022 }
3023
3024 if (bmsr & BMSR_LSTATUS) {
3025 u32 aux_stat, bmcr;
3026
3027 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3028 for (i = 0; i < 2000; i++) {
3029 udelay(10);
3030 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3031 aux_stat)
3032 break;
3033 }
3034
3035 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3036 &current_speed,
3037 &current_duplex);
3038
3039 bmcr = 0;
3040 for (i = 0; i < 200; i++) {
3041 tg3_readphy(tp, MII_BMCR, &bmcr);
3042 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3043 continue;
3044 if (bmcr && bmcr != 0x7fff)
3045 break;
3046 udelay(10);
3047 }
3048
3049 lcl_adv = 0;
3050 rmt_adv = 0;
3051
3052 tp->link_config.active_speed = current_speed;
3053 tp->link_config.active_duplex = current_duplex;
3054
3055 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3056 if ((bmcr & BMCR_ANENABLE) &&
3057 tg3_copper_is_advertising_all(tp,
3058 tp->link_config.advertising)) {
3059 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3060 &rmt_adv))
3061 current_link_up = 1;
3062 }
3063 } else {
3064 if (!(bmcr & BMCR_ANENABLE) &&
3065 tp->link_config.speed == current_speed &&
3066 tp->link_config.duplex == current_duplex &&
3067 tp->link_config.flowctrl ==
3068 tp->link_config.active_flowctrl) {
3069 current_link_up = 1;
3070 }
3071 }
3072
3073 if (current_link_up == 1 &&
3074 tp->link_config.active_duplex == DUPLEX_FULL)
3075 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3076 }
3077
3078 relink:
3079 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3080 u32 tmp;
3081
3082 tg3_phy_copper_begin(tp);
3083
3084 tg3_readphy(tp, MII_BMSR, &tmp);
3085 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3086 (tmp & BMSR_LSTATUS))
3087 current_link_up = 1;
3088 }
3089
3090 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3091 if (current_link_up == 1) {
3092 if (tp->link_config.active_speed == SPEED_100 ||
3093 tp->link_config.active_speed == SPEED_10)
3094 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3095 else
3096 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3097 } else
3098 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3099
3100 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3101 if (tp->link_config.active_duplex == DUPLEX_HALF)
3102 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3103
3104 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3105 if (current_link_up == 1 &&
3106 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3107 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3108 else
3109 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3110 }
3111
3112 /* ??? Without this setting Netgear GA302T PHY does not
3113 * ??? send/receive packets...
3114 */
3115 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3116 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3117 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3118 tw32_f(MAC_MI_MODE, tp->mi_mode);
3119 udelay(80);
3120 }
3121
3122 tw32_f(MAC_MODE, tp->mac_mode);
3123 udelay(40);
3124
3125 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3126 /* Polled via timer. */
3127 tw32_f(MAC_EVENT, 0);
3128 } else {
3129 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3130 }
3131 udelay(40);
3132
3133 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3134 current_link_up == 1 &&
3135 tp->link_config.active_speed == SPEED_1000 &&
3136 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3137 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3138 udelay(120);
3139 tw32_f(MAC_STATUS,
3140 (MAC_STATUS_SYNC_CHANGED |
3141 MAC_STATUS_CFG_CHANGED));
3142 udelay(40);
3143 tg3_write_mem(tp,
3144 NIC_SRAM_FIRMWARE_MBOX,
3145 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3146 }
3147
3148 /* Prevent send BD corruption. */
3149 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3150 u16 oldlnkctl, newlnkctl;
3151
3152 pci_read_config_word(tp->pdev,
3153 tp->pcie_cap + PCI_EXP_LNKCTL,
3154 &oldlnkctl);
3155 if (tp->link_config.active_speed == SPEED_100 ||
3156 tp->link_config.active_speed == SPEED_10)
3157 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3158 else
3159 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3160 if (newlnkctl != oldlnkctl)
3161 pci_write_config_word(tp->pdev,
3162 tp->pcie_cap + PCI_EXP_LNKCTL,
3163 newlnkctl);
3164 }
3165
3166 if (current_link_up != netif_carrier_ok(tp->dev)) {
3167 if (current_link_up)
3168 netif_carrier_on(tp->dev);
3169 else
3170 netif_carrier_off(tp->dev);
3171 tg3_link_report(tp);
3172 }
3173
3174 return 0;
3175 }
3176
3177 struct tg3_fiber_aneginfo {
3178 int state;
3179 #define ANEG_STATE_UNKNOWN 0
3180 #define ANEG_STATE_AN_ENABLE 1
3181 #define ANEG_STATE_RESTART_INIT 2
3182 #define ANEG_STATE_RESTART 3
3183 #define ANEG_STATE_DISABLE_LINK_OK 4
3184 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3185 #define ANEG_STATE_ABILITY_DETECT 6
3186 #define ANEG_STATE_ACK_DETECT_INIT 7
3187 #define ANEG_STATE_ACK_DETECT 8
3188 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3189 #define ANEG_STATE_COMPLETE_ACK 10
3190 #define ANEG_STATE_IDLE_DETECT_INIT 11
3191 #define ANEG_STATE_IDLE_DETECT 12
3192 #define ANEG_STATE_LINK_OK 13
3193 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3194 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3195
3196 u32 flags;
3197 #define MR_AN_ENABLE 0x00000001
3198 #define MR_RESTART_AN 0x00000002
3199 #define MR_AN_COMPLETE 0x00000004
3200 #define MR_PAGE_RX 0x00000008
3201 #define MR_NP_LOADED 0x00000010
3202 #define MR_TOGGLE_TX 0x00000020
3203 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3204 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3205 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3206 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3207 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3208 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3209 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3210 #define MR_TOGGLE_RX 0x00002000
3211 #define MR_NP_RX 0x00004000
3212
3213 #define MR_LINK_OK 0x80000000
3214
3215 unsigned long link_time, cur_time;
3216
3217 u32 ability_match_cfg;
3218 int ability_match_count;
3219
3220 char ability_match, idle_match, ack_match;
3221
3222 u32 txconfig, rxconfig;
3223 #define ANEG_CFG_NP 0x00000080
3224 #define ANEG_CFG_ACK 0x00000040
3225 #define ANEG_CFG_RF2 0x00000020
3226 #define ANEG_CFG_RF1 0x00000010
3227 #define ANEG_CFG_PS2 0x00000001
3228 #define ANEG_CFG_PS1 0x00008000
3229 #define ANEG_CFG_HD 0x00004000
3230 #define ANEG_CFG_FD 0x00002000
3231 #define ANEG_CFG_INVAL 0x00001f06
3232
3233 };
3234 #define ANEG_OK 0
3235 #define ANEG_DONE 1
3236 #define ANEG_TIMER_ENAB 2
3237 #define ANEG_FAILED -1
3238
3239 #define ANEG_STATE_SETTLE_TIME 10000
3240
3241 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3242 struct tg3_fiber_aneginfo *ap)
3243 {
3244 u16 flowctrl;
3245 unsigned long delta;
3246 u32 rx_cfg_reg;
3247 int ret;
3248
3249 if (ap->state == ANEG_STATE_UNKNOWN) {
3250 ap->rxconfig = 0;
3251 ap->link_time = 0;
3252 ap->cur_time = 0;
3253 ap->ability_match_cfg = 0;
3254 ap->ability_match_count = 0;
3255 ap->ability_match = 0;
3256 ap->idle_match = 0;
3257 ap->ack_match = 0;
3258 }
3259 ap->cur_time++;
3260
3261 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3262 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3263
3264 if (rx_cfg_reg != ap->ability_match_cfg) {
3265 ap->ability_match_cfg = rx_cfg_reg;
3266 ap->ability_match = 0;
3267 ap->ability_match_count = 0;
3268 } else {
3269 if (++ap->ability_match_count > 1) {
3270 ap->ability_match = 1;
3271 ap->ability_match_cfg = rx_cfg_reg;
3272 }
3273 }
3274 if (rx_cfg_reg & ANEG_CFG_ACK)
3275 ap->ack_match = 1;
3276 else
3277 ap->ack_match = 0;
3278
3279 ap->idle_match = 0;
3280 } else {
3281 ap->idle_match = 1;
3282 ap->ability_match_cfg = 0;
3283 ap->ability_match_count = 0;
3284 ap->ability_match = 0;
3285 ap->ack_match = 0;
3286
3287 rx_cfg_reg = 0;
3288 }
3289
3290 ap->rxconfig = rx_cfg_reg;
3291 ret = ANEG_OK;
3292
3293 switch(ap->state) {
3294 case ANEG_STATE_UNKNOWN:
3295 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3296 ap->state = ANEG_STATE_AN_ENABLE;
3297
3298 /* fallthru */
3299 case ANEG_STATE_AN_ENABLE:
3300 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3301 if (ap->flags & MR_AN_ENABLE) {
3302 ap->link_time = 0;
3303 ap->cur_time = 0;
3304 ap->ability_match_cfg = 0;
3305 ap->ability_match_count = 0;
3306 ap->ability_match = 0;
3307 ap->idle_match = 0;
3308 ap->ack_match = 0;
3309
3310 ap->state = ANEG_STATE_RESTART_INIT;
3311 } else {
3312 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3313 }
3314 break;
3315
3316 case ANEG_STATE_RESTART_INIT:
3317 ap->link_time = ap->cur_time;
3318 ap->flags &= ~(MR_NP_LOADED);
3319 ap->txconfig = 0;
3320 tw32(MAC_TX_AUTO_NEG, 0);
3321 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3322 tw32_f(MAC_MODE, tp->mac_mode);
3323 udelay(40);
3324
3325 ret = ANEG_TIMER_ENAB;
3326 ap->state = ANEG_STATE_RESTART;
3327
3328 /* fallthru */
3329 case ANEG_STATE_RESTART:
3330 delta = ap->cur_time - ap->link_time;
3331 if (delta > ANEG_STATE_SETTLE_TIME) {
3332 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3333 } else {
3334 ret = ANEG_TIMER_ENAB;
3335 }
3336 break;
3337
3338 case ANEG_STATE_DISABLE_LINK_OK:
3339 ret = ANEG_DONE;
3340 break;
3341
3342 case ANEG_STATE_ABILITY_DETECT_INIT:
3343 ap->flags &= ~(MR_TOGGLE_TX);
3344 ap->txconfig = ANEG_CFG_FD;
3345 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3346 if (flowctrl & ADVERTISE_1000XPAUSE)
3347 ap->txconfig |= ANEG_CFG_PS1;
3348 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3349 ap->txconfig |= ANEG_CFG_PS2;
3350 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3351 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3352 tw32_f(MAC_MODE, tp->mac_mode);
3353 udelay(40);
3354
3355 ap->state = ANEG_STATE_ABILITY_DETECT;
3356 break;
3357
3358 case ANEG_STATE_ABILITY_DETECT:
3359 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3360 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3361 }
3362 break;
3363
3364 case ANEG_STATE_ACK_DETECT_INIT:
3365 ap->txconfig |= ANEG_CFG_ACK;
3366 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3367 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3368 tw32_f(MAC_MODE, tp->mac_mode);
3369 udelay(40);
3370
3371 ap->state = ANEG_STATE_ACK_DETECT;
3372
3373 /* fallthru */
3374 case ANEG_STATE_ACK_DETECT:
3375 if (ap->ack_match != 0) {
3376 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3377 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3378 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3379 } else {
3380 ap->state = ANEG_STATE_AN_ENABLE;
3381 }
3382 } else if (ap->ability_match != 0 &&
3383 ap->rxconfig == 0) {
3384 ap->state = ANEG_STATE_AN_ENABLE;
3385 }
3386 break;
3387
3388 case ANEG_STATE_COMPLETE_ACK_INIT:
3389 if (ap->rxconfig & ANEG_CFG_INVAL) {
3390 ret = ANEG_FAILED;
3391 break;
3392 }
3393 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3394 MR_LP_ADV_HALF_DUPLEX |
3395 MR_LP_ADV_SYM_PAUSE |
3396 MR_LP_ADV_ASYM_PAUSE |
3397 MR_LP_ADV_REMOTE_FAULT1 |
3398 MR_LP_ADV_REMOTE_FAULT2 |
3399 MR_LP_ADV_NEXT_PAGE |
3400 MR_TOGGLE_RX |
3401 MR_NP_RX);
3402 if (ap->rxconfig & ANEG_CFG_FD)
3403 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3404 if (ap->rxconfig & ANEG_CFG_HD)
3405 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3406 if (ap->rxconfig & ANEG_CFG_PS1)
3407 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3408 if (ap->rxconfig & ANEG_CFG_PS2)
3409 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3410 if (ap->rxconfig & ANEG_CFG_RF1)
3411 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3412 if (ap->rxconfig & ANEG_CFG_RF2)
3413 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3414 if (ap->rxconfig & ANEG_CFG_NP)
3415 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3416
3417 ap->link_time = ap->cur_time;
3418
3419 ap->flags ^= (MR_TOGGLE_TX);
3420 if (ap->rxconfig & 0x0008)
3421 ap->flags |= MR_TOGGLE_RX;
3422 if (ap->rxconfig & ANEG_CFG_NP)
3423 ap->flags |= MR_NP_RX;
3424 ap->flags |= MR_PAGE_RX;
3425
3426 ap->state = ANEG_STATE_COMPLETE_ACK;
3427 ret = ANEG_TIMER_ENAB;
3428 break;
3429
3430 case ANEG_STATE_COMPLETE_ACK:
3431 if (ap->ability_match != 0 &&
3432 ap->rxconfig == 0) {
3433 ap->state = ANEG_STATE_AN_ENABLE;
3434 break;
3435 }
3436 delta = ap->cur_time - ap->link_time;
3437 if (delta > ANEG_STATE_SETTLE_TIME) {
3438 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3439 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3440 } else {
3441 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3442 !(ap->flags & MR_NP_RX)) {
3443 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3444 } else {
3445 ret = ANEG_FAILED;
3446 }
3447 }
3448 }
3449 break;
3450
3451 case ANEG_STATE_IDLE_DETECT_INIT:
3452 ap->link_time = ap->cur_time;
3453 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3454 tw32_f(MAC_MODE, tp->mac_mode);
3455 udelay(40);
3456
3457 ap->state = ANEG_STATE_IDLE_DETECT;
3458 ret = ANEG_TIMER_ENAB;
3459 break;
3460
3461 case ANEG_STATE_IDLE_DETECT:
3462 if (ap->ability_match != 0 &&
3463 ap->rxconfig == 0) {
3464 ap->state = ANEG_STATE_AN_ENABLE;
3465 break;
3466 }
3467 delta = ap->cur_time - ap->link_time;
3468 if (delta > ANEG_STATE_SETTLE_TIME) {
3469 /* XXX another gem from the Broadcom driver :( */
3470 ap->state = ANEG_STATE_LINK_OK;
3471 }
3472 break;
3473
3474 case ANEG_STATE_LINK_OK:
3475 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3476 ret = ANEG_DONE;
3477 break;
3478
3479 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3480 /* ??? unimplemented */
3481 break;
3482
3483 case ANEG_STATE_NEXT_PAGE_WAIT:
3484 /* ??? unimplemented */
3485 break;
3486
3487 default:
3488 ret = ANEG_FAILED;
3489 break;
3490 }
3491
3492 return ret;
3493 }
3494
3495 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3496 {
3497 int res = 0;
3498 struct tg3_fiber_aneginfo aninfo;
3499 int status = ANEG_FAILED;
3500 unsigned int tick;
3501 u32 tmp;
3502
3503 tw32_f(MAC_TX_AUTO_NEG, 0);
3504
3505 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3506 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3507 udelay(40);
3508
3509 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3510 udelay(40);
3511
3512 memset(&aninfo, 0, sizeof(aninfo));
3513 aninfo.flags |= MR_AN_ENABLE;
3514 aninfo.state = ANEG_STATE_UNKNOWN;
3515 aninfo.cur_time = 0;
3516 tick = 0;
3517 while (++tick < 195000) {
3518 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3519 if (status == ANEG_DONE || status == ANEG_FAILED)
3520 break;
3521
3522 udelay(1);
3523 }
3524
3525 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3526 tw32_f(MAC_MODE, tp->mac_mode);
3527 udelay(40);
3528
3529 *txflags = aninfo.txconfig;
3530 *rxflags = aninfo.flags;
3531
3532 if (status == ANEG_DONE &&
3533 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3534 MR_LP_ADV_FULL_DUPLEX)))
3535 res = 1;
3536
3537 return res;
3538 }
3539
3540 static void tg3_init_bcm8002(struct tg3 *tp)
3541 {
3542 u32 mac_status = tr32(MAC_STATUS);
3543 int i;
3544
3545 /* Reset when initting first time or we have a link. */
3546 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3547 !(mac_status & MAC_STATUS_PCS_SYNCED))
3548 return;
3549
3550 /* Set PLL lock range. */
3551 tg3_writephy(tp, 0x16, 0x8007);
3552
3553 /* SW reset */
3554 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3555
3556 /* Wait for reset to complete. */
3557 /* XXX schedule_timeout() ... */
3558 for (i = 0; i < 500; i++)
3559 udelay(10);
3560
3561 /* Config mode; select PMA/Ch 1 regs. */
3562 tg3_writephy(tp, 0x10, 0x8411);
3563
3564 /* Enable auto-lock and comdet, select txclk for tx. */
3565 tg3_writephy(tp, 0x11, 0x0a10);
3566
3567 tg3_writephy(tp, 0x18, 0x00a0);
3568 tg3_writephy(tp, 0x16, 0x41ff);
3569
3570 /* Assert and deassert POR. */
3571 tg3_writephy(tp, 0x13, 0x0400);
3572 udelay(40);
3573 tg3_writephy(tp, 0x13, 0x0000);
3574
3575 tg3_writephy(tp, 0x11, 0x0a50);
3576 udelay(40);
3577 tg3_writephy(tp, 0x11, 0x0a10);
3578
3579 /* Wait for signal to stabilize */
3580 /* XXX schedule_timeout() ... */
3581 for (i = 0; i < 15000; i++)
3582 udelay(10);
3583
3584 /* Deselect the channel register so we can read the PHYID
3585 * later.
3586 */
3587 tg3_writephy(tp, 0x10, 0x8011);
3588 }
3589
3590 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3591 {
3592 u16 flowctrl;
3593 u32 sg_dig_ctrl, sg_dig_status;
3594 u32 serdes_cfg, expected_sg_dig_ctrl;
3595 int workaround, port_a;
3596 int current_link_up;
3597
3598 serdes_cfg = 0;
3599 expected_sg_dig_ctrl = 0;
3600 workaround = 0;
3601 port_a = 1;
3602 current_link_up = 0;
3603
3604 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3605 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3606 workaround = 1;
3607 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3608 port_a = 0;
3609
3610 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3611 /* preserve bits 20-23 for voltage regulator */
3612 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3613 }
3614
3615 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3616
3617 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3618 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3619 if (workaround) {
3620 u32 val = serdes_cfg;
3621
3622 if (port_a)
3623 val |= 0xc010000;
3624 else
3625 val |= 0x4010000;
3626 tw32_f(MAC_SERDES_CFG, val);
3627 }
3628
3629 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3630 }
3631 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3632 tg3_setup_flow_control(tp, 0, 0);
3633 current_link_up = 1;
3634 }
3635 goto out;
3636 }
3637
3638 /* Want auto-negotiation. */
3639 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3640
3641 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3642 if (flowctrl & ADVERTISE_1000XPAUSE)
3643 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3644 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3645 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3646
3647 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3648 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3649 tp->serdes_counter &&
3650 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3651 MAC_STATUS_RCVD_CFG)) ==
3652 MAC_STATUS_PCS_SYNCED)) {
3653 tp->serdes_counter--;
3654 current_link_up = 1;
3655 goto out;
3656 }
3657 restart_autoneg:
3658 if (workaround)
3659 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3660 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3661 udelay(5);
3662 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3663
3664 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3665 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3666 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3667 MAC_STATUS_SIGNAL_DET)) {
3668 sg_dig_status = tr32(SG_DIG_STATUS);
3669 mac_status = tr32(MAC_STATUS);
3670
3671 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3672 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3673 u32 local_adv = 0, remote_adv = 0;
3674
3675 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3676 local_adv |= ADVERTISE_1000XPAUSE;
3677 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3678 local_adv |= ADVERTISE_1000XPSE_ASYM;
3679
3680 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3681 remote_adv |= LPA_1000XPAUSE;
3682 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3683 remote_adv |= LPA_1000XPAUSE_ASYM;
3684
3685 tg3_setup_flow_control(tp, local_adv, remote_adv);
3686 current_link_up = 1;
3687 tp->serdes_counter = 0;
3688 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3689 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3690 if (tp->serdes_counter)
3691 tp->serdes_counter--;
3692 else {
3693 if (workaround) {
3694 u32 val = serdes_cfg;
3695
3696 if (port_a)
3697 val |= 0xc010000;
3698 else
3699 val |= 0x4010000;
3700
3701 tw32_f(MAC_SERDES_CFG, val);
3702 }
3703
3704 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3705 udelay(40);
3706
3707 /* Link parallel detection - link is up */
3708 /* only if we have PCS_SYNC and not */
3709 /* receiving config code words */
3710 mac_status = tr32(MAC_STATUS);
3711 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3712 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3713 tg3_setup_flow_control(tp, 0, 0);
3714 current_link_up = 1;
3715 tp->tg3_flags2 |=
3716 TG3_FLG2_PARALLEL_DETECT;
3717 tp->serdes_counter =
3718 SERDES_PARALLEL_DET_TIMEOUT;
3719 } else
3720 goto restart_autoneg;
3721 }
3722 }
3723 } else {
3724 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3725 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3726 }
3727
3728 out:
3729 return current_link_up;
3730 }
3731
3732 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3733 {
3734 int current_link_up = 0;
3735
3736 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3737 goto out;
3738
3739 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3740 u32 txflags, rxflags;
3741 int i;
3742
3743 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3744 u32 local_adv = 0, remote_adv = 0;
3745
3746 if (txflags & ANEG_CFG_PS1)
3747 local_adv |= ADVERTISE_1000XPAUSE;
3748 if (txflags & ANEG_CFG_PS2)
3749 local_adv |= ADVERTISE_1000XPSE_ASYM;
3750
3751 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3752 remote_adv |= LPA_1000XPAUSE;
3753 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3754 remote_adv |= LPA_1000XPAUSE_ASYM;
3755
3756 tg3_setup_flow_control(tp, local_adv, remote_adv);
3757
3758 current_link_up = 1;
3759 }
3760 for (i = 0; i < 30; i++) {
3761 udelay(20);
3762 tw32_f(MAC_STATUS,
3763 (MAC_STATUS_SYNC_CHANGED |
3764 MAC_STATUS_CFG_CHANGED));
3765 udelay(40);
3766 if ((tr32(MAC_STATUS) &
3767 (MAC_STATUS_SYNC_CHANGED |
3768 MAC_STATUS_CFG_CHANGED)) == 0)
3769 break;
3770 }
3771
3772 mac_status = tr32(MAC_STATUS);
3773 if (current_link_up == 0 &&
3774 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3775 !(mac_status & MAC_STATUS_RCVD_CFG))
3776 current_link_up = 1;
3777 } else {
3778 tg3_setup_flow_control(tp, 0, 0);
3779
3780 /* Forcing 1000FD link up. */
3781 current_link_up = 1;
3782
3783 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3784 udelay(40);
3785
3786 tw32_f(MAC_MODE, tp->mac_mode);
3787 udelay(40);
3788 }
3789
3790 out:
3791 return current_link_up;
3792 }
3793
3794 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3795 {
3796 u32 orig_pause_cfg;
3797 u16 orig_active_speed;
3798 u8 orig_active_duplex;
3799 u32 mac_status;
3800 int current_link_up;
3801 int i;
3802
3803 orig_pause_cfg = tp->link_config.active_flowctrl;
3804 orig_active_speed = tp->link_config.active_speed;
3805 orig_active_duplex = tp->link_config.active_duplex;
3806
3807 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3808 netif_carrier_ok(tp->dev) &&
3809 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3810 mac_status = tr32(MAC_STATUS);
3811 mac_status &= (MAC_STATUS_PCS_SYNCED |
3812 MAC_STATUS_SIGNAL_DET |
3813 MAC_STATUS_CFG_CHANGED |
3814 MAC_STATUS_RCVD_CFG);
3815 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3816 MAC_STATUS_SIGNAL_DET)) {
3817 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3818 MAC_STATUS_CFG_CHANGED));
3819 return 0;
3820 }
3821 }
3822
3823 tw32_f(MAC_TX_AUTO_NEG, 0);
3824
3825 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3826 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3827 tw32_f(MAC_MODE, tp->mac_mode);
3828 udelay(40);
3829
3830 if (tp->phy_id == PHY_ID_BCM8002)
3831 tg3_init_bcm8002(tp);
3832
3833 /* Enable link change event even when serdes polling. */
3834 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3835 udelay(40);
3836
3837 current_link_up = 0;
3838 mac_status = tr32(MAC_STATUS);
3839
3840 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3841 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3842 else
3843 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3844
3845 tp->hw_status->status =
3846 (SD_STATUS_UPDATED |
3847 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3848
3849 for (i = 0; i < 100; i++) {
3850 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3851 MAC_STATUS_CFG_CHANGED));
3852 udelay(5);
3853 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3854 MAC_STATUS_CFG_CHANGED |
3855 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3856 break;
3857 }
3858
3859 mac_status = tr32(MAC_STATUS);
3860 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3861 current_link_up = 0;
3862 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3863 tp->serdes_counter == 0) {
3864 tw32_f(MAC_MODE, (tp->mac_mode |
3865 MAC_MODE_SEND_CONFIGS));
3866 udelay(1);
3867 tw32_f(MAC_MODE, tp->mac_mode);
3868 }
3869 }
3870
3871 if (current_link_up == 1) {
3872 tp->link_config.active_speed = SPEED_1000;
3873 tp->link_config.active_duplex = DUPLEX_FULL;
3874 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3875 LED_CTRL_LNKLED_OVERRIDE |
3876 LED_CTRL_1000MBPS_ON));
3877 } else {
3878 tp->link_config.active_speed = SPEED_INVALID;
3879 tp->link_config.active_duplex = DUPLEX_INVALID;
3880 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3881 LED_CTRL_LNKLED_OVERRIDE |
3882 LED_CTRL_TRAFFIC_OVERRIDE));
3883 }
3884
3885 if (current_link_up != netif_carrier_ok(tp->dev)) {
3886 if (current_link_up)
3887 netif_carrier_on(tp->dev);
3888 else
3889 netif_carrier_off(tp->dev);
3890 tg3_link_report(tp);
3891 } else {
3892 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3893 if (orig_pause_cfg != now_pause_cfg ||
3894 orig_active_speed != tp->link_config.active_speed ||
3895 orig_active_duplex != tp->link_config.active_duplex)
3896 tg3_link_report(tp);
3897 }
3898
3899 return 0;
3900 }
3901
3902 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3903 {
3904 int current_link_up, err = 0;
3905 u32 bmsr, bmcr;
3906 u16 current_speed;
3907 u8 current_duplex;
3908 u32 local_adv, remote_adv;
3909
3910 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3911 tw32_f(MAC_MODE, tp->mac_mode);
3912 udelay(40);
3913
3914 tw32(MAC_EVENT, 0);
3915
3916 tw32_f(MAC_STATUS,
3917 (MAC_STATUS_SYNC_CHANGED |
3918 MAC_STATUS_CFG_CHANGED |
3919 MAC_STATUS_MI_COMPLETION |
3920 MAC_STATUS_LNKSTATE_CHANGED));
3921 udelay(40);
3922
3923 if (force_reset)
3924 tg3_phy_reset(tp);
3925
3926 current_link_up = 0;
3927 current_speed = SPEED_INVALID;
3928 current_duplex = DUPLEX_INVALID;
3929
3930 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3931 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3932 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3933 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3934 bmsr |= BMSR_LSTATUS;
3935 else
3936 bmsr &= ~BMSR_LSTATUS;
3937 }
3938
3939 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3940
3941 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3942 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3943 /* do nothing, just check for link up at the end */
3944 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3945 u32 adv, new_adv;
3946
3947 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3948 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3949 ADVERTISE_1000XPAUSE |
3950 ADVERTISE_1000XPSE_ASYM |
3951 ADVERTISE_SLCT);
3952
3953 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3954
3955 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3956 new_adv |= ADVERTISE_1000XHALF;
3957 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3958 new_adv |= ADVERTISE_1000XFULL;
3959
3960 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3961 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3962 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3963 tg3_writephy(tp, MII_BMCR, bmcr);
3964
3965 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3966 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3967 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3968
3969 return err;
3970 }
3971 } else {
3972 u32 new_bmcr;
3973
3974 bmcr &= ~BMCR_SPEED1000;
3975 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3976
3977 if (tp->link_config.duplex == DUPLEX_FULL)
3978 new_bmcr |= BMCR_FULLDPLX;
3979
3980 if (new_bmcr != bmcr) {
3981 /* BMCR_SPEED1000 is a reserved bit that needs
3982 * to be set on write.
3983 */
3984 new_bmcr |= BMCR_SPEED1000;
3985
3986 /* Force a linkdown */
3987 if (netif_carrier_ok(tp->dev)) {
3988 u32 adv;
3989
3990 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3991 adv &= ~(ADVERTISE_1000XFULL |
3992 ADVERTISE_1000XHALF |
3993 ADVERTISE_SLCT);
3994 tg3_writephy(tp, MII_ADVERTISE, adv);
3995 tg3_writephy(tp, MII_BMCR, bmcr |
3996 BMCR_ANRESTART |
3997 BMCR_ANENABLE);
3998 udelay(10);
3999 netif_carrier_off(tp->dev);
4000 }
4001 tg3_writephy(tp, MII_BMCR, new_bmcr);
4002 bmcr = new_bmcr;
4003 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4004 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4005 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4006 ASIC_REV_5714) {
4007 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4008 bmsr |= BMSR_LSTATUS;
4009 else
4010 bmsr &= ~BMSR_LSTATUS;
4011 }
4012 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4013 }
4014 }
4015
4016 if (bmsr & BMSR_LSTATUS) {
4017 current_speed = SPEED_1000;
4018 current_link_up = 1;
4019 if (bmcr & BMCR_FULLDPLX)
4020 current_duplex = DUPLEX_FULL;
4021 else
4022 current_duplex = DUPLEX_HALF;
4023
4024 local_adv = 0;
4025 remote_adv = 0;
4026
4027 if (bmcr & BMCR_ANENABLE) {
4028 u32 common;
4029
4030 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4031 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4032 common = local_adv & remote_adv;
4033 if (common & (ADVERTISE_1000XHALF |
4034 ADVERTISE_1000XFULL)) {
4035 if (common & ADVERTISE_1000XFULL)
4036 current_duplex = DUPLEX_FULL;
4037 else
4038 current_duplex = DUPLEX_HALF;
4039 }
4040 else
4041 current_link_up = 0;
4042 }
4043 }
4044
4045 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4046 tg3_setup_flow_control(tp, local_adv, remote_adv);
4047
4048 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4049 if (tp->link_config.active_duplex == DUPLEX_HALF)
4050 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4051
4052 tw32_f(MAC_MODE, tp->mac_mode);
4053 udelay(40);
4054
4055 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4056
4057 tp->link_config.active_speed = current_speed;
4058 tp->link_config.active_duplex = current_duplex;
4059
4060 if (current_link_up != netif_carrier_ok(tp->dev)) {
4061 if (current_link_up)
4062 netif_carrier_on(tp->dev);
4063 else {
4064 netif_carrier_off(tp->dev);
4065 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4066 }
4067 tg3_link_report(tp);
4068 }
4069 return err;
4070 }
4071
4072 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4073 {
4074 if (tp->serdes_counter) {
4075 /* Give autoneg time to complete. */
4076 tp->serdes_counter--;
4077 return;
4078 }
4079 if (!netif_carrier_ok(tp->dev) &&
4080 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4081 u32 bmcr;
4082
4083 tg3_readphy(tp, MII_BMCR, &bmcr);
4084 if (bmcr & BMCR_ANENABLE) {
4085 u32 phy1, phy2;
4086
4087 /* Select shadow register 0x1f */
4088 tg3_writephy(tp, 0x1c, 0x7c00);
4089 tg3_readphy(tp, 0x1c, &phy1);
4090
4091 /* Select expansion interrupt status register */
4092 tg3_writephy(tp, 0x17, 0x0f01);
4093 tg3_readphy(tp, 0x15, &phy2);
4094 tg3_readphy(tp, 0x15, &phy2);
4095
4096 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4097 /* We have signal detect and not receiving
4098 * config code words, link is up by parallel
4099 * detection.
4100 */
4101
4102 bmcr &= ~BMCR_ANENABLE;
4103 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4104 tg3_writephy(tp, MII_BMCR, bmcr);
4105 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4106 }
4107 }
4108 }
4109 else if (netif_carrier_ok(tp->dev) &&
4110 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4111 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4112 u32 phy2;
4113
4114 /* Select expansion interrupt status register */
4115 tg3_writephy(tp, 0x17, 0x0f01);
4116 tg3_readphy(tp, 0x15, &phy2);
4117 if (phy2 & 0x20) {
4118 u32 bmcr;
4119
4120 /* Config code words received, turn on autoneg. */
4121 tg3_readphy(tp, MII_BMCR, &bmcr);
4122 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4123
4124 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4125
4126 }
4127 }
4128 }
4129
4130 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4131 {
4132 int err;
4133
4134 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4135 err = tg3_setup_fiber_phy(tp, force_reset);
4136 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4137 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4138 } else {
4139 err = tg3_setup_copper_phy(tp, force_reset);
4140 }
4141
4142 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4143 u32 val, scale;
4144
4145 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4146 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4147 scale = 65;
4148 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4149 scale = 6;
4150 else
4151 scale = 12;
4152
4153 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4154 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4155 tw32(GRC_MISC_CFG, val);
4156 }
4157
4158 if (tp->link_config.active_speed == SPEED_1000 &&
4159 tp->link_config.active_duplex == DUPLEX_HALF)
4160 tw32(MAC_TX_LENGTHS,
4161 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4162 (6 << TX_LENGTHS_IPG_SHIFT) |
4163 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4164 else
4165 tw32(MAC_TX_LENGTHS,
4166 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4167 (6 << TX_LENGTHS_IPG_SHIFT) |
4168 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4169
4170 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4171 if (netif_carrier_ok(tp->dev)) {
4172 tw32(HOSTCC_STAT_COAL_TICKS,
4173 tp->coal.stats_block_coalesce_usecs);
4174 } else {
4175 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4176 }
4177 }
4178
4179 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4180 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4181 if (!netif_carrier_ok(tp->dev))
4182 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4183 tp->pwrmgmt_thresh;
4184 else
4185 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4186 tw32(PCIE_PWR_MGMT_THRESH, val);
4187 }
4188
4189 return err;
4190 }
4191
4192 /* This is called whenever we suspect that the system chipset is re-
4193 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4194 * is bogus tx completions. We try to recover by setting the
4195 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4196 * in the workqueue.
4197 */
4198 static void tg3_tx_recover(struct tg3 *tp)
4199 {
4200 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4201 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4202
4203 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4204 "mapped I/O cycles to the network device, attempting to "
4205 "recover. Please report the problem to the driver maintainer "
4206 "and include system chipset information.\n", tp->dev->name);
4207
4208 spin_lock(&tp->lock);
4209 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4210 spin_unlock(&tp->lock);
4211 }
4212
4213 static inline u32 tg3_tx_avail(struct tg3 *tp)
4214 {
4215 smp_mb();
4216 return (tp->tx_pending -
4217 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4218 }
4219
4220 /* Tigon3 never reports partial packet sends. So we do not
4221 * need special logic to handle SKBs that have not had all
4222 * of their frags sent yet, like SunGEM does.
4223 */
4224 static void tg3_tx(struct tg3 *tp)
4225 {
4226 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4227 u32 sw_idx = tp->tx_cons;
4228
4229 while (sw_idx != hw_idx) {
4230 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4231 struct sk_buff *skb = ri->skb;
4232 int i, tx_bug = 0;
4233
4234 if (unlikely(skb == NULL)) {
4235 tg3_tx_recover(tp);
4236 return;
4237 }
4238
4239 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4240
4241 ri->skb = NULL;
4242
4243 sw_idx = NEXT_TX(sw_idx);
4244
4245 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4246 ri = &tp->tx_buffers[sw_idx];
4247 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4248 tx_bug = 1;
4249 sw_idx = NEXT_TX(sw_idx);
4250 }
4251
4252 dev_kfree_skb(skb);
4253
4254 if (unlikely(tx_bug)) {
4255 tg3_tx_recover(tp);
4256 return;
4257 }
4258 }
4259
4260 tp->tx_cons = sw_idx;
4261
4262 /* Need to make the tx_cons update visible to tg3_start_xmit()
4263 * before checking for netif_queue_stopped(). Without the
4264 * memory barrier, there is a small possibility that tg3_start_xmit()
4265 * will miss it and cause the queue to be stopped forever.
4266 */
4267 smp_mb();
4268
4269 if (unlikely(netif_queue_stopped(tp->dev) &&
4270 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4271 netif_tx_lock(tp->dev);
4272 if (netif_queue_stopped(tp->dev) &&
4273 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4274 netif_wake_queue(tp->dev);
4275 netif_tx_unlock(tp->dev);
4276 }
4277 }
4278
4279 /* Returns size of skb allocated or < 0 on error.
4280 *
4281 * We only need to fill in the address because the other members
4282 * of the RX descriptor are invariant, see tg3_init_rings.
4283 *
4284 * Note the purposeful assymetry of cpu vs. chip accesses. For
4285 * posting buffers we only dirty the first cache line of the RX
4286 * descriptor (containing the address). Whereas for the RX status
4287 * buffers the cpu only reads the last cacheline of the RX descriptor
4288 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4289 */
4290 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4291 int src_idx, u32 dest_idx_unmasked)
4292 {
4293 struct tg3_rx_buffer_desc *desc;
4294 struct ring_info *map, *src_map;
4295 struct sk_buff *skb;
4296 dma_addr_t mapping;
4297 int skb_size, dest_idx;
4298
4299 src_map = NULL;
4300 switch (opaque_key) {
4301 case RXD_OPAQUE_RING_STD:
4302 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4303 desc = &tp->rx_std[dest_idx];
4304 map = &tp->rx_std_buffers[dest_idx];
4305 if (src_idx >= 0)
4306 src_map = &tp->rx_std_buffers[src_idx];
4307 skb_size = tp->rx_pkt_buf_sz;
4308 break;
4309
4310 case RXD_OPAQUE_RING_JUMBO:
4311 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4312 desc = &tp->rx_jumbo[dest_idx];
4313 map = &tp->rx_jumbo_buffers[dest_idx];
4314 if (src_idx >= 0)
4315 src_map = &tp->rx_jumbo_buffers[src_idx];
4316 skb_size = RX_JUMBO_PKT_BUF_SZ;
4317 break;
4318
4319 default:
4320 return -EINVAL;
4321 }
4322
4323 /* Do not overwrite any of the map or rp information
4324 * until we are sure we can commit to a new buffer.
4325 *
4326 * Callers depend upon this behavior and assume that
4327 * we leave everything unchanged if we fail.
4328 */
4329 skb = netdev_alloc_skb(tp->dev, skb_size);
4330 if (skb == NULL)
4331 return -ENOMEM;
4332
4333 skb_reserve(skb, tp->rx_offset);
4334
4335 mapping = pci_map_single(tp->pdev, skb->data,
4336 skb_size - tp->rx_offset,
4337 PCI_DMA_FROMDEVICE);
4338
4339 map->skb = skb;
4340 pci_unmap_addr_set(map, mapping, mapping);
4341
4342 if (src_map != NULL)
4343 src_map->skb = NULL;
4344
4345 desc->addr_hi = ((u64)mapping >> 32);
4346 desc->addr_lo = ((u64)mapping & 0xffffffff);
4347
4348 return skb_size;
4349 }
4350
4351 /* We only need to move over in the address because the other
4352 * members of the RX descriptor are invariant. See notes above
4353 * tg3_alloc_rx_skb for full details.
4354 */
4355 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4356 int src_idx, u32 dest_idx_unmasked)
4357 {
4358 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4359 struct ring_info *src_map, *dest_map;
4360 int dest_idx;
4361
4362 switch (opaque_key) {
4363 case RXD_OPAQUE_RING_STD:
4364 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4365 dest_desc = &tp->rx_std[dest_idx];
4366 dest_map = &tp->rx_std_buffers[dest_idx];
4367 src_desc = &tp->rx_std[src_idx];
4368 src_map = &tp->rx_std_buffers[src_idx];
4369 break;
4370
4371 case RXD_OPAQUE_RING_JUMBO:
4372 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4373 dest_desc = &tp->rx_jumbo[dest_idx];
4374 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4375 src_desc = &tp->rx_jumbo[src_idx];
4376 src_map = &tp->rx_jumbo_buffers[src_idx];
4377 break;
4378
4379 default:
4380 return;
4381 }
4382
4383 dest_map->skb = src_map->skb;
4384 pci_unmap_addr_set(dest_map, mapping,
4385 pci_unmap_addr(src_map, mapping));
4386 dest_desc->addr_hi = src_desc->addr_hi;
4387 dest_desc->addr_lo = src_desc->addr_lo;
4388
4389 src_map->skb = NULL;
4390 }
4391
4392 #if TG3_VLAN_TAG_USED
4393 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4394 {
4395 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4396 }
4397 #endif
4398
4399 /* The RX ring scheme is composed of multiple rings which post fresh
4400 * buffers to the chip, and one special ring the chip uses to report
4401 * status back to the host.
4402 *
4403 * The special ring reports the status of received packets to the
4404 * host. The chip does not write into the original descriptor the
4405 * RX buffer was obtained from. The chip simply takes the original
4406 * descriptor as provided by the host, updates the status and length
4407 * field, then writes this into the next status ring entry.
4408 *
4409 * Each ring the host uses to post buffers to the chip is described
4410 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4411 * it is first placed into the on-chip ram. When the packet's length
4412 * is known, it walks down the TG3_BDINFO entries to select the ring.
4413 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4414 * which is within the range of the new packet's length is chosen.
4415 *
4416 * The "separate ring for rx status" scheme may sound queer, but it makes
4417 * sense from a cache coherency perspective. If only the host writes
4418 * to the buffer post rings, and only the chip writes to the rx status
4419 * rings, then cache lines never move beyond shared-modified state.
4420 * If both the host and chip were to write into the same ring, cache line
4421 * eviction could occur since both entities want it in an exclusive state.
4422 */
4423 static int tg3_rx(struct tg3 *tp, int budget)
4424 {
4425 u32 work_mask, rx_std_posted = 0;
4426 u32 sw_idx = tp->rx_rcb_ptr;
4427 u16 hw_idx;
4428 int received;
4429
4430 hw_idx = tp->hw_status->idx[0].rx_producer;
4431 /*
4432 * We need to order the read of hw_idx and the read of
4433 * the opaque cookie.
4434 */
4435 rmb();
4436 work_mask = 0;
4437 received = 0;
4438 while (sw_idx != hw_idx && budget > 0) {
4439 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4440 unsigned int len;
4441 struct sk_buff *skb;
4442 dma_addr_t dma_addr;
4443 u32 opaque_key, desc_idx, *post_ptr;
4444
4445 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4446 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4447 if (opaque_key == RXD_OPAQUE_RING_STD) {
4448 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4449 mapping);
4450 skb = tp->rx_std_buffers[desc_idx].skb;
4451 post_ptr = &tp->rx_std_ptr;
4452 rx_std_posted++;
4453 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4454 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4455 mapping);
4456 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4457 post_ptr = &tp->rx_jumbo_ptr;
4458 }
4459 else {
4460 goto next_pkt_nopost;
4461 }
4462
4463 work_mask |= opaque_key;
4464
4465 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4466 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4467 drop_it:
4468 tg3_recycle_rx(tp, opaque_key,
4469 desc_idx, *post_ptr);
4470 drop_it_no_recycle:
4471 /* Other statistics kept track of by card. */
4472 tp->net_stats.rx_dropped++;
4473 goto next_pkt;
4474 }
4475
4476 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4477 ETH_FCS_LEN;
4478
4479 if (len > RX_COPY_THRESHOLD
4480 && tp->rx_offset == NET_IP_ALIGN
4481 /* rx_offset will likely not equal NET_IP_ALIGN
4482 * if this is a 5701 card running in PCI-X mode
4483 * [see tg3_get_invariants()]
4484 */
4485 ) {
4486 int skb_size;
4487
4488 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4489 desc_idx, *post_ptr);
4490 if (skb_size < 0)
4491 goto drop_it;
4492
4493 pci_unmap_single(tp->pdev, dma_addr,
4494 skb_size - tp->rx_offset,
4495 PCI_DMA_FROMDEVICE);
4496
4497 skb_put(skb, len);
4498 } else {
4499 struct sk_buff *copy_skb;
4500
4501 tg3_recycle_rx(tp, opaque_key,
4502 desc_idx, *post_ptr);
4503
4504 copy_skb = netdev_alloc_skb(tp->dev,
4505 len + TG3_RAW_IP_ALIGN);
4506 if (copy_skb == NULL)
4507 goto drop_it_no_recycle;
4508
4509 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4510 skb_put(copy_skb, len);
4511 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4512 skb_copy_from_linear_data(skb, copy_skb->data, len);
4513 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4514
4515 /* We'll reuse the original ring buffer. */
4516 skb = copy_skb;
4517 }
4518
4519 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4520 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4521 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4522 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4523 skb->ip_summed = CHECKSUM_UNNECESSARY;
4524 else
4525 skb->ip_summed = CHECKSUM_NONE;
4526
4527 skb->protocol = eth_type_trans(skb, tp->dev);
4528
4529 if (len > (tp->dev->mtu + ETH_HLEN) &&
4530 skb->protocol != htons(ETH_P_8021Q)) {
4531 dev_kfree_skb(skb);
4532 goto next_pkt;
4533 }
4534
4535 #if TG3_VLAN_TAG_USED
4536 if (tp->vlgrp != NULL &&
4537 desc->type_flags & RXD_FLAG_VLAN) {
4538 tg3_vlan_rx(tp, skb,
4539 desc->err_vlan & RXD_VLAN_MASK);
4540 } else
4541 #endif
4542 netif_receive_skb(skb);
4543
4544 received++;
4545 budget--;
4546
4547 next_pkt:
4548 (*post_ptr)++;
4549
4550 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4551 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4552
4553 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4554 TG3_64BIT_REG_LOW, idx);
4555 work_mask &= ~RXD_OPAQUE_RING_STD;
4556 rx_std_posted = 0;
4557 }
4558 next_pkt_nopost:
4559 sw_idx++;
4560 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4561
4562 /* Refresh hw_idx to see if there is new work */
4563 if (sw_idx == hw_idx) {
4564 hw_idx = tp->hw_status->idx[0].rx_producer;
4565 rmb();
4566 }
4567 }
4568
4569 /* ACK the status ring. */
4570 tp->rx_rcb_ptr = sw_idx;
4571 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4572
4573 /* Refill RX ring(s). */
4574 if (work_mask & RXD_OPAQUE_RING_STD) {
4575 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4576 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4577 sw_idx);
4578 }
4579 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4580 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4581 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4582 sw_idx);
4583 }
4584 mmiowb();
4585
4586 return received;
4587 }
4588
4589 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4590 {
4591 struct tg3_hw_status *sblk = tp->hw_status;
4592
4593 /* handle link change and other phy events */
4594 if (!(tp->tg3_flags &
4595 (TG3_FLAG_USE_LINKCHG_REG |
4596 TG3_FLAG_POLL_SERDES))) {
4597 if (sblk->status & SD_STATUS_LINK_CHG) {
4598 sblk->status = SD_STATUS_UPDATED |
4599 (sblk->status & ~SD_STATUS_LINK_CHG);
4600 spin_lock(&tp->lock);
4601 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4602 tw32_f(MAC_STATUS,
4603 (MAC_STATUS_SYNC_CHANGED |
4604 MAC_STATUS_CFG_CHANGED |
4605 MAC_STATUS_MI_COMPLETION |
4606 MAC_STATUS_LNKSTATE_CHANGED));
4607 udelay(40);
4608 } else
4609 tg3_setup_phy(tp, 0);
4610 spin_unlock(&tp->lock);
4611 }
4612 }
4613
4614 /* run TX completion thread */
4615 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4616 tg3_tx(tp);
4617 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4618 return work_done;
4619 }
4620
4621 /* run RX thread, within the bounds set by NAPI.
4622 * All RX "locking" is done by ensuring outside
4623 * code synchronizes with tg3->napi.poll()
4624 */
4625 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4626 work_done += tg3_rx(tp, budget - work_done);
4627
4628 return work_done;
4629 }
4630
4631 static int tg3_poll(struct napi_struct *napi, int budget)
4632 {
4633 struct tg3 *tp = container_of(napi, struct tg3, napi);
4634 int work_done = 0;
4635 struct tg3_hw_status *sblk = tp->hw_status;
4636
4637 while (1) {
4638 work_done = tg3_poll_work(tp, work_done, budget);
4639
4640 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4641 goto tx_recovery;
4642
4643 if (unlikely(work_done >= budget))
4644 break;
4645
4646 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4647 /* tp->last_tag is used in tg3_restart_ints() below
4648 * to tell the hw how much work has been processed,
4649 * so we must read it before checking for more work.
4650 */
4651 tp->last_tag = sblk->status_tag;
4652 rmb();
4653 } else
4654 sblk->status &= ~SD_STATUS_UPDATED;
4655
4656 if (likely(!tg3_has_work(tp))) {
4657 napi_complete(napi);
4658 tg3_restart_ints(tp);
4659 break;
4660 }
4661 }
4662
4663 return work_done;
4664
4665 tx_recovery:
4666 /* work_done is guaranteed to be less than budget. */
4667 napi_complete(napi);
4668 schedule_work(&tp->reset_task);
4669 return work_done;
4670 }
4671
4672 static void tg3_irq_quiesce(struct tg3 *tp)
4673 {
4674 BUG_ON(tp->irq_sync);
4675
4676 tp->irq_sync = 1;
4677 smp_mb();
4678
4679 synchronize_irq(tp->pdev->irq);
4680 }
4681
4682 static inline int tg3_irq_sync(struct tg3 *tp)
4683 {
4684 return tp->irq_sync;
4685 }
4686
4687 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4688 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4689 * with as well. Most of the time, this is not necessary except when
4690 * shutting down the device.
4691 */
4692 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4693 {
4694 spin_lock_bh(&tp->lock);
4695 if (irq_sync)
4696 tg3_irq_quiesce(tp);
4697 }
4698
4699 static inline void tg3_full_unlock(struct tg3 *tp)
4700 {
4701 spin_unlock_bh(&tp->lock);
4702 }
4703
4704 /* One-shot MSI handler - Chip automatically disables interrupt
4705 * after sending MSI so driver doesn't have to do it.
4706 */
4707 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4708 {
4709 struct net_device *dev = dev_id;
4710 struct tg3 *tp = netdev_priv(dev);
4711
4712 prefetch(tp->hw_status);
4713 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4714
4715 if (likely(!tg3_irq_sync(tp)))
4716 napi_schedule(&tp->napi);
4717
4718 return IRQ_HANDLED;
4719 }
4720
4721 /* MSI ISR - No need to check for interrupt sharing and no need to
4722 * flush status block and interrupt mailbox. PCI ordering rules
4723 * guarantee that MSI will arrive after the status block.
4724 */
4725 static irqreturn_t tg3_msi(int irq, void *dev_id)
4726 {
4727 struct net_device *dev = dev_id;
4728 struct tg3 *tp = netdev_priv(dev);
4729
4730 prefetch(tp->hw_status);
4731 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4732 /*
4733 * Writing any value to intr-mbox-0 clears PCI INTA# and
4734 * chip-internal interrupt pending events.
4735 * Writing non-zero to intr-mbox-0 additional tells the
4736 * NIC to stop sending us irqs, engaging "in-intr-handler"
4737 * event coalescing.
4738 */
4739 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4740 if (likely(!tg3_irq_sync(tp)))
4741 napi_schedule(&tp->napi);
4742
4743 return IRQ_RETVAL(1);
4744 }
4745
4746 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4747 {
4748 struct net_device *dev = dev_id;
4749 struct tg3 *tp = netdev_priv(dev);
4750 struct tg3_hw_status *sblk = tp->hw_status;
4751 unsigned int handled = 1;
4752
4753 /* In INTx mode, it is possible for the interrupt to arrive at
4754 * the CPU before the status block posted prior to the interrupt.
4755 * Reading the PCI State register will confirm whether the
4756 * interrupt is ours and will flush the status block.
4757 */
4758 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4759 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4760 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4761 handled = 0;
4762 goto out;
4763 }
4764 }
4765
4766 /*
4767 * Writing any value to intr-mbox-0 clears PCI INTA# and
4768 * chip-internal interrupt pending events.
4769 * Writing non-zero to intr-mbox-0 additional tells the
4770 * NIC to stop sending us irqs, engaging "in-intr-handler"
4771 * event coalescing.
4772 *
4773 * Flush the mailbox to de-assert the IRQ immediately to prevent
4774 * spurious interrupts. The flush impacts performance but
4775 * excessive spurious interrupts can be worse in some cases.
4776 */
4777 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4778 if (tg3_irq_sync(tp))
4779 goto out;
4780 sblk->status &= ~SD_STATUS_UPDATED;
4781 if (likely(tg3_has_work(tp))) {
4782 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4783 napi_schedule(&tp->napi);
4784 } else {
4785 /* No work, shared interrupt perhaps? re-enable
4786 * interrupts, and flush that PCI write
4787 */
4788 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4789 0x00000000);
4790 }
4791 out:
4792 return IRQ_RETVAL(handled);
4793 }
4794
4795 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4796 {
4797 struct net_device *dev = dev_id;
4798 struct tg3 *tp = netdev_priv(dev);
4799 struct tg3_hw_status *sblk = tp->hw_status;
4800 unsigned int handled = 1;
4801
4802 /* In INTx mode, it is possible for the interrupt to arrive at
4803 * the CPU before the status block posted prior to the interrupt.
4804 * Reading the PCI State register will confirm whether the
4805 * interrupt is ours and will flush the status block.
4806 */
4807 if (unlikely(sblk->status_tag == tp->last_tag)) {
4808 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4809 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4810 handled = 0;
4811 goto out;
4812 }
4813 }
4814
4815 /*
4816 * writing any value to intr-mbox-0 clears PCI INTA# and
4817 * chip-internal interrupt pending events.
4818 * writing non-zero to intr-mbox-0 additional tells the
4819 * NIC to stop sending us irqs, engaging "in-intr-handler"
4820 * event coalescing.
4821 *
4822 * Flush the mailbox to de-assert the IRQ immediately to prevent
4823 * spurious interrupts. The flush impacts performance but
4824 * excessive spurious interrupts can be worse in some cases.
4825 */
4826 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4827 if (tg3_irq_sync(tp))
4828 goto out;
4829 if (napi_schedule_prep(&tp->napi)) {
4830 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4831 /* Update last_tag to mark that this status has been
4832 * seen. Because interrupt may be shared, we may be
4833 * racing with tg3_poll(), so only update last_tag
4834 * if tg3_poll() is not scheduled.
4835 */
4836 tp->last_tag = sblk->status_tag;
4837 __napi_schedule(&tp->napi);
4838 }
4839 out:
4840 return IRQ_RETVAL(handled);
4841 }
4842
4843 /* ISR for interrupt test */
4844 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4845 {
4846 struct net_device *dev = dev_id;
4847 struct tg3 *tp = netdev_priv(dev);
4848 struct tg3_hw_status *sblk = tp->hw_status;
4849
4850 if ((sblk->status & SD_STATUS_UPDATED) ||
4851 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4852 tg3_disable_ints(tp);
4853 return IRQ_RETVAL(1);
4854 }
4855 return IRQ_RETVAL(0);
4856 }
4857
4858 static int tg3_init_hw(struct tg3 *, int);
4859 static int tg3_halt(struct tg3 *, int, int);
4860
4861 /* Restart hardware after configuration changes, self-test, etc.
4862 * Invoked with tp->lock held.
4863 */
4864 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4865 __releases(tp->lock)
4866 __acquires(tp->lock)
4867 {
4868 int err;
4869
4870 err = tg3_init_hw(tp, reset_phy);
4871 if (err) {
4872 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4873 "aborting.\n", tp->dev->name);
4874 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4875 tg3_full_unlock(tp);
4876 del_timer_sync(&tp->timer);
4877 tp->irq_sync = 0;
4878 napi_enable(&tp->napi);
4879 dev_close(tp->dev);
4880 tg3_full_lock(tp, 0);
4881 }
4882 return err;
4883 }
4884
4885 #ifdef CONFIG_NET_POLL_CONTROLLER
4886 static void tg3_poll_controller(struct net_device *dev)
4887 {
4888 struct tg3 *tp = netdev_priv(dev);
4889
4890 tg3_interrupt(tp->pdev->irq, dev);
4891 }
4892 #endif
4893
4894 static void tg3_reset_task(struct work_struct *work)
4895 {
4896 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4897 int err;
4898 unsigned int restart_timer;
4899
4900 tg3_full_lock(tp, 0);
4901
4902 if (!netif_running(tp->dev)) {
4903 tg3_full_unlock(tp);
4904 return;
4905 }
4906
4907 tg3_full_unlock(tp);
4908
4909 tg3_phy_stop(tp);
4910
4911 tg3_netif_stop(tp);
4912
4913 tg3_full_lock(tp, 1);
4914
4915 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4916 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4917
4918 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4919 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4920 tp->write32_rx_mbox = tg3_write_flush_reg32;
4921 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4922 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4923 }
4924
4925 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4926 err = tg3_init_hw(tp, 1);
4927 if (err)
4928 goto out;
4929
4930 tg3_netif_start(tp);
4931
4932 if (restart_timer)
4933 mod_timer(&tp->timer, jiffies + 1);
4934
4935 out:
4936 tg3_full_unlock(tp);
4937
4938 if (!err)
4939 tg3_phy_start(tp);
4940 }
4941
4942 static void tg3_dump_short_state(struct tg3 *tp)
4943 {
4944 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4945 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4946 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4947 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4948 }
4949
4950 static void tg3_tx_timeout(struct net_device *dev)
4951 {
4952 struct tg3 *tp = netdev_priv(dev);
4953
4954 if (netif_msg_tx_err(tp)) {
4955 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4956 dev->name);
4957 tg3_dump_short_state(tp);
4958 }
4959
4960 schedule_work(&tp->reset_task);
4961 }
4962
4963 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4964 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4965 {
4966 u32 base = (u32) mapping & 0xffffffff;
4967
4968 return ((base > 0xffffdcc0) &&
4969 (base + len + 8 < base));
4970 }
4971
4972 /* Test for DMA addresses > 40-bit */
4973 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4974 int len)
4975 {
4976 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4977 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4978 return (((u64) mapping + len) > DMA_40BIT_MASK);
4979 return 0;
4980 #else
4981 return 0;
4982 #endif
4983 }
4984
4985 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4986
4987 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4988 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4989 u32 last_plus_one, u32 *start,
4990 u32 base_flags, u32 mss)
4991 {
4992 struct sk_buff *new_skb;
4993 dma_addr_t new_addr = 0;
4994 u32 entry = *start;
4995 int i, ret = 0;
4996
4997 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4998 new_skb = skb_copy(skb, GFP_ATOMIC);
4999 else {
5000 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5001
5002 new_skb = skb_copy_expand(skb,
5003 skb_headroom(skb) + more_headroom,
5004 skb_tailroom(skb), GFP_ATOMIC);
5005 }
5006
5007 if (!new_skb) {
5008 ret = -1;
5009 } else {
5010 /* New SKB is guaranteed to be linear. */
5011 entry = *start;
5012 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5013 new_addr = skb_shinfo(new_skb)->dma_maps[0];
5014
5015 /* Make sure new skb does not cross any 4G boundaries.
5016 * Drop the packet if it does.
5017 */
5018 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5019 if (!ret)
5020 skb_dma_unmap(&tp->pdev->dev, new_skb,
5021 DMA_TO_DEVICE);
5022 ret = -1;
5023 dev_kfree_skb(new_skb);
5024 new_skb = NULL;
5025 } else {
5026 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5027 base_flags, 1 | (mss << 1));
5028 *start = NEXT_TX(entry);
5029 }
5030 }
5031
5032 /* Now clean up the sw ring entries. */
5033 i = 0;
5034 while (entry != last_plus_one) {
5035 if (i == 0) {
5036 tp->tx_buffers[entry].skb = new_skb;
5037 } else {
5038 tp->tx_buffers[entry].skb = NULL;
5039 }
5040 entry = NEXT_TX(entry);
5041 i++;
5042 }
5043
5044 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5045 dev_kfree_skb(skb);
5046
5047 return ret;
5048 }
5049
5050 static void tg3_set_txd(struct tg3 *tp, int entry,
5051 dma_addr_t mapping, int len, u32 flags,
5052 u32 mss_and_is_end)
5053 {
5054 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5055 int is_end = (mss_and_is_end & 0x1);
5056 u32 mss = (mss_and_is_end >> 1);
5057 u32 vlan_tag = 0;
5058
5059 if (is_end)
5060 flags |= TXD_FLAG_END;
5061 if (flags & TXD_FLAG_VLAN) {
5062 vlan_tag = flags >> 16;
5063 flags &= 0xffff;
5064 }
5065 vlan_tag |= (mss << TXD_MSS_SHIFT);
5066
5067 txd->addr_hi = ((u64) mapping >> 32);
5068 txd->addr_lo = ((u64) mapping & 0xffffffff);
5069 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5070 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5071 }
5072
5073 /* hard_start_xmit for devices that don't have any bugs and
5074 * support TG3_FLG2_HW_TSO_2 only.
5075 */
5076 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5077 {
5078 struct tg3 *tp = netdev_priv(dev);
5079 u32 len, entry, base_flags, mss;
5080 struct skb_shared_info *sp;
5081 dma_addr_t mapping;
5082
5083 len = skb_headlen(skb);
5084
5085 /* We are running in BH disabled context with netif_tx_lock
5086 * and TX reclaim runs via tp->napi.poll inside of a software
5087 * interrupt. Furthermore, IRQ processing runs lockless so we have
5088 * no IRQ context deadlocks to worry about either. Rejoice!
5089 */
5090 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5091 if (!netif_queue_stopped(dev)) {
5092 netif_stop_queue(dev);
5093
5094 /* This is a hard error, log it. */
5095 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5096 "queue awake!\n", dev->name);
5097 }
5098 return NETDEV_TX_BUSY;
5099 }
5100
5101 entry = tp->tx_prod;
5102 base_flags = 0;
5103 mss = 0;
5104 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5105 int tcp_opt_len, ip_tcp_len;
5106
5107 if (skb_header_cloned(skb) &&
5108 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5109 dev_kfree_skb(skb);
5110 goto out_unlock;
5111 }
5112
5113 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5114 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5115 else {
5116 struct iphdr *iph = ip_hdr(skb);
5117
5118 tcp_opt_len = tcp_optlen(skb);
5119 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5120
5121 iph->check = 0;
5122 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5123 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5124 }
5125
5126 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5127 TXD_FLAG_CPU_POST_DMA);
5128
5129 tcp_hdr(skb)->check = 0;
5130
5131 }
5132 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5133 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5134 #if TG3_VLAN_TAG_USED
5135 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5136 base_flags |= (TXD_FLAG_VLAN |
5137 (vlan_tx_tag_get(skb) << 16));
5138 #endif
5139
5140 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5141 dev_kfree_skb(skb);
5142 goto out_unlock;
5143 }
5144
5145 sp = skb_shinfo(skb);
5146
5147 mapping = sp->dma_maps[0];
5148
5149 tp->tx_buffers[entry].skb = skb;
5150
5151 tg3_set_txd(tp, entry, mapping, len, base_flags,
5152 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5153
5154 entry = NEXT_TX(entry);
5155
5156 /* Now loop through additional data fragments, and queue them. */
5157 if (skb_shinfo(skb)->nr_frags > 0) {
5158 unsigned int i, last;
5159
5160 last = skb_shinfo(skb)->nr_frags - 1;
5161 for (i = 0; i <= last; i++) {
5162 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5163
5164 len = frag->size;
5165 mapping = sp->dma_maps[i + 1];
5166 tp->tx_buffers[entry].skb = NULL;
5167
5168 tg3_set_txd(tp, entry, mapping, len,
5169 base_flags, (i == last) | (mss << 1));
5170
5171 entry = NEXT_TX(entry);
5172 }
5173 }
5174
5175 /* Packets are ready, update Tx producer idx local and on card. */
5176 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5177
5178 tp->tx_prod = entry;
5179 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5180 netif_stop_queue(dev);
5181 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5182 netif_wake_queue(tp->dev);
5183 }
5184
5185 out_unlock:
5186 mmiowb();
5187
5188 dev->trans_start = jiffies;
5189
5190 return NETDEV_TX_OK;
5191 }
5192
5193 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5194
5195 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5196 * TSO header is greater than 80 bytes.
5197 */
5198 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5199 {
5200 struct sk_buff *segs, *nskb;
5201
5202 /* Estimate the number of fragments in the worst case */
5203 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5204 netif_stop_queue(tp->dev);
5205 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5206 return NETDEV_TX_BUSY;
5207
5208 netif_wake_queue(tp->dev);
5209 }
5210
5211 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5212 if (IS_ERR(segs))
5213 goto tg3_tso_bug_end;
5214
5215 do {
5216 nskb = segs;
5217 segs = segs->next;
5218 nskb->next = NULL;
5219 tg3_start_xmit_dma_bug(nskb, tp->dev);
5220 } while (segs);
5221
5222 tg3_tso_bug_end:
5223 dev_kfree_skb(skb);
5224
5225 return NETDEV_TX_OK;
5226 }
5227
5228 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5229 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5230 */
5231 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5232 {
5233 struct tg3 *tp = netdev_priv(dev);
5234 u32 len, entry, base_flags, mss;
5235 struct skb_shared_info *sp;
5236 int would_hit_hwbug;
5237 dma_addr_t mapping;
5238
5239 len = skb_headlen(skb);
5240
5241 /* We are running in BH disabled context with netif_tx_lock
5242 * and TX reclaim runs via tp->napi.poll inside of a software
5243 * interrupt. Furthermore, IRQ processing runs lockless so we have
5244 * no IRQ context deadlocks to worry about either. Rejoice!
5245 */
5246 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5247 if (!netif_queue_stopped(dev)) {
5248 netif_stop_queue(dev);
5249
5250 /* This is a hard error, log it. */
5251 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5252 "queue awake!\n", dev->name);
5253 }
5254 return NETDEV_TX_BUSY;
5255 }
5256
5257 entry = tp->tx_prod;
5258 base_flags = 0;
5259 if (skb->ip_summed == CHECKSUM_PARTIAL)
5260 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5261 mss = 0;
5262 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5263 struct iphdr *iph;
5264 int tcp_opt_len, ip_tcp_len, hdr_len;
5265
5266 if (skb_header_cloned(skb) &&
5267 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5268 dev_kfree_skb(skb);
5269 goto out_unlock;
5270 }
5271
5272 tcp_opt_len = tcp_optlen(skb);
5273 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5274
5275 hdr_len = ip_tcp_len + tcp_opt_len;
5276 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5277 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5278 return (tg3_tso_bug(tp, skb));
5279
5280 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5281 TXD_FLAG_CPU_POST_DMA);
5282
5283 iph = ip_hdr(skb);
5284 iph->check = 0;
5285 iph->tot_len = htons(mss + hdr_len);
5286 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5287 tcp_hdr(skb)->check = 0;
5288 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5289 } else
5290 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5291 iph->daddr, 0,
5292 IPPROTO_TCP,
5293 0);
5294
5295 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5296 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5297 if (tcp_opt_len || iph->ihl > 5) {
5298 int tsflags;
5299
5300 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5301 mss |= (tsflags << 11);
5302 }
5303 } else {
5304 if (tcp_opt_len || iph->ihl > 5) {
5305 int tsflags;
5306
5307 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5308 base_flags |= tsflags << 12;
5309 }
5310 }
5311 }
5312 #if TG3_VLAN_TAG_USED
5313 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5314 base_flags |= (TXD_FLAG_VLAN |
5315 (vlan_tx_tag_get(skb) << 16));
5316 #endif
5317
5318 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5319 dev_kfree_skb(skb);
5320 goto out_unlock;
5321 }
5322
5323 sp = skb_shinfo(skb);
5324
5325 mapping = sp->dma_maps[0];
5326
5327 tp->tx_buffers[entry].skb = skb;
5328
5329 would_hit_hwbug = 0;
5330
5331 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5332 would_hit_hwbug = 1;
5333 else if (tg3_4g_overflow_test(mapping, len))
5334 would_hit_hwbug = 1;
5335
5336 tg3_set_txd(tp, entry, mapping, len, base_flags,
5337 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5338
5339 entry = NEXT_TX(entry);
5340
5341 /* Now loop through additional data fragments, and queue them. */
5342 if (skb_shinfo(skb)->nr_frags > 0) {
5343 unsigned int i, last;
5344
5345 last = skb_shinfo(skb)->nr_frags - 1;
5346 for (i = 0; i <= last; i++) {
5347 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5348
5349 len = frag->size;
5350 mapping = sp->dma_maps[i + 1];
5351
5352 tp->tx_buffers[entry].skb = NULL;
5353
5354 if (tg3_4g_overflow_test(mapping, len))
5355 would_hit_hwbug = 1;
5356
5357 if (tg3_40bit_overflow_test(tp, mapping, len))
5358 would_hit_hwbug = 1;
5359
5360 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5361 tg3_set_txd(tp, entry, mapping, len,
5362 base_flags, (i == last)|(mss << 1));
5363 else
5364 tg3_set_txd(tp, entry, mapping, len,
5365 base_flags, (i == last));
5366
5367 entry = NEXT_TX(entry);
5368 }
5369 }
5370
5371 if (would_hit_hwbug) {
5372 u32 last_plus_one = entry;
5373 u32 start;
5374
5375 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5376 start &= (TG3_TX_RING_SIZE - 1);
5377
5378 /* If the workaround fails due to memory/mapping
5379 * failure, silently drop this packet.
5380 */
5381 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5382 &start, base_flags, mss))
5383 goto out_unlock;
5384
5385 entry = start;
5386 }
5387
5388 /* Packets are ready, update Tx producer idx local and on card. */
5389 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5390
5391 tp->tx_prod = entry;
5392 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5393 netif_stop_queue(dev);
5394 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5395 netif_wake_queue(tp->dev);
5396 }
5397
5398 out_unlock:
5399 mmiowb();
5400
5401 dev->trans_start = jiffies;
5402
5403 return NETDEV_TX_OK;
5404 }
5405
5406 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5407 int new_mtu)
5408 {
5409 dev->mtu = new_mtu;
5410
5411 if (new_mtu > ETH_DATA_LEN) {
5412 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5413 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5414 ethtool_op_set_tso(dev, 0);
5415 }
5416 else
5417 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5418 } else {
5419 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5420 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5421 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5422 }
5423 }
5424
5425 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5426 {
5427 struct tg3 *tp = netdev_priv(dev);
5428 int err;
5429
5430 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5431 return -EINVAL;
5432
5433 if (!netif_running(dev)) {
5434 /* We'll just catch it later when the
5435 * device is up'd.
5436 */
5437 tg3_set_mtu(dev, tp, new_mtu);
5438 return 0;
5439 }
5440
5441 tg3_phy_stop(tp);
5442
5443 tg3_netif_stop(tp);
5444
5445 tg3_full_lock(tp, 1);
5446
5447 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5448
5449 tg3_set_mtu(dev, tp, new_mtu);
5450
5451 err = tg3_restart_hw(tp, 0);
5452
5453 if (!err)
5454 tg3_netif_start(tp);
5455
5456 tg3_full_unlock(tp);
5457
5458 if (!err)
5459 tg3_phy_start(tp);
5460
5461 return err;
5462 }
5463
5464 /* Free up pending packets in all rx/tx rings.
5465 *
5466 * The chip has been shut down and the driver detached from
5467 * the networking, so no interrupts or new tx packets will
5468 * end up in the driver. tp->{tx,}lock is not held and we are not
5469 * in an interrupt context and thus may sleep.
5470 */
5471 static void tg3_free_rings(struct tg3 *tp)
5472 {
5473 struct ring_info *rxp;
5474 int i;
5475
5476 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5477 rxp = &tp->rx_std_buffers[i];
5478
5479 if (rxp->skb == NULL)
5480 continue;
5481 pci_unmap_single(tp->pdev,
5482 pci_unmap_addr(rxp, mapping),
5483 tp->rx_pkt_buf_sz - tp->rx_offset,
5484 PCI_DMA_FROMDEVICE);
5485 dev_kfree_skb_any(rxp->skb);
5486 rxp->skb = NULL;
5487 }
5488
5489 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5490 rxp = &tp->rx_jumbo_buffers[i];
5491
5492 if (rxp->skb == NULL)
5493 continue;
5494 pci_unmap_single(tp->pdev,
5495 pci_unmap_addr(rxp, mapping),
5496 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5497 PCI_DMA_FROMDEVICE);
5498 dev_kfree_skb_any(rxp->skb);
5499 rxp->skb = NULL;
5500 }
5501
5502 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5503 struct tx_ring_info *txp;
5504 struct sk_buff *skb;
5505
5506 txp = &tp->tx_buffers[i];
5507 skb = txp->skb;
5508
5509 if (skb == NULL) {
5510 i++;
5511 continue;
5512 }
5513
5514 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5515
5516 txp->skb = NULL;
5517
5518 i += skb_shinfo(skb)->nr_frags + 1;
5519
5520 dev_kfree_skb_any(skb);
5521 }
5522 }
5523
5524 /* Initialize tx/rx rings for packet processing.
5525 *
5526 * The chip has been shut down and the driver detached from
5527 * the networking, so no interrupts or new tx packets will
5528 * end up in the driver. tp->{tx,}lock are held and thus
5529 * we may not sleep.
5530 */
5531 static int tg3_init_rings(struct tg3 *tp)
5532 {
5533 u32 i;
5534
5535 /* Free up all the SKBs. */
5536 tg3_free_rings(tp);
5537
5538 /* Zero out all descriptors. */
5539 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5540 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5541 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5542 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5543
5544 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5545 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5546 (tp->dev->mtu > ETH_DATA_LEN))
5547 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5548
5549 /* Initialize invariants of the rings, we only set this
5550 * stuff once. This works because the card does not
5551 * write into the rx buffer posting rings.
5552 */
5553 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5554 struct tg3_rx_buffer_desc *rxd;
5555
5556 rxd = &tp->rx_std[i];
5557 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5558 << RXD_LEN_SHIFT;
5559 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5560 rxd->opaque = (RXD_OPAQUE_RING_STD |
5561 (i << RXD_OPAQUE_INDEX_SHIFT));
5562 }
5563
5564 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5565 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5566 struct tg3_rx_buffer_desc *rxd;
5567
5568 rxd = &tp->rx_jumbo[i];
5569 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5570 << RXD_LEN_SHIFT;
5571 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5572 RXD_FLAG_JUMBO;
5573 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5574 (i << RXD_OPAQUE_INDEX_SHIFT));
5575 }
5576 }
5577
5578 /* Now allocate fresh SKBs for each rx ring. */
5579 for (i = 0; i < tp->rx_pending; i++) {
5580 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5581 printk(KERN_WARNING PFX
5582 "%s: Using a smaller RX standard ring, "
5583 "only %d out of %d buffers were allocated "
5584 "successfully.\n",
5585 tp->dev->name, i, tp->rx_pending);
5586 if (i == 0)
5587 return -ENOMEM;
5588 tp->rx_pending = i;
5589 break;
5590 }
5591 }
5592
5593 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5594 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5595 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5596 -1, i) < 0) {
5597 printk(KERN_WARNING PFX
5598 "%s: Using a smaller RX jumbo ring, "
5599 "only %d out of %d buffers were "
5600 "allocated successfully.\n",
5601 tp->dev->name, i, tp->rx_jumbo_pending);
5602 if (i == 0) {
5603 tg3_free_rings(tp);
5604 return -ENOMEM;
5605 }
5606 tp->rx_jumbo_pending = i;
5607 break;
5608 }
5609 }
5610 }
5611 return 0;
5612 }
5613
5614 /*
5615 * Must not be invoked with interrupt sources disabled and
5616 * the hardware shutdown down.
5617 */
5618 static void tg3_free_consistent(struct tg3 *tp)
5619 {
5620 kfree(tp->rx_std_buffers);
5621 tp->rx_std_buffers = NULL;
5622 if (tp->rx_std) {
5623 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5624 tp->rx_std, tp->rx_std_mapping);
5625 tp->rx_std = NULL;
5626 }
5627 if (tp->rx_jumbo) {
5628 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5629 tp->rx_jumbo, tp->rx_jumbo_mapping);
5630 tp->rx_jumbo = NULL;
5631 }
5632 if (tp->rx_rcb) {
5633 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5634 tp->rx_rcb, tp->rx_rcb_mapping);
5635 tp->rx_rcb = NULL;
5636 }
5637 if (tp->tx_ring) {
5638 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5639 tp->tx_ring, tp->tx_desc_mapping);
5640 tp->tx_ring = NULL;
5641 }
5642 if (tp->hw_status) {
5643 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5644 tp->hw_status, tp->status_mapping);
5645 tp->hw_status = NULL;
5646 }
5647 if (tp->hw_stats) {
5648 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5649 tp->hw_stats, tp->stats_mapping);
5650 tp->hw_stats = NULL;
5651 }
5652 }
5653
5654 /*
5655 * Must not be invoked with interrupt sources disabled and
5656 * the hardware shutdown down. Can sleep.
5657 */
5658 static int tg3_alloc_consistent(struct tg3 *tp)
5659 {
5660 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5661 (TG3_RX_RING_SIZE +
5662 TG3_RX_JUMBO_RING_SIZE)) +
5663 (sizeof(struct tx_ring_info) *
5664 TG3_TX_RING_SIZE),
5665 GFP_KERNEL);
5666 if (!tp->rx_std_buffers)
5667 return -ENOMEM;
5668
5669 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5670 tp->tx_buffers = (struct tx_ring_info *)
5671 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5672
5673 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5674 &tp->rx_std_mapping);
5675 if (!tp->rx_std)
5676 goto err_out;
5677
5678 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5679 &tp->rx_jumbo_mapping);
5680
5681 if (!tp->rx_jumbo)
5682 goto err_out;
5683
5684 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5685 &tp->rx_rcb_mapping);
5686 if (!tp->rx_rcb)
5687 goto err_out;
5688
5689 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5690 &tp->tx_desc_mapping);
5691 if (!tp->tx_ring)
5692 goto err_out;
5693
5694 tp->hw_status = pci_alloc_consistent(tp->pdev,
5695 TG3_HW_STATUS_SIZE,
5696 &tp->status_mapping);
5697 if (!tp->hw_status)
5698 goto err_out;
5699
5700 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5701 sizeof(struct tg3_hw_stats),
5702 &tp->stats_mapping);
5703 if (!tp->hw_stats)
5704 goto err_out;
5705
5706 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5707 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5708
5709 return 0;
5710
5711 err_out:
5712 tg3_free_consistent(tp);
5713 return -ENOMEM;
5714 }
5715
5716 #define MAX_WAIT_CNT 1000
5717
5718 /* To stop a block, clear the enable bit and poll till it
5719 * clears. tp->lock is held.
5720 */
5721 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5722 {
5723 unsigned int i;
5724 u32 val;
5725
5726 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5727 switch (ofs) {
5728 case RCVLSC_MODE:
5729 case DMAC_MODE:
5730 case MBFREE_MODE:
5731 case BUFMGR_MODE:
5732 case MEMARB_MODE:
5733 /* We can't enable/disable these bits of the
5734 * 5705/5750, just say success.
5735 */
5736 return 0;
5737
5738 default:
5739 break;
5740 }
5741 }
5742
5743 val = tr32(ofs);
5744 val &= ~enable_bit;
5745 tw32_f(ofs, val);
5746
5747 for (i = 0; i < MAX_WAIT_CNT; i++) {
5748 udelay(100);
5749 val = tr32(ofs);
5750 if ((val & enable_bit) == 0)
5751 break;
5752 }
5753
5754 if (i == MAX_WAIT_CNT && !silent) {
5755 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5756 "ofs=%lx enable_bit=%x\n",
5757 ofs, enable_bit);
5758 return -ENODEV;
5759 }
5760
5761 return 0;
5762 }
5763
5764 /* tp->lock is held. */
5765 static int tg3_abort_hw(struct tg3 *tp, int silent)
5766 {
5767 int i, err;
5768
5769 tg3_disable_ints(tp);
5770
5771 tp->rx_mode &= ~RX_MODE_ENABLE;
5772 tw32_f(MAC_RX_MODE, tp->rx_mode);
5773 udelay(10);
5774
5775 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5776 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5777 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5778 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5779 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5780 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5781
5782 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5783 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5784 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5785 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5786 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5787 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5788 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5789
5790 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5791 tw32_f(MAC_MODE, tp->mac_mode);
5792 udelay(40);
5793
5794 tp->tx_mode &= ~TX_MODE_ENABLE;
5795 tw32_f(MAC_TX_MODE, tp->tx_mode);
5796
5797 for (i = 0; i < MAX_WAIT_CNT; i++) {
5798 udelay(100);
5799 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5800 break;
5801 }
5802 if (i >= MAX_WAIT_CNT) {
5803 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5804 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5805 tp->dev->name, tr32(MAC_TX_MODE));
5806 err |= -ENODEV;
5807 }
5808
5809 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5810 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5811 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5812
5813 tw32(FTQ_RESET, 0xffffffff);
5814 tw32(FTQ_RESET, 0x00000000);
5815
5816 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5817 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5818
5819 if (tp->hw_status)
5820 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5821 if (tp->hw_stats)
5822 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5823
5824 return err;
5825 }
5826
5827 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5828 {
5829 int i;
5830 u32 apedata;
5831
5832 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5833 if (apedata != APE_SEG_SIG_MAGIC)
5834 return;
5835
5836 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5837 if (!(apedata & APE_FW_STATUS_READY))
5838 return;
5839
5840 /* Wait for up to 1 millisecond for APE to service previous event. */
5841 for (i = 0; i < 10; i++) {
5842 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5843 return;
5844
5845 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5846
5847 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5848 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5849 event | APE_EVENT_STATUS_EVENT_PENDING);
5850
5851 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5852
5853 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5854 break;
5855
5856 udelay(100);
5857 }
5858
5859 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5860 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5861 }
5862
5863 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5864 {
5865 u32 event;
5866 u32 apedata;
5867
5868 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5869 return;
5870
5871 switch (kind) {
5872 case RESET_KIND_INIT:
5873 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5874 APE_HOST_SEG_SIG_MAGIC);
5875 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5876 APE_HOST_SEG_LEN_MAGIC);
5877 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5878 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5879 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5880 APE_HOST_DRIVER_ID_MAGIC);
5881 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5882 APE_HOST_BEHAV_NO_PHYLOCK);
5883
5884 event = APE_EVENT_STATUS_STATE_START;
5885 break;
5886 case RESET_KIND_SHUTDOWN:
5887 /* With the interface we are currently using,
5888 * APE does not track driver state. Wiping
5889 * out the HOST SEGMENT SIGNATURE forces
5890 * the APE to assume OS absent status.
5891 */
5892 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5893
5894 event = APE_EVENT_STATUS_STATE_UNLOAD;
5895 break;
5896 case RESET_KIND_SUSPEND:
5897 event = APE_EVENT_STATUS_STATE_SUSPEND;
5898 break;
5899 default:
5900 return;
5901 }
5902
5903 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5904
5905 tg3_ape_send_event(tp, event);
5906 }
5907
5908 /* tp->lock is held. */
5909 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5910 {
5911 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5912 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5913
5914 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5915 switch (kind) {
5916 case RESET_KIND_INIT:
5917 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5918 DRV_STATE_START);
5919 break;
5920
5921 case RESET_KIND_SHUTDOWN:
5922 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5923 DRV_STATE_UNLOAD);
5924 break;
5925
5926 case RESET_KIND_SUSPEND:
5927 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5928 DRV_STATE_SUSPEND);
5929 break;
5930
5931 default:
5932 break;
5933 }
5934 }
5935
5936 if (kind == RESET_KIND_INIT ||
5937 kind == RESET_KIND_SUSPEND)
5938 tg3_ape_driver_state_change(tp, kind);
5939 }
5940
5941 /* tp->lock is held. */
5942 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5943 {
5944 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5945 switch (kind) {
5946 case RESET_KIND_INIT:
5947 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5948 DRV_STATE_START_DONE);
5949 break;
5950
5951 case RESET_KIND_SHUTDOWN:
5952 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5953 DRV_STATE_UNLOAD_DONE);
5954 break;
5955
5956 default:
5957 break;
5958 }
5959 }
5960
5961 if (kind == RESET_KIND_SHUTDOWN)
5962 tg3_ape_driver_state_change(tp, kind);
5963 }
5964
5965 /* tp->lock is held. */
5966 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5967 {
5968 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5969 switch (kind) {
5970 case RESET_KIND_INIT:
5971 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5972 DRV_STATE_START);
5973 break;
5974
5975 case RESET_KIND_SHUTDOWN:
5976 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5977 DRV_STATE_UNLOAD);
5978 break;
5979
5980 case RESET_KIND_SUSPEND:
5981 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5982 DRV_STATE_SUSPEND);
5983 break;
5984
5985 default:
5986 break;
5987 }
5988 }
5989 }
5990
5991 static int tg3_poll_fw(struct tg3 *tp)
5992 {
5993 int i;
5994 u32 val;
5995
5996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5997 /* Wait up to 20ms for init done. */
5998 for (i = 0; i < 200; i++) {
5999 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6000 return 0;
6001 udelay(100);
6002 }
6003 return -ENODEV;
6004 }
6005
6006 /* Wait for firmware initialization to complete. */
6007 for (i = 0; i < 100000; i++) {
6008 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6009 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6010 break;
6011 udelay(10);
6012 }
6013
6014 /* Chip might not be fitted with firmware. Some Sun onboard
6015 * parts are configured like that. So don't signal the timeout
6016 * of the above loop as an error, but do report the lack of
6017 * running firmware once.
6018 */
6019 if (i >= 100000 &&
6020 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6021 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6022
6023 printk(KERN_INFO PFX "%s: No firmware running.\n",
6024 tp->dev->name);
6025 }
6026
6027 return 0;
6028 }
6029
6030 /* Save PCI command register before chip reset */
6031 static void tg3_save_pci_state(struct tg3 *tp)
6032 {
6033 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6034 }
6035
6036 /* Restore PCI state after chip reset */
6037 static void tg3_restore_pci_state(struct tg3 *tp)
6038 {
6039 u32 val;
6040
6041 /* Re-enable indirect register accesses. */
6042 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6043 tp->misc_host_ctrl);
6044
6045 /* Set MAX PCI retry to zero. */
6046 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6047 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6048 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6049 val |= PCISTATE_RETRY_SAME_DMA;
6050 /* Allow reads and writes to the APE register and memory space. */
6051 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6052 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6053 PCISTATE_ALLOW_APE_SHMEM_WR;
6054 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6055
6056 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6057
6058 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6059 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6060 pcie_set_readrq(tp->pdev, 4096);
6061 else {
6062 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6063 tp->pci_cacheline_sz);
6064 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6065 tp->pci_lat_timer);
6066 }
6067 }
6068
6069 /* Make sure PCI-X relaxed ordering bit is clear. */
6070 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6071 u16 pcix_cmd;
6072
6073 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6074 &pcix_cmd);
6075 pcix_cmd &= ~PCI_X_CMD_ERO;
6076 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6077 pcix_cmd);
6078 }
6079
6080 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6081
6082 /* Chip reset on 5780 will reset MSI enable bit,
6083 * so need to restore it.
6084 */
6085 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6086 u16 ctrl;
6087
6088 pci_read_config_word(tp->pdev,
6089 tp->msi_cap + PCI_MSI_FLAGS,
6090 &ctrl);
6091 pci_write_config_word(tp->pdev,
6092 tp->msi_cap + PCI_MSI_FLAGS,
6093 ctrl | PCI_MSI_FLAGS_ENABLE);
6094 val = tr32(MSGINT_MODE);
6095 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6096 }
6097 }
6098 }
6099
6100 static void tg3_stop_fw(struct tg3 *);
6101
6102 /* tp->lock is held. */
6103 static int tg3_chip_reset(struct tg3 *tp)
6104 {
6105 u32 val;
6106 void (*write_op)(struct tg3 *, u32, u32);
6107 int err;
6108
6109 tg3_nvram_lock(tp);
6110
6111 tg3_mdio_stop(tp);
6112
6113 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6114
6115 /* No matching tg3_nvram_unlock() after this because
6116 * chip reset below will undo the nvram lock.
6117 */
6118 tp->nvram_lock_cnt = 0;
6119
6120 /* GRC_MISC_CFG core clock reset will clear the memory
6121 * enable bit in PCI register 4 and the MSI enable bit
6122 * on some chips, so we save relevant registers here.
6123 */
6124 tg3_save_pci_state(tp);
6125
6126 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6127 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6128 tw32(GRC_FASTBOOT_PC, 0);
6129
6130 /*
6131 * We must avoid the readl() that normally takes place.
6132 * It locks machines, causes machine checks, and other
6133 * fun things. So, temporarily disable the 5701
6134 * hardware workaround, while we do the reset.
6135 */
6136 write_op = tp->write32;
6137 if (write_op == tg3_write_flush_reg32)
6138 tp->write32 = tg3_write32;
6139
6140 /* Prevent the irq handler from reading or writing PCI registers
6141 * during chip reset when the memory enable bit in the PCI command
6142 * register may be cleared. The chip does not generate interrupt
6143 * at this time, but the irq handler may still be called due to irq
6144 * sharing or irqpoll.
6145 */
6146 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6147 if (tp->hw_status) {
6148 tp->hw_status->status = 0;
6149 tp->hw_status->status_tag = 0;
6150 }
6151 tp->last_tag = 0;
6152 smp_mb();
6153 synchronize_irq(tp->pdev->irq);
6154
6155 /* do the reset */
6156 val = GRC_MISC_CFG_CORECLK_RESET;
6157
6158 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6159 if (tr32(0x7e2c) == 0x60) {
6160 tw32(0x7e2c, 0x20);
6161 }
6162 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6163 tw32(GRC_MISC_CFG, (1 << 29));
6164 val |= (1 << 29);
6165 }
6166 }
6167
6168 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6169 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6170 tw32(GRC_VCPU_EXT_CTRL,
6171 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6172 }
6173
6174 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6175 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6176 tw32(GRC_MISC_CFG, val);
6177
6178 /* restore 5701 hardware bug workaround write method */
6179 tp->write32 = write_op;
6180
6181 /* Unfortunately, we have to delay before the PCI read back.
6182 * Some 575X chips even will not respond to a PCI cfg access
6183 * when the reset command is given to the chip.
6184 *
6185 * How do these hardware designers expect things to work
6186 * properly if the PCI write is posted for a long period
6187 * of time? It is always necessary to have some method by
6188 * which a register read back can occur to push the write
6189 * out which does the reset.
6190 *
6191 * For most tg3 variants the trick below was working.
6192 * Ho hum...
6193 */
6194 udelay(120);
6195
6196 /* Flush PCI posted writes. The normal MMIO registers
6197 * are inaccessible at this time so this is the only
6198 * way to make this reliably (actually, this is no longer
6199 * the case, see above). I tried to use indirect
6200 * register read/write but this upset some 5701 variants.
6201 */
6202 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6203
6204 udelay(120);
6205
6206 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6207 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6208 int i;
6209 u32 cfg_val;
6210
6211 /* Wait for link training to complete. */
6212 for (i = 0; i < 5000; i++)
6213 udelay(100);
6214
6215 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6216 pci_write_config_dword(tp->pdev, 0xc4,
6217 cfg_val | (1 << 15));
6218 }
6219
6220 /* Set PCIE max payload size to 128 bytes and
6221 * clear the "no snoop" and "relaxed ordering" bits.
6222 */
6223 pci_write_config_word(tp->pdev,
6224 tp->pcie_cap + PCI_EXP_DEVCTL,
6225 0);
6226
6227 pcie_set_readrq(tp->pdev, 4096);
6228
6229 /* Clear error status */
6230 pci_write_config_word(tp->pdev,
6231 tp->pcie_cap + PCI_EXP_DEVSTA,
6232 PCI_EXP_DEVSTA_CED |
6233 PCI_EXP_DEVSTA_NFED |
6234 PCI_EXP_DEVSTA_FED |
6235 PCI_EXP_DEVSTA_URD);
6236 }
6237
6238 tg3_restore_pci_state(tp);
6239
6240 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6241
6242 val = 0;
6243 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6244 val = tr32(MEMARB_MODE);
6245 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6246
6247 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6248 tg3_stop_fw(tp);
6249 tw32(0x5000, 0x400);
6250 }
6251
6252 tw32(GRC_MODE, tp->grc_mode);
6253
6254 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6255 val = tr32(0xc4);
6256
6257 tw32(0xc4, val | (1 << 15));
6258 }
6259
6260 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6261 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6262 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6263 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6264 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6265 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6266 }
6267
6268 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6269 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6270 tw32_f(MAC_MODE, tp->mac_mode);
6271 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6272 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6273 tw32_f(MAC_MODE, tp->mac_mode);
6274 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6275 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6276 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6277 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6278 tw32_f(MAC_MODE, tp->mac_mode);
6279 } else
6280 tw32_f(MAC_MODE, 0);
6281 udelay(40);
6282
6283 tg3_mdio_start(tp);
6284
6285 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6286
6287 err = tg3_poll_fw(tp);
6288 if (err)
6289 return err;
6290
6291 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6292 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6293 val = tr32(0x7c00);
6294
6295 tw32(0x7c00, val | (1 << 25));
6296 }
6297
6298 /* Reprobe ASF enable state. */
6299 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6300 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6301 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6302 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6303 u32 nic_cfg;
6304
6305 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6306 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6307 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6308 tp->last_event_jiffies = jiffies;
6309 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6310 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6311 }
6312 }
6313
6314 return 0;
6315 }
6316
6317 /* tp->lock is held. */
6318 static void tg3_stop_fw(struct tg3 *tp)
6319 {
6320 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6321 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6322 /* Wait for RX cpu to ACK the previous event. */
6323 tg3_wait_for_event_ack(tp);
6324
6325 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6326
6327 tg3_generate_fw_event(tp);
6328
6329 /* Wait for RX cpu to ACK this event. */
6330 tg3_wait_for_event_ack(tp);
6331 }
6332 }
6333
6334 /* tp->lock is held. */
6335 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6336 {
6337 int err;
6338
6339 tg3_stop_fw(tp);
6340
6341 tg3_write_sig_pre_reset(tp, kind);
6342
6343 tg3_abort_hw(tp, silent);
6344 err = tg3_chip_reset(tp);
6345
6346 tg3_write_sig_legacy(tp, kind);
6347 tg3_write_sig_post_reset(tp, kind);
6348
6349 if (err)
6350 return err;
6351
6352 return 0;
6353 }
6354
6355 #define RX_CPU_SCRATCH_BASE 0x30000
6356 #define RX_CPU_SCRATCH_SIZE 0x04000
6357 #define TX_CPU_SCRATCH_BASE 0x34000
6358 #define TX_CPU_SCRATCH_SIZE 0x04000
6359
6360 /* tp->lock is held. */
6361 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6362 {
6363 int i;
6364
6365 BUG_ON(offset == TX_CPU_BASE &&
6366 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6367
6368 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6369 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6370
6371 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6372 return 0;
6373 }
6374 if (offset == RX_CPU_BASE) {
6375 for (i = 0; i < 10000; i++) {
6376 tw32(offset + CPU_STATE, 0xffffffff);
6377 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6378 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6379 break;
6380 }
6381
6382 tw32(offset + CPU_STATE, 0xffffffff);
6383 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6384 udelay(10);
6385 } else {
6386 for (i = 0; i < 10000; i++) {
6387 tw32(offset + CPU_STATE, 0xffffffff);
6388 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6389 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6390 break;
6391 }
6392 }
6393
6394 if (i >= 10000) {
6395 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6396 "and %s CPU\n",
6397 tp->dev->name,
6398 (offset == RX_CPU_BASE ? "RX" : "TX"));
6399 return -ENODEV;
6400 }
6401
6402 /* Clear firmware's nvram arbitration. */
6403 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6404 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6405 return 0;
6406 }
6407
6408 struct fw_info {
6409 unsigned int fw_base;
6410 unsigned int fw_len;
6411 const __be32 *fw_data;
6412 };
6413
6414 /* tp->lock is held. */
6415 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6416 int cpu_scratch_size, struct fw_info *info)
6417 {
6418 int err, lock_err, i;
6419 void (*write_op)(struct tg3 *, u32, u32);
6420
6421 if (cpu_base == TX_CPU_BASE &&
6422 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6423 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6424 "TX cpu firmware on %s which is 5705.\n",
6425 tp->dev->name);
6426 return -EINVAL;
6427 }
6428
6429 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6430 write_op = tg3_write_mem;
6431 else
6432 write_op = tg3_write_indirect_reg32;
6433
6434 /* It is possible that bootcode is still loading at this point.
6435 * Get the nvram lock first before halting the cpu.
6436 */
6437 lock_err = tg3_nvram_lock(tp);
6438 err = tg3_halt_cpu(tp, cpu_base);
6439 if (!lock_err)
6440 tg3_nvram_unlock(tp);
6441 if (err)
6442 goto out;
6443
6444 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6445 write_op(tp, cpu_scratch_base + i, 0);
6446 tw32(cpu_base + CPU_STATE, 0xffffffff);
6447 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6448 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6449 write_op(tp, (cpu_scratch_base +
6450 (info->fw_base & 0xffff) +
6451 (i * sizeof(u32))),
6452 be32_to_cpu(info->fw_data[i]));
6453
6454 err = 0;
6455
6456 out:
6457 return err;
6458 }
6459
6460 /* tp->lock is held. */
6461 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6462 {
6463 struct fw_info info;
6464 const __be32 *fw_data;
6465 int err, i;
6466
6467 fw_data = (void *)tp->fw->data;
6468
6469 /* Firmware blob starts with version numbers, followed by
6470 start address and length. We are setting complete length.
6471 length = end_address_of_bss - start_address_of_text.
6472 Remainder is the blob to be loaded contiguously
6473 from start address. */
6474
6475 info.fw_base = be32_to_cpu(fw_data[1]);
6476 info.fw_len = tp->fw->size - 12;
6477 info.fw_data = &fw_data[3];
6478
6479 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6480 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6481 &info);
6482 if (err)
6483 return err;
6484
6485 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6486 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6487 &info);
6488 if (err)
6489 return err;
6490
6491 /* Now startup only the RX cpu. */
6492 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6493 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6494
6495 for (i = 0; i < 5; i++) {
6496 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6497 break;
6498 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6499 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6500 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6501 udelay(1000);
6502 }
6503 if (i >= 5) {
6504 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6505 "to set RX CPU PC, is %08x should be %08x\n",
6506 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6507 info.fw_base);
6508 return -ENODEV;
6509 }
6510 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6511 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6512
6513 return 0;
6514 }
6515
6516 /* 5705 needs a special version of the TSO firmware. */
6517
6518 /* tp->lock is held. */
6519 static int tg3_load_tso_firmware(struct tg3 *tp)
6520 {
6521 struct fw_info info;
6522 const __be32 *fw_data;
6523 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6524 int err, i;
6525
6526 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6527 return 0;
6528
6529 fw_data = (void *)tp->fw->data;
6530
6531 /* Firmware blob starts with version numbers, followed by
6532 start address and length. We are setting complete length.
6533 length = end_address_of_bss - start_address_of_text.
6534 Remainder is the blob to be loaded contiguously
6535 from start address. */
6536
6537 info.fw_base = be32_to_cpu(fw_data[1]);
6538 cpu_scratch_size = tp->fw_len;
6539 info.fw_len = tp->fw->size - 12;
6540 info.fw_data = &fw_data[3];
6541
6542 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6543 cpu_base = RX_CPU_BASE;
6544 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6545 } else {
6546 cpu_base = TX_CPU_BASE;
6547 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6548 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6549 }
6550
6551 err = tg3_load_firmware_cpu(tp, cpu_base,
6552 cpu_scratch_base, cpu_scratch_size,
6553 &info);
6554 if (err)
6555 return err;
6556
6557 /* Now startup the cpu. */
6558 tw32(cpu_base + CPU_STATE, 0xffffffff);
6559 tw32_f(cpu_base + CPU_PC, info.fw_base);
6560
6561 for (i = 0; i < 5; i++) {
6562 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6563 break;
6564 tw32(cpu_base + CPU_STATE, 0xffffffff);
6565 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6566 tw32_f(cpu_base + CPU_PC, info.fw_base);
6567 udelay(1000);
6568 }
6569 if (i >= 5) {
6570 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6571 "to set CPU PC, is %08x should be %08x\n",
6572 tp->dev->name, tr32(cpu_base + CPU_PC),
6573 info.fw_base);
6574 return -ENODEV;
6575 }
6576 tw32(cpu_base + CPU_STATE, 0xffffffff);
6577 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6578 return 0;
6579 }
6580
6581
6582 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6583 {
6584 struct tg3 *tp = netdev_priv(dev);
6585 struct sockaddr *addr = p;
6586 int err = 0, skip_mac_1 = 0;
6587
6588 if (!is_valid_ether_addr(addr->sa_data))
6589 return -EINVAL;
6590
6591 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6592
6593 if (!netif_running(dev))
6594 return 0;
6595
6596 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6597 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6598
6599 addr0_high = tr32(MAC_ADDR_0_HIGH);
6600 addr0_low = tr32(MAC_ADDR_0_LOW);
6601 addr1_high = tr32(MAC_ADDR_1_HIGH);
6602 addr1_low = tr32(MAC_ADDR_1_LOW);
6603
6604 /* Skip MAC addr 1 if ASF is using it. */
6605 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6606 !(addr1_high == 0 && addr1_low == 0))
6607 skip_mac_1 = 1;
6608 }
6609 spin_lock_bh(&tp->lock);
6610 __tg3_set_mac_addr(tp, skip_mac_1);
6611 spin_unlock_bh(&tp->lock);
6612
6613 return err;
6614 }
6615
6616 /* tp->lock is held. */
6617 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6618 dma_addr_t mapping, u32 maxlen_flags,
6619 u32 nic_addr)
6620 {
6621 tg3_write_mem(tp,
6622 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6623 ((u64) mapping >> 32));
6624 tg3_write_mem(tp,
6625 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6626 ((u64) mapping & 0xffffffff));
6627 tg3_write_mem(tp,
6628 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6629 maxlen_flags);
6630
6631 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6632 tg3_write_mem(tp,
6633 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6634 nic_addr);
6635 }
6636
6637 static void __tg3_set_rx_mode(struct net_device *);
6638 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6639 {
6640 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6641 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6642 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6643 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6644 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6645 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6646 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6647 }
6648 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6649 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6650 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6651 u32 val = ec->stats_block_coalesce_usecs;
6652
6653 if (!netif_carrier_ok(tp->dev))
6654 val = 0;
6655
6656 tw32(HOSTCC_STAT_COAL_TICKS, val);
6657 }
6658 }
6659
6660 /* tp->lock is held. */
6661 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6662 {
6663 u32 val, rdmac_mode;
6664 int i, err, limit;
6665
6666 tg3_disable_ints(tp);
6667
6668 tg3_stop_fw(tp);
6669
6670 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6671
6672 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6673 tg3_abort_hw(tp, 1);
6674 }
6675
6676 if (reset_phy &&
6677 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6678 tg3_phy_reset(tp);
6679
6680 err = tg3_chip_reset(tp);
6681 if (err)
6682 return err;
6683
6684 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6685
6686 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6687 val = tr32(TG3_CPMU_CTRL);
6688 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6689 tw32(TG3_CPMU_CTRL, val);
6690
6691 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6692 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6693 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6694 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6695
6696 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6697 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6698 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6699 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6700
6701 val = tr32(TG3_CPMU_HST_ACC);
6702 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6703 val |= CPMU_HST_ACC_MACCLK_6_25;
6704 tw32(TG3_CPMU_HST_ACC, val);
6705 }
6706
6707 /* This works around an issue with Athlon chipsets on
6708 * B3 tigon3 silicon. This bit has no effect on any
6709 * other revision. But do not set this on PCI Express
6710 * chips and don't even touch the clocks if the CPMU is present.
6711 */
6712 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6713 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6714 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6715 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6716 }
6717
6718 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6719 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6720 val = tr32(TG3PCI_PCISTATE);
6721 val |= PCISTATE_RETRY_SAME_DMA;
6722 tw32(TG3PCI_PCISTATE, val);
6723 }
6724
6725 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6726 /* Allow reads and writes to the
6727 * APE register and memory space.
6728 */
6729 val = tr32(TG3PCI_PCISTATE);
6730 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6731 PCISTATE_ALLOW_APE_SHMEM_WR;
6732 tw32(TG3PCI_PCISTATE, val);
6733 }
6734
6735 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6736 /* Enable some hw fixes. */
6737 val = tr32(TG3PCI_MSI_DATA);
6738 val |= (1 << 26) | (1 << 28) | (1 << 29);
6739 tw32(TG3PCI_MSI_DATA, val);
6740 }
6741
6742 /* Descriptor ring init may make accesses to the
6743 * NIC SRAM area to setup the TX descriptors, so we
6744 * can only do this after the hardware has been
6745 * successfully reset.
6746 */
6747 err = tg3_init_rings(tp);
6748 if (err)
6749 return err;
6750
6751 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6752 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6753 /* This value is determined during the probe time DMA
6754 * engine test, tg3_test_dma.
6755 */
6756 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6757 }
6758
6759 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6760 GRC_MODE_4X_NIC_SEND_RINGS |
6761 GRC_MODE_NO_TX_PHDR_CSUM |
6762 GRC_MODE_NO_RX_PHDR_CSUM);
6763 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6764
6765 /* Pseudo-header checksum is done by hardware logic and not
6766 * the offload processers, so make the chip do the pseudo-
6767 * header checksums on receive. For transmit it is more
6768 * convenient to do the pseudo-header checksum in software
6769 * as Linux does that on transmit for us in all cases.
6770 */
6771 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6772
6773 tw32(GRC_MODE,
6774 tp->grc_mode |
6775 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6776
6777 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6778 val = tr32(GRC_MISC_CFG);
6779 val &= ~0xff;
6780 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6781 tw32(GRC_MISC_CFG, val);
6782
6783 /* Initialize MBUF/DESC pool. */
6784 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6785 /* Do nothing. */
6786 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6787 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6788 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6789 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6790 else
6791 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6792 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6793 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6794 }
6795 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6796 int fw_len;
6797
6798 fw_len = tp->fw_len;
6799 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6800 tw32(BUFMGR_MB_POOL_ADDR,
6801 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6802 tw32(BUFMGR_MB_POOL_SIZE,
6803 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6804 }
6805
6806 if (tp->dev->mtu <= ETH_DATA_LEN) {
6807 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6808 tp->bufmgr_config.mbuf_read_dma_low_water);
6809 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6810 tp->bufmgr_config.mbuf_mac_rx_low_water);
6811 tw32(BUFMGR_MB_HIGH_WATER,
6812 tp->bufmgr_config.mbuf_high_water);
6813 } else {
6814 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6815 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6816 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6817 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6818 tw32(BUFMGR_MB_HIGH_WATER,
6819 tp->bufmgr_config.mbuf_high_water_jumbo);
6820 }
6821 tw32(BUFMGR_DMA_LOW_WATER,
6822 tp->bufmgr_config.dma_low_water);
6823 tw32(BUFMGR_DMA_HIGH_WATER,
6824 tp->bufmgr_config.dma_high_water);
6825
6826 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6827 for (i = 0; i < 2000; i++) {
6828 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6829 break;
6830 udelay(10);
6831 }
6832 if (i >= 2000) {
6833 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6834 tp->dev->name);
6835 return -ENODEV;
6836 }
6837
6838 /* Setup replenish threshold. */
6839 val = tp->rx_pending / 8;
6840 if (val == 0)
6841 val = 1;
6842 else if (val > tp->rx_std_max_post)
6843 val = tp->rx_std_max_post;
6844 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6845 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6846 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6847
6848 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6849 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6850 }
6851
6852 tw32(RCVBDI_STD_THRESH, val);
6853
6854 /* Initialize TG3_BDINFO's at:
6855 * RCVDBDI_STD_BD: standard eth size rx ring
6856 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6857 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6858 *
6859 * like so:
6860 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6861 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6862 * ring attribute flags
6863 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6864 *
6865 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6866 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6867 *
6868 * The size of each ring is fixed in the firmware, but the location is
6869 * configurable.
6870 */
6871 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6872 ((u64) tp->rx_std_mapping >> 32));
6873 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6874 ((u64) tp->rx_std_mapping & 0xffffffff));
6875 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6876 NIC_SRAM_RX_BUFFER_DESC);
6877
6878 /* Don't even try to program the JUMBO/MINI buffer descriptor
6879 * configs on 5705.
6880 */
6881 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6882 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6883 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6884 } else {
6885 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6886 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6887
6888 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6889 BDINFO_FLAGS_DISABLED);
6890
6891 /* Setup replenish threshold. */
6892 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6893
6894 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6895 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6896 ((u64) tp->rx_jumbo_mapping >> 32));
6897 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6898 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6899 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6900 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6901 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6902 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6903 } else {
6904 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6905 BDINFO_FLAGS_DISABLED);
6906 }
6907
6908 }
6909
6910 /* There is only one send ring on 5705/5750, no need to explicitly
6911 * disable the others.
6912 */
6913 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6914 /* Clear out send RCB ring in SRAM. */
6915 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6916 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6917 BDINFO_FLAGS_DISABLED);
6918 }
6919
6920 tp->tx_prod = 0;
6921 tp->tx_cons = 0;
6922 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6923 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6924
6925 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6926 tp->tx_desc_mapping,
6927 (TG3_TX_RING_SIZE <<
6928 BDINFO_FLAGS_MAXLEN_SHIFT),
6929 NIC_SRAM_TX_BUFFER_DESC);
6930
6931 /* There is only one receive return ring on 5705/5750, no need
6932 * to explicitly disable the others.
6933 */
6934 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6935 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6936 i += TG3_BDINFO_SIZE) {
6937 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6938 BDINFO_FLAGS_DISABLED);
6939 }
6940 }
6941
6942 tp->rx_rcb_ptr = 0;
6943 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6944
6945 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6946 tp->rx_rcb_mapping,
6947 (TG3_RX_RCB_RING_SIZE(tp) <<
6948 BDINFO_FLAGS_MAXLEN_SHIFT),
6949 0);
6950
6951 tp->rx_std_ptr = tp->rx_pending;
6952 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6953 tp->rx_std_ptr);
6954
6955 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6956 tp->rx_jumbo_pending : 0;
6957 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6958 tp->rx_jumbo_ptr);
6959
6960 /* Initialize MAC address and backoff seed. */
6961 __tg3_set_mac_addr(tp, 0);
6962
6963 /* MTU + ethernet header + FCS + optional VLAN tag */
6964 tw32(MAC_RX_MTU_SIZE,
6965 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
6966
6967 /* The slot time is changed by tg3_setup_phy if we
6968 * run at gigabit with half duplex.
6969 */
6970 tw32(MAC_TX_LENGTHS,
6971 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6972 (6 << TX_LENGTHS_IPG_SHIFT) |
6973 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6974
6975 /* Receive rules. */
6976 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6977 tw32(RCVLPC_CONFIG, 0x0181);
6978
6979 /* Calculate RDMAC_MODE setting early, we need it to determine
6980 * the RCVLPC_STATE_ENABLE mask.
6981 */
6982 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6983 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6984 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6985 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6986 RDMAC_MODE_LNGREAD_ENAB);
6987
6988 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
6989 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
6990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
6991 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6992 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6993 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
6994
6995 /* If statement applies to 5705 and 5750 PCI devices only */
6996 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6997 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6998 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6999 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7001 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7002 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7003 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7004 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7005 }
7006 }
7007
7008 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7009 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7010
7011 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7012 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7013
7014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7016 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7017
7018 /* Receive/send statistics. */
7019 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7020 val = tr32(RCVLPC_STATS_ENABLE);
7021 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7022 tw32(RCVLPC_STATS_ENABLE, val);
7023 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7024 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7025 val = tr32(RCVLPC_STATS_ENABLE);
7026 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7027 tw32(RCVLPC_STATS_ENABLE, val);
7028 } else {
7029 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7030 }
7031 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7032 tw32(SNDDATAI_STATSENAB, 0xffffff);
7033 tw32(SNDDATAI_STATSCTRL,
7034 (SNDDATAI_SCTRL_ENABLE |
7035 SNDDATAI_SCTRL_FASTUPD));
7036
7037 /* Setup host coalescing engine. */
7038 tw32(HOSTCC_MODE, 0);
7039 for (i = 0; i < 2000; i++) {
7040 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7041 break;
7042 udelay(10);
7043 }
7044
7045 __tg3_set_coalesce(tp, &tp->coal);
7046
7047 /* set status block DMA address */
7048 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7049 ((u64) tp->status_mapping >> 32));
7050 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7051 ((u64) tp->status_mapping & 0xffffffff));
7052
7053 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7054 /* Status/statistics block address. See tg3_timer,
7055 * the tg3_periodic_fetch_stats call there, and
7056 * tg3_get_stats to see how this works for 5705/5750 chips.
7057 */
7058 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7059 ((u64) tp->stats_mapping >> 32));
7060 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7061 ((u64) tp->stats_mapping & 0xffffffff));
7062 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7063 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7064 }
7065
7066 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7067
7068 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7069 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7070 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7071 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7072
7073 /* Clear statistics/status block in chip, and status block in ram. */
7074 for (i = NIC_SRAM_STATS_BLK;
7075 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7076 i += sizeof(u32)) {
7077 tg3_write_mem(tp, i, 0);
7078 udelay(40);
7079 }
7080 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7081
7082 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7083 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7084 /* reset to prevent losing 1st rx packet intermittently */
7085 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7086 udelay(10);
7087 }
7088
7089 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7090 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7091 else
7092 tp->mac_mode = 0;
7093 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7094 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7095 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7096 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7097 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7098 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7099 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7100 udelay(40);
7101
7102 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7103 * If TG3_FLG2_IS_NIC is zero, we should read the
7104 * register to preserve the GPIO settings for LOMs. The GPIOs,
7105 * whether used as inputs or outputs, are set by boot code after
7106 * reset.
7107 */
7108 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7109 u32 gpio_mask;
7110
7111 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7112 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7113 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7114
7115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7116 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7117 GRC_LCLCTRL_GPIO_OUTPUT3;
7118
7119 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7120 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7121
7122 tp->grc_local_ctrl &= ~gpio_mask;
7123 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7124
7125 /* GPIO1 must be driven high for eeprom write protect */
7126 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7127 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7128 GRC_LCLCTRL_GPIO_OUTPUT1);
7129 }
7130 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7131 udelay(100);
7132
7133 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7134 tp->last_tag = 0;
7135
7136 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7137 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7138 udelay(40);
7139 }
7140
7141 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7142 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7143 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7144 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7145 WDMAC_MODE_LNGREAD_ENAB);
7146
7147 /* If statement applies to 5705 and 5750 PCI devices only */
7148 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7149 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7150 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7151 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7152 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7153 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7154 /* nothing */
7155 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7156 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7157 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7158 val |= WDMAC_MODE_RX_ACCEL;
7159 }
7160 }
7161
7162 /* Enable host coalescing bug fix */
7163 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7164 val |= WDMAC_MODE_STATUS_TAG_FIX;
7165
7166 tw32_f(WDMAC_MODE, val);
7167 udelay(40);
7168
7169 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7170 u16 pcix_cmd;
7171
7172 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7173 &pcix_cmd);
7174 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7175 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7176 pcix_cmd |= PCI_X_CMD_READ_2K;
7177 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7178 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7179 pcix_cmd |= PCI_X_CMD_READ_2K;
7180 }
7181 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7182 pcix_cmd);
7183 }
7184
7185 tw32_f(RDMAC_MODE, rdmac_mode);
7186 udelay(40);
7187
7188 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7189 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7190 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7191
7192 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7193 tw32(SNDDATAC_MODE,
7194 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7195 else
7196 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7197
7198 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7199 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7200 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7201 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7202 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7203 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7204 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7205 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7206
7207 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7208 err = tg3_load_5701_a0_firmware_fix(tp);
7209 if (err)
7210 return err;
7211 }
7212
7213 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7214 err = tg3_load_tso_firmware(tp);
7215 if (err)
7216 return err;
7217 }
7218
7219 tp->tx_mode = TX_MODE_ENABLE;
7220 tw32_f(MAC_TX_MODE, tp->tx_mode);
7221 udelay(100);
7222
7223 tp->rx_mode = RX_MODE_ENABLE;
7224 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7225 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7226
7227 tw32_f(MAC_RX_MODE, tp->rx_mode);
7228 udelay(10);
7229
7230 tw32(MAC_LED_CTRL, tp->led_ctrl);
7231
7232 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7233 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7234 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7235 udelay(10);
7236 }
7237 tw32_f(MAC_RX_MODE, tp->rx_mode);
7238 udelay(10);
7239
7240 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7241 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7242 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7243 /* Set drive transmission level to 1.2V */
7244 /* only if the signal pre-emphasis bit is not set */
7245 val = tr32(MAC_SERDES_CFG);
7246 val &= 0xfffff000;
7247 val |= 0x880;
7248 tw32(MAC_SERDES_CFG, val);
7249 }
7250 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7251 tw32(MAC_SERDES_CFG, 0x616000);
7252 }
7253
7254 /* Prevent chip from dropping frames when flow control
7255 * is enabled.
7256 */
7257 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7258
7259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7260 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7261 /* Use hardware link auto-negotiation */
7262 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7263 }
7264
7265 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7266 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7267 u32 tmp;
7268
7269 tmp = tr32(SERDES_RX_CTRL);
7270 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7271 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7272 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7273 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7274 }
7275
7276 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7277 if (tp->link_config.phy_is_low_power) {
7278 tp->link_config.phy_is_low_power = 0;
7279 tp->link_config.speed = tp->link_config.orig_speed;
7280 tp->link_config.duplex = tp->link_config.orig_duplex;
7281 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7282 }
7283
7284 err = tg3_setup_phy(tp, 0);
7285 if (err)
7286 return err;
7287
7288 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7289 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7290 u32 tmp;
7291
7292 /* Clear CRC stats. */
7293 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7294 tg3_writephy(tp, MII_TG3_TEST1,
7295 tmp | MII_TG3_TEST1_CRC_EN);
7296 tg3_readphy(tp, 0x14, &tmp);
7297 }
7298 }
7299 }
7300
7301 __tg3_set_rx_mode(tp->dev);
7302
7303 /* Initialize receive rules. */
7304 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7305 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7306 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7307 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7308
7309 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7310 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7311 limit = 8;
7312 else
7313 limit = 16;
7314 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7315 limit -= 4;
7316 switch (limit) {
7317 case 16:
7318 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7319 case 15:
7320 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7321 case 14:
7322 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7323 case 13:
7324 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7325 case 12:
7326 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7327 case 11:
7328 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7329 case 10:
7330 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7331 case 9:
7332 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7333 case 8:
7334 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7335 case 7:
7336 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7337 case 6:
7338 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7339 case 5:
7340 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7341 case 4:
7342 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7343 case 3:
7344 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7345 case 2:
7346 case 1:
7347
7348 default:
7349 break;
7350 }
7351
7352 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7353 /* Write our heartbeat update interval to APE. */
7354 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7355 APE_HOST_HEARTBEAT_INT_DISABLE);
7356
7357 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7358
7359 return 0;
7360 }
7361
7362 /* Called at device open time to get the chip ready for
7363 * packet processing. Invoked with tp->lock held.
7364 */
7365 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7366 {
7367 tg3_switch_clocks(tp);
7368
7369 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7370
7371 return tg3_reset_hw(tp, reset_phy);
7372 }
7373
7374 #define TG3_STAT_ADD32(PSTAT, REG) \
7375 do { u32 __val = tr32(REG); \
7376 (PSTAT)->low += __val; \
7377 if ((PSTAT)->low < __val) \
7378 (PSTAT)->high += 1; \
7379 } while (0)
7380
7381 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7382 {
7383 struct tg3_hw_stats *sp = tp->hw_stats;
7384
7385 if (!netif_carrier_ok(tp->dev))
7386 return;
7387
7388 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7389 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7390 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7391 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7392 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7393 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7394 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7395 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7396 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7397 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7398 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7399 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7400 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7401
7402 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7403 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7404 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7405 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7406 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7407 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7408 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7409 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7410 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7411 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7412 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7413 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7414 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7415 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7416
7417 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7418 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7419 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7420 }
7421
7422 static void tg3_timer(unsigned long __opaque)
7423 {
7424 struct tg3 *tp = (struct tg3 *) __opaque;
7425
7426 if (tp->irq_sync)
7427 goto restart_timer;
7428
7429 spin_lock(&tp->lock);
7430
7431 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7432 /* All of this garbage is because when using non-tagged
7433 * IRQ status the mailbox/status_block protocol the chip
7434 * uses with the cpu is race prone.
7435 */
7436 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7437 tw32(GRC_LOCAL_CTRL,
7438 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7439 } else {
7440 tw32(HOSTCC_MODE, tp->coalesce_mode |
7441 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7442 }
7443
7444 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7445 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7446 spin_unlock(&tp->lock);
7447 schedule_work(&tp->reset_task);
7448 return;
7449 }
7450 }
7451
7452 /* This part only runs once per second. */
7453 if (!--tp->timer_counter) {
7454 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7455 tg3_periodic_fetch_stats(tp);
7456
7457 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7458 u32 mac_stat;
7459 int phy_event;
7460
7461 mac_stat = tr32(MAC_STATUS);
7462
7463 phy_event = 0;
7464 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7465 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7466 phy_event = 1;
7467 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7468 phy_event = 1;
7469
7470 if (phy_event)
7471 tg3_setup_phy(tp, 0);
7472 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7473 u32 mac_stat = tr32(MAC_STATUS);
7474 int need_setup = 0;
7475
7476 if (netif_carrier_ok(tp->dev) &&
7477 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7478 need_setup = 1;
7479 }
7480 if (! netif_carrier_ok(tp->dev) &&
7481 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7482 MAC_STATUS_SIGNAL_DET))) {
7483 need_setup = 1;
7484 }
7485 if (need_setup) {
7486 if (!tp->serdes_counter) {
7487 tw32_f(MAC_MODE,
7488 (tp->mac_mode &
7489 ~MAC_MODE_PORT_MODE_MASK));
7490 udelay(40);
7491 tw32_f(MAC_MODE, tp->mac_mode);
7492 udelay(40);
7493 }
7494 tg3_setup_phy(tp, 0);
7495 }
7496 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7497 tg3_serdes_parallel_detect(tp);
7498
7499 tp->timer_counter = tp->timer_multiplier;
7500 }
7501
7502 /* Heartbeat is only sent once every 2 seconds.
7503 *
7504 * The heartbeat is to tell the ASF firmware that the host
7505 * driver is still alive. In the event that the OS crashes,
7506 * ASF needs to reset the hardware to free up the FIFO space
7507 * that may be filled with rx packets destined for the host.
7508 * If the FIFO is full, ASF will no longer function properly.
7509 *
7510 * Unintended resets have been reported on real time kernels
7511 * where the timer doesn't run on time. Netpoll will also have
7512 * same problem.
7513 *
7514 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7515 * to check the ring condition when the heartbeat is expiring
7516 * before doing the reset. This will prevent most unintended
7517 * resets.
7518 */
7519 if (!--tp->asf_counter) {
7520 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7521 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7522 tg3_wait_for_event_ack(tp);
7523
7524 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7525 FWCMD_NICDRV_ALIVE3);
7526 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7527 /* 5 seconds timeout */
7528 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7529
7530 tg3_generate_fw_event(tp);
7531 }
7532 tp->asf_counter = tp->asf_multiplier;
7533 }
7534
7535 spin_unlock(&tp->lock);
7536
7537 restart_timer:
7538 tp->timer.expires = jiffies + tp->timer_offset;
7539 add_timer(&tp->timer);
7540 }
7541
7542 static int tg3_request_irq(struct tg3 *tp)
7543 {
7544 irq_handler_t fn;
7545 unsigned long flags;
7546 struct net_device *dev = tp->dev;
7547
7548 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7549 fn = tg3_msi;
7550 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7551 fn = tg3_msi_1shot;
7552 flags = IRQF_SAMPLE_RANDOM;
7553 } else {
7554 fn = tg3_interrupt;
7555 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7556 fn = tg3_interrupt_tagged;
7557 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7558 }
7559 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7560 }
7561
7562 static int tg3_test_interrupt(struct tg3 *tp)
7563 {
7564 struct net_device *dev = tp->dev;
7565 int err, i, intr_ok = 0;
7566
7567 if (!netif_running(dev))
7568 return -ENODEV;
7569
7570 tg3_disable_ints(tp);
7571
7572 free_irq(tp->pdev->irq, dev);
7573
7574 err = request_irq(tp->pdev->irq, tg3_test_isr,
7575 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7576 if (err)
7577 return err;
7578
7579 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7580 tg3_enable_ints(tp);
7581
7582 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7583 HOSTCC_MODE_NOW);
7584
7585 for (i = 0; i < 5; i++) {
7586 u32 int_mbox, misc_host_ctrl;
7587
7588 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7589 TG3_64BIT_REG_LOW);
7590 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7591
7592 if ((int_mbox != 0) ||
7593 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7594 intr_ok = 1;
7595 break;
7596 }
7597
7598 msleep(10);
7599 }
7600
7601 tg3_disable_ints(tp);
7602
7603 free_irq(tp->pdev->irq, dev);
7604
7605 err = tg3_request_irq(tp);
7606
7607 if (err)
7608 return err;
7609
7610 if (intr_ok)
7611 return 0;
7612
7613 return -EIO;
7614 }
7615
7616 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7617 * successfully restored
7618 */
7619 static int tg3_test_msi(struct tg3 *tp)
7620 {
7621 struct net_device *dev = tp->dev;
7622 int err;
7623 u16 pci_cmd;
7624
7625 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7626 return 0;
7627
7628 /* Turn off SERR reporting in case MSI terminates with Master
7629 * Abort.
7630 */
7631 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7632 pci_write_config_word(tp->pdev, PCI_COMMAND,
7633 pci_cmd & ~PCI_COMMAND_SERR);
7634
7635 err = tg3_test_interrupt(tp);
7636
7637 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7638
7639 if (!err)
7640 return 0;
7641
7642 /* other failures */
7643 if (err != -EIO)
7644 return err;
7645
7646 /* MSI test failed, go back to INTx mode */
7647 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7648 "switching to INTx mode. Please report this failure to "
7649 "the PCI maintainer and include system chipset information.\n",
7650 tp->dev->name);
7651
7652 free_irq(tp->pdev->irq, dev);
7653 pci_disable_msi(tp->pdev);
7654
7655 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7656
7657 err = tg3_request_irq(tp);
7658 if (err)
7659 return err;
7660
7661 /* Need to reset the chip because the MSI cycle may have terminated
7662 * with Master Abort.
7663 */
7664 tg3_full_lock(tp, 1);
7665
7666 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7667 err = tg3_init_hw(tp, 1);
7668
7669 tg3_full_unlock(tp);
7670
7671 if (err)
7672 free_irq(tp->pdev->irq, dev);
7673
7674 return err;
7675 }
7676
7677 static int tg3_request_firmware(struct tg3 *tp)
7678 {
7679 const __be32 *fw_data;
7680
7681 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7682 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7683 tp->dev->name, tp->fw_needed);
7684 return -ENOENT;
7685 }
7686
7687 fw_data = (void *)tp->fw->data;
7688
7689 /* Firmware blob starts with version numbers, followed by
7690 * start address and _full_ length including BSS sections
7691 * (which must be longer than the actual data, of course
7692 */
7693
7694 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7695 if (tp->fw_len < (tp->fw->size - 12)) {
7696 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7697 tp->dev->name, tp->fw_len, tp->fw_needed);
7698 release_firmware(tp->fw);
7699 tp->fw = NULL;
7700 return -EINVAL;
7701 }
7702
7703 /* We no longer need firmware; we have it. */
7704 tp->fw_needed = NULL;
7705 return 0;
7706 }
7707
7708 static int tg3_open(struct net_device *dev)
7709 {
7710 struct tg3 *tp = netdev_priv(dev);
7711 int err;
7712
7713 if (tp->fw_needed) {
7714 err = tg3_request_firmware(tp);
7715 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7716 if (err)
7717 return err;
7718 } else if (err) {
7719 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7720 tp->dev->name);
7721 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7722 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7723 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7724 tp->dev->name);
7725 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7726 }
7727 }
7728
7729 netif_carrier_off(tp->dev);
7730
7731 err = tg3_set_power_state(tp, PCI_D0);
7732 if (err)
7733 return err;
7734
7735 tg3_full_lock(tp, 0);
7736
7737 tg3_disable_ints(tp);
7738 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7739
7740 tg3_full_unlock(tp);
7741
7742 /* The placement of this call is tied
7743 * to the setup and use of Host TX descriptors.
7744 */
7745 err = tg3_alloc_consistent(tp);
7746 if (err)
7747 return err;
7748
7749 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7750 /* All MSI supporting chips should support tagged
7751 * status. Assert that this is the case.
7752 */
7753 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7754 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7755 "Not using MSI.\n", tp->dev->name);
7756 } else if (pci_enable_msi(tp->pdev) == 0) {
7757 u32 msi_mode;
7758
7759 msi_mode = tr32(MSGINT_MODE);
7760 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7761 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7762 }
7763 }
7764 err = tg3_request_irq(tp);
7765
7766 if (err) {
7767 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7768 pci_disable_msi(tp->pdev);
7769 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7770 }
7771 tg3_free_consistent(tp);
7772 return err;
7773 }
7774
7775 napi_enable(&tp->napi);
7776
7777 tg3_full_lock(tp, 0);
7778
7779 err = tg3_init_hw(tp, 1);
7780 if (err) {
7781 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7782 tg3_free_rings(tp);
7783 } else {
7784 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7785 tp->timer_offset = HZ;
7786 else
7787 tp->timer_offset = HZ / 10;
7788
7789 BUG_ON(tp->timer_offset > HZ);
7790 tp->timer_counter = tp->timer_multiplier =
7791 (HZ / tp->timer_offset);
7792 tp->asf_counter = tp->asf_multiplier =
7793 ((HZ / tp->timer_offset) * 2);
7794
7795 init_timer(&tp->timer);
7796 tp->timer.expires = jiffies + tp->timer_offset;
7797 tp->timer.data = (unsigned long) tp;
7798 tp->timer.function = tg3_timer;
7799 }
7800
7801 tg3_full_unlock(tp);
7802
7803 if (err) {
7804 napi_disable(&tp->napi);
7805 free_irq(tp->pdev->irq, dev);
7806 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7807 pci_disable_msi(tp->pdev);
7808 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7809 }
7810 tg3_free_consistent(tp);
7811 return err;
7812 }
7813
7814 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7815 err = tg3_test_msi(tp);
7816
7817 if (err) {
7818 tg3_full_lock(tp, 0);
7819
7820 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7821 pci_disable_msi(tp->pdev);
7822 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7823 }
7824 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7825 tg3_free_rings(tp);
7826 tg3_free_consistent(tp);
7827
7828 tg3_full_unlock(tp);
7829
7830 napi_disable(&tp->napi);
7831
7832 return err;
7833 }
7834
7835 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7836 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7837 u32 val = tr32(PCIE_TRANSACTION_CFG);
7838
7839 tw32(PCIE_TRANSACTION_CFG,
7840 val | PCIE_TRANS_CFG_1SHOT_MSI);
7841 }
7842 }
7843 }
7844
7845 tg3_phy_start(tp);
7846
7847 tg3_full_lock(tp, 0);
7848
7849 add_timer(&tp->timer);
7850 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7851 tg3_enable_ints(tp);
7852
7853 tg3_full_unlock(tp);
7854
7855 netif_start_queue(dev);
7856
7857 return 0;
7858 }
7859
7860 #if 0
7861 /*static*/ void tg3_dump_state(struct tg3 *tp)
7862 {
7863 u32 val32, val32_2, val32_3, val32_4, val32_5;
7864 u16 val16;
7865 int i;
7866
7867 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7868 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7869 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7870 val16, val32);
7871
7872 /* MAC block */
7873 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7874 tr32(MAC_MODE), tr32(MAC_STATUS));
7875 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7876 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7877 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7878 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7879 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7880 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7881
7882 /* Send data initiator control block */
7883 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7884 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7885 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7886 tr32(SNDDATAI_STATSCTRL));
7887
7888 /* Send data completion control block */
7889 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7890
7891 /* Send BD ring selector block */
7892 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7893 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7894
7895 /* Send BD initiator control block */
7896 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7897 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7898
7899 /* Send BD completion control block */
7900 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7901
7902 /* Receive list placement control block */
7903 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7904 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7905 printk(" RCVLPC_STATSCTRL[%08x]\n",
7906 tr32(RCVLPC_STATSCTRL));
7907
7908 /* Receive data and receive BD initiator control block */
7909 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7910 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7911
7912 /* Receive data completion control block */
7913 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7914 tr32(RCVDCC_MODE));
7915
7916 /* Receive BD initiator control block */
7917 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7918 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7919
7920 /* Receive BD completion control block */
7921 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7922 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7923
7924 /* Receive list selector control block */
7925 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7926 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7927
7928 /* Mbuf cluster free block */
7929 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7930 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7931
7932 /* Host coalescing control block */
7933 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7934 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7935 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7936 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7937 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7938 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7939 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7940 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7941 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7942 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7943 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7944 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7945
7946 /* Memory arbiter control block */
7947 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7948 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7949
7950 /* Buffer manager control block */
7951 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7952 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7953 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7954 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7955 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7956 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7957 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7958 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7959
7960 /* Read DMA control block */
7961 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7962 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7963
7964 /* Write DMA control block */
7965 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7966 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7967
7968 /* DMA completion block */
7969 printk("DEBUG: DMAC_MODE[%08x]\n",
7970 tr32(DMAC_MODE));
7971
7972 /* GRC block */
7973 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7974 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7975 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7976 tr32(GRC_LOCAL_CTRL));
7977
7978 /* TG3_BDINFOs */
7979 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7980 tr32(RCVDBDI_JUMBO_BD + 0x0),
7981 tr32(RCVDBDI_JUMBO_BD + 0x4),
7982 tr32(RCVDBDI_JUMBO_BD + 0x8),
7983 tr32(RCVDBDI_JUMBO_BD + 0xc));
7984 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7985 tr32(RCVDBDI_STD_BD + 0x0),
7986 tr32(RCVDBDI_STD_BD + 0x4),
7987 tr32(RCVDBDI_STD_BD + 0x8),
7988 tr32(RCVDBDI_STD_BD + 0xc));
7989 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7990 tr32(RCVDBDI_MINI_BD + 0x0),
7991 tr32(RCVDBDI_MINI_BD + 0x4),
7992 tr32(RCVDBDI_MINI_BD + 0x8),
7993 tr32(RCVDBDI_MINI_BD + 0xc));
7994
7995 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7996 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7997 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7998 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7999 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8000 val32, val32_2, val32_3, val32_4);
8001
8002 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8003 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8004 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8005 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8006 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8007 val32, val32_2, val32_3, val32_4);
8008
8009 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8010 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8011 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8012 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8013 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8014 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8015 val32, val32_2, val32_3, val32_4, val32_5);
8016
8017 /* SW status block */
8018 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8019 tp->hw_status->status,
8020 tp->hw_status->status_tag,
8021 tp->hw_status->rx_jumbo_consumer,
8022 tp->hw_status->rx_consumer,
8023 tp->hw_status->rx_mini_consumer,
8024 tp->hw_status->idx[0].rx_producer,
8025 tp->hw_status->idx[0].tx_consumer);
8026
8027 /* SW statistics block */
8028 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8029 ((u32 *)tp->hw_stats)[0],
8030 ((u32 *)tp->hw_stats)[1],
8031 ((u32 *)tp->hw_stats)[2],
8032 ((u32 *)tp->hw_stats)[3]);
8033
8034 /* Mailboxes */
8035 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8036 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8037 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8038 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8039 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8040
8041 /* NIC side send descriptors. */
8042 for (i = 0; i < 6; i++) {
8043 unsigned long txd;
8044
8045 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8046 + (i * sizeof(struct tg3_tx_buffer_desc));
8047 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8048 i,
8049 readl(txd + 0x0), readl(txd + 0x4),
8050 readl(txd + 0x8), readl(txd + 0xc));
8051 }
8052
8053 /* NIC side RX descriptors. */
8054 for (i = 0; i < 6; i++) {
8055 unsigned long rxd;
8056
8057 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8058 + (i * sizeof(struct tg3_rx_buffer_desc));
8059 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8060 i,
8061 readl(rxd + 0x0), readl(rxd + 0x4),
8062 readl(rxd + 0x8), readl(rxd + 0xc));
8063 rxd += (4 * sizeof(u32));
8064 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8065 i,
8066 readl(rxd + 0x0), readl(rxd + 0x4),
8067 readl(rxd + 0x8), readl(rxd + 0xc));
8068 }
8069
8070 for (i = 0; i < 6; i++) {
8071 unsigned long rxd;
8072
8073 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8074 + (i * sizeof(struct tg3_rx_buffer_desc));
8075 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8076 i,
8077 readl(rxd + 0x0), readl(rxd + 0x4),
8078 readl(rxd + 0x8), readl(rxd + 0xc));
8079 rxd += (4 * sizeof(u32));
8080 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8081 i,
8082 readl(rxd + 0x0), readl(rxd + 0x4),
8083 readl(rxd + 0x8), readl(rxd + 0xc));
8084 }
8085 }
8086 #endif
8087
8088 static struct net_device_stats *tg3_get_stats(struct net_device *);
8089 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8090
8091 static int tg3_close(struct net_device *dev)
8092 {
8093 struct tg3 *tp = netdev_priv(dev);
8094
8095 napi_disable(&tp->napi);
8096 cancel_work_sync(&tp->reset_task);
8097
8098 netif_stop_queue(dev);
8099
8100 del_timer_sync(&tp->timer);
8101
8102 tg3_full_lock(tp, 1);
8103 #if 0
8104 tg3_dump_state(tp);
8105 #endif
8106
8107 tg3_disable_ints(tp);
8108
8109 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8110 tg3_free_rings(tp);
8111 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8112
8113 tg3_full_unlock(tp);
8114
8115 free_irq(tp->pdev->irq, dev);
8116 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8117 pci_disable_msi(tp->pdev);
8118 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8119 }
8120
8121 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8122 sizeof(tp->net_stats_prev));
8123 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8124 sizeof(tp->estats_prev));
8125
8126 tg3_free_consistent(tp);
8127
8128 tg3_set_power_state(tp, PCI_D3hot);
8129
8130 netif_carrier_off(tp->dev);
8131
8132 return 0;
8133 }
8134
8135 static inline unsigned long get_stat64(tg3_stat64_t *val)
8136 {
8137 unsigned long ret;
8138
8139 #if (BITS_PER_LONG == 32)
8140 ret = val->low;
8141 #else
8142 ret = ((u64)val->high << 32) | ((u64)val->low);
8143 #endif
8144 return ret;
8145 }
8146
8147 static inline u64 get_estat64(tg3_stat64_t *val)
8148 {
8149 return ((u64)val->high << 32) | ((u64)val->low);
8150 }
8151
8152 static unsigned long calc_crc_errors(struct tg3 *tp)
8153 {
8154 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8155
8156 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8157 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8158 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8159 u32 val;
8160
8161 spin_lock_bh(&tp->lock);
8162 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8163 tg3_writephy(tp, MII_TG3_TEST1,
8164 val | MII_TG3_TEST1_CRC_EN);
8165 tg3_readphy(tp, 0x14, &val);
8166 } else
8167 val = 0;
8168 spin_unlock_bh(&tp->lock);
8169
8170 tp->phy_crc_errors += val;
8171
8172 return tp->phy_crc_errors;
8173 }
8174
8175 return get_stat64(&hw_stats->rx_fcs_errors);
8176 }
8177
8178 #define ESTAT_ADD(member) \
8179 estats->member = old_estats->member + \
8180 get_estat64(&hw_stats->member)
8181
8182 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8183 {
8184 struct tg3_ethtool_stats *estats = &tp->estats;
8185 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8186 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8187
8188 if (!hw_stats)
8189 return old_estats;
8190
8191 ESTAT_ADD(rx_octets);
8192 ESTAT_ADD(rx_fragments);
8193 ESTAT_ADD(rx_ucast_packets);
8194 ESTAT_ADD(rx_mcast_packets);
8195 ESTAT_ADD(rx_bcast_packets);
8196 ESTAT_ADD(rx_fcs_errors);
8197 ESTAT_ADD(rx_align_errors);
8198 ESTAT_ADD(rx_xon_pause_rcvd);
8199 ESTAT_ADD(rx_xoff_pause_rcvd);
8200 ESTAT_ADD(rx_mac_ctrl_rcvd);
8201 ESTAT_ADD(rx_xoff_entered);
8202 ESTAT_ADD(rx_frame_too_long_errors);
8203 ESTAT_ADD(rx_jabbers);
8204 ESTAT_ADD(rx_undersize_packets);
8205 ESTAT_ADD(rx_in_length_errors);
8206 ESTAT_ADD(rx_out_length_errors);
8207 ESTAT_ADD(rx_64_or_less_octet_packets);
8208 ESTAT_ADD(rx_65_to_127_octet_packets);
8209 ESTAT_ADD(rx_128_to_255_octet_packets);
8210 ESTAT_ADD(rx_256_to_511_octet_packets);
8211 ESTAT_ADD(rx_512_to_1023_octet_packets);
8212 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8213 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8214 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8215 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8216 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8217
8218 ESTAT_ADD(tx_octets);
8219 ESTAT_ADD(tx_collisions);
8220 ESTAT_ADD(tx_xon_sent);
8221 ESTAT_ADD(tx_xoff_sent);
8222 ESTAT_ADD(tx_flow_control);
8223 ESTAT_ADD(tx_mac_errors);
8224 ESTAT_ADD(tx_single_collisions);
8225 ESTAT_ADD(tx_mult_collisions);
8226 ESTAT_ADD(tx_deferred);
8227 ESTAT_ADD(tx_excessive_collisions);
8228 ESTAT_ADD(tx_late_collisions);
8229 ESTAT_ADD(tx_collide_2times);
8230 ESTAT_ADD(tx_collide_3times);
8231 ESTAT_ADD(tx_collide_4times);
8232 ESTAT_ADD(tx_collide_5times);
8233 ESTAT_ADD(tx_collide_6times);
8234 ESTAT_ADD(tx_collide_7times);
8235 ESTAT_ADD(tx_collide_8times);
8236 ESTAT_ADD(tx_collide_9times);
8237 ESTAT_ADD(tx_collide_10times);
8238 ESTAT_ADD(tx_collide_11times);
8239 ESTAT_ADD(tx_collide_12times);
8240 ESTAT_ADD(tx_collide_13times);
8241 ESTAT_ADD(tx_collide_14times);
8242 ESTAT_ADD(tx_collide_15times);
8243 ESTAT_ADD(tx_ucast_packets);
8244 ESTAT_ADD(tx_mcast_packets);
8245 ESTAT_ADD(tx_bcast_packets);
8246 ESTAT_ADD(tx_carrier_sense_errors);
8247 ESTAT_ADD(tx_discards);
8248 ESTAT_ADD(tx_errors);
8249
8250 ESTAT_ADD(dma_writeq_full);
8251 ESTAT_ADD(dma_write_prioq_full);
8252 ESTAT_ADD(rxbds_empty);
8253 ESTAT_ADD(rx_discards);
8254 ESTAT_ADD(rx_errors);
8255 ESTAT_ADD(rx_threshold_hit);
8256
8257 ESTAT_ADD(dma_readq_full);
8258 ESTAT_ADD(dma_read_prioq_full);
8259 ESTAT_ADD(tx_comp_queue_full);
8260
8261 ESTAT_ADD(ring_set_send_prod_index);
8262 ESTAT_ADD(ring_status_update);
8263 ESTAT_ADD(nic_irqs);
8264 ESTAT_ADD(nic_avoided_irqs);
8265 ESTAT_ADD(nic_tx_threshold_hit);
8266
8267 return estats;
8268 }
8269
8270 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8271 {
8272 struct tg3 *tp = netdev_priv(dev);
8273 struct net_device_stats *stats = &tp->net_stats;
8274 struct net_device_stats *old_stats = &tp->net_stats_prev;
8275 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8276
8277 if (!hw_stats)
8278 return old_stats;
8279
8280 stats->rx_packets = old_stats->rx_packets +
8281 get_stat64(&hw_stats->rx_ucast_packets) +
8282 get_stat64(&hw_stats->rx_mcast_packets) +
8283 get_stat64(&hw_stats->rx_bcast_packets);
8284
8285 stats->tx_packets = old_stats->tx_packets +
8286 get_stat64(&hw_stats->tx_ucast_packets) +
8287 get_stat64(&hw_stats->tx_mcast_packets) +
8288 get_stat64(&hw_stats->tx_bcast_packets);
8289
8290 stats->rx_bytes = old_stats->rx_bytes +
8291 get_stat64(&hw_stats->rx_octets);
8292 stats->tx_bytes = old_stats->tx_bytes +
8293 get_stat64(&hw_stats->tx_octets);
8294
8295 stats->rx_errors = old_stats->rx_errors +
8296 get_stat64(&hw_stats->rx_errors);
8297 stats->tx_errors = old_stats->tx_errors +
8298 get_stat64(&hw_stats->tx_errors) +
8299 get_stat64(&hw_stats->tx_mac_errors) +
8300 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8301 get_stat64(&hw_stats->tx_discards);
8302
8303 stats->multicast = old_stats->multicast +
8304 get_stat64(&hw_stats->rx_mcast_packets);
8305 stats->collisions = old_stats->collisions +
8306 get_stat64(&hw_stats->tx_collisions);
8307
8308 stats->rx_length_errors = old_stats->rx_length_errors +
8309 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8310 get_stat64(&hw_stats->rx_undersize_packets);
8311
8312 stats->rx_over_errors = old_stats->rx_over_errors +
8313 get_stat64(&hw_stats->rxbds_empty);
8314 stats->rx_frame_errors = old_stats->rx_frame_errors +
8315 get_stat64(&hw_stats->rx_align_errors);
8316 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8317 get_stat64(&hw_stats->tx_discards);
8318 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8319 get_stat64(&hw_stats->tx_carrier_sense_errors);
8320
8321 stats->rx_crc_errors = old_stats->rx_crc_errors +
8322 calc_crc_errors(tp);
8323
8324 stats->rx_missed_errors = old_stats->rx_missed_errors +
8325 get_stat64(&hw_stats->rx_discards);
8326
8327 return stats;
8328 }
8329
8330 static inline u32 calc_crc(unsigned char *buf, int len)
8331 {
8332 u32 reg;
8333 u32 tmp;
8334 int j, k;
8335
8336 reg = 0xffffffff;
8337
8338 for (j = 0; j < len; j++) {
8339 reg ^= buf[j];
8340
8341 for (k = 0; k < 8; k++) {
8342 tmp = reg & 0x01;
8343
8344 reg >>= 1;
8345
8346 if (tmp) {
8347 reg ^= 0xedb88320;
8348 }
8349 }
8350 }
8351
8352 return ~reg;
8353 }
8354
8355 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8356 {
8357 /* accept or reject all multicast frames */
8358 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8359 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8360 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8361 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8362 }
8363
8364 static void __tg3_set_rx_mode(struct net_device *dev)
8365 {
8366 struct tg3 *tp = netdev_priv(dev);
8367 u32 rx_mode;
8368
8369 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8370 RX_MODE_KEEP_VLAN_TAG);
8371
8372 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8373 * flag clear.
8374 */
8375 #if TG3_VLAN_TAG_USED
8376 if (!tp->vlgrp &&
8377 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8378 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8379 #else
8380 /* By definition, VLAN is disabled always in this
8381 * case.
8382 */
8383 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8384 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8385 #endif
8386
8387 if (dev->flags & IFF_PROMISC) {
8388 /* Promiscuous mode. */
8389 rx_mode |= RX_MODE_PROMISC;
8390 } else if (dev->flags & IFF_ALLMULTI) {
8391 /* Accept all multicast. */
8392 tg3_set_multi (tp, 1);
8393 } else if (dev->mc_count < 1) {
8394 /* Reject all multicast. */
8395 tg3_set_multi (tp, 0);
8396 } else {
8397 /* Accept one or more multicast(s). */
8398 struct dev_mc_list *mclist;
8399 unsigned int i;
8400 u32 mc_filter[4] = { 0, };
8401 u32 regidx;
8402 u32 bit;
8403 u32 crc;
8404
8405 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8406 i++, mclist = mclist->next) {
8407
8408 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8409 bit = ~crc & 0x7f;
8410 regidx = (bit & 0x60) >> 5;
8411 bit &= 0x1f;
8412 mc_filter[regidx] |= (1 << bit);
8413 }
8414
8415 tw32(MAC_HASH_REG_0, mc_filter[0]);
8416 tw32(MAC_HASH_REG_1, mc_filter[1]);
8417 tw32(MAC_HASH_REG_2, mc_filter[2]);
8418 tw32(MAC_HASH_REG_3, mc_filter[3]);
8419 }
8420
8421 if (rx_mode != tp->rx_mode) {
8422 tp->rx_mode = rx_mode;
8423 tw32_f(MAC_RX_MODE, rx_mode);
8424 udelay(10);
8425 }
8426 }
8427
8428 static void tg3_set_rx_mode(struct net_device *dev)
8429 {
8430 struct tg3 *tp = netdev_priv(dev);
8431
8432 if (!netif_running(dev))
8433 return;
8434
8435 tg3_full_lock(tp, 0);
8436 __tg3_set_rx_mode(dev);
8437 tg3_full_unlock(tp);
8438 }
8439
8440 #define TG3_REGDUMP_LEN (32 * 1024)
8441
8442 static int tg3_get_regs_len(struct net_device *dev)
8443 {
8444 return TG3_REGDUMP_LEN;
8445 }
8446
8447 static void tg3_get_regs(struct net_device *dev,
8448 struct ethtool_regs *regs, void *_p)
8449 {
8450 u32 *p = _p;
8451 struct tg3 *tp = netdev_priv(dev);
8452 u8 *orig_p = _p;
8453 int i;
8454
8455 regs->version = 0;
8456
8457 memset(p, 0, TG3_REGDUMP_LEN);
8458
8459 if (tp->link_config.phy_is_low_power)
8460 return;
8461
8462 tg3_full_lock(tp, 0);
8463
8464 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8465 #define GET_REG32_LOOP(base,len) \
8466 do { p = (u32 *)(orig_p + (base)); \
8467 for (i = 0; i < len; i += 4) \
8468 __GET_REG32((base) + i); \
8469 } while (0)
8470 #define GET_REG32_1(reg) \
8471 do { p = (u32 *)(orig_p + (reg)); \
8472 __GET_REG32((reg)); \
8473 } while (0)
8474
8475 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8476 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8477 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8478 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8479 GET_REG32_1(SNDDATAC_MODE);
8480 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8481 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8482 GET_REG32_1(SNDBDC_MODE);
8483 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8484 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8485 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8486 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8487 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8488 GET_REG32_1(RCVDCC_MODE);
8489 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8490 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8491 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8492 GET_REG32_1(MBFREE_MODE);
8493 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8494 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8495 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8496 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8497 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8498 GET_REG32_1(RX_CPU_MODE);
8499 GET_REG32_1(RX_CPU_STATE);
8500 GET_REG32_1(RX_CPU_PGMCTR);
8501 GET_REG32_1(RX_CPU_HWBKPT);
8502 GET_REG32_1(TX_CPU_MODE);
8503 GET_REG32_1(TX_CPU_STATE);
8504 GET_REG32_1(TX_CPU_PGMCTR);
8505 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8506 GET_REG32_LOOP(FTQ_RESET, 0x120);
8507 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8508 GET_REG32_1(DMAC_MODE);
8509 GET_REG32_LOOP(GRC_MODE, 0x4c);
8510 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8511 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8512
8513 #undef __GET_REG32
8514 #undef GET_REG32_LOOP
8515 #undef GET_REG32_1
8516
8517 tg3_full_unlock(tp);
8518 }
8519
8520 static int tg3_get_eeprom_len(struct net_device *dev)
8521 {
8522 struct tg3 *tp = netdev_priv(dev);
8523
8524 return tp->nvram_size;
8525 }
8526
8527 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8528 {
8529 struct tg3 *tp = netdev_priv(dev);
8530 int ret;
8531 u8 *pd;
8532 u32 i, offset, len, b_offset, b_count;
8533 __be32 val;
8534
8535 if (tp->link_config.phy_is_low_power)
8536 return -EAGAIN;
8537
8538 offset = eeprom->offset;
8539 len = eeprom->len;
8540 eeprom->len = 0;
8541
8542 eeprom->magic = TG3_EEPROM_MAGIC;
8543
8544 if (offset & 3) {
8545 /* adjustments to start on required 4 byte boundary */
8546 b_offset = offset & 3;
8547 b_count = 4 - b_offset;
8548 if (b_count > len) {
8549 /* i.e. offset=1 len=2 */
8550 b_count = len;
8551 }
8552 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8553 if (ret)
8554 return ret;
8555 memcpy(data, ((char*)&val) + b_offset, b_count);
8556 len -= b_count;
8557 offset += b_count;
8558 eeprom->len += b_count;
8559 }
8560
8561 /* read bytes upto the last 4 byte boundary */
8562 pd = &data[eeprom->len];
8563 for (i = 0; i < (len - (len & 3)); i += 4) {
8564 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8565 if (ret) {
8566 eeprom->len += i;
8567 return ret;
8568 }
8569 memcpy(pd + i, &val, 4);
8570 }
8571 eeprom->len += i;
8572
8573 if (len & 3) {
8574 /* read last bytes not ending on 4 byte boundary */
8575 pd = &data[eeprom->len];
8576 b_count = len & 3;
8577 b_offset = offset + len - b_count;
8578 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8579 if (ret)
8580 return ret;
8581 memcpy(pd, &val, b_count);
8582 eeprom->len += b_count;
8583 }
8584 return 0;
8585 }
8586
8587 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8588
8589 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8590 {
8591 struct tg3 *tp = netdev_priv(dev);
8592 int ret;
8593 u32 offset, len, b_offset, odd_len;
8594 u8 *buf;
8595 __be32 start, end;
8596
8597 if (tp->link_config.phy_is_low_power)
8598 return -EAGAIN;
8599
8600 if (eeprom->magic != TG3_EEPROM_MAGIC)
8601 return -EINVAL;
8602
8603 offset = eeprom->offset;
8604 len = eeprom->len;
8605
8606 if ((b_offset = (offset & 3))) {
8607 /* adjustments to start on required 4 byte boundary */
8608 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8609 if (ret)
8610 return ret;
8611 len += b_offset;
8612 offset &= ~3;
8613 if (len < 4)
8614 len = 4;
8615 }
8616
8617 odd_len = 0;
8618 if (len & 3) {
8619 /* adjustments to end on required 4 byte boundary */
8620 odd_len = 1;
8621 len = (len + 3) & ~3;
8622 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8623 if (ret)
8624 return ret;
8625 }
8626
8627 buf = data;
8628 if (b_offset || odd_len) {
8629 buf = kmalloc(len, GFP_KERNEL);
8630 if (!buf)
8631 return -ENOMEM;
8632 if (b_offset)
8633 memcpy(buf, &start, 4);
8634 if (odd_len)
8635 memcpy(buf+len-4, &end, 4);
8636 memcpy(buf + b_offset, data, eeprom->len);
8637 }
8638
8639 ret = tg3_nvram_write_block(tp, offset, len, buf);
8640
8641 if (buf != data)
8642 kfree(buf);
8643
8644 return ret;
8645 }
8646
8647 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8648 {
8649 struct tg3 *tp = netdev_priv(dev);
8650
8651 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8652 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8653 return -EAGAIN;
8654 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8655 }
8656
8657 cmd->supported = (SUPPORTED_Autoneg);
8658
8659 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8660 cmd->supported |= (SUPPORTED_1000baseT_Half |
8661 SUPPORTED_1000baseT_Full);
8662
8663 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8664 cmd->supported |= (SUPPORTED_100baseT_Half |
8665 SUPPORTED_100baseT_Full |
8666 SUPPORTED_10baseT_Half |
8667 SUPPORTED_10baseT_Full |
8668 SUPPORTED_TP);
8669 cmd->port = PORT_TP;
8670 } else {
8671 cmd->supported |= SUPPORTED_FIBRE;
8672 cmd->port = PORT_FIBRE;
8673 }
8674
8675 cmd->advertising = tp->link_config.advertising;
8676 if (netif_running(dev)) {
8677 cmd->speed = tp->link_config.active_speed;
8678 cmd->duplex = tp->link_config.active_duplex;
8679 }
8680 cmd->phy_address = PHY_ADDR;
8681 cmd->transceiver = XCVR_INTERNAL;
8682 cmd->autoneg = tp->link_config.autoneg;
8683 cmd->maxtxpkt = 0;
8684 cmd->maxrxpkt = 0;
8685 return 0;
8686 }
8687
8688 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8689 {
8690 struct tg3 *tp = netdev_priv(dev);
8691
8692 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8693 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8694 return -EAGAIN;
8695 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8696 }
8697
8698 if (cmd->autoneg != AUTONEG_ENABLE &&
8699 cmd->autoneg != AUTONEG_DISABLE)
8700 return -EINVAL;
8701
8702 if (cmd->autoneg == AUTONEG_DISABLE &&
8703 cmd->duplex != DUPLEX_FULL &&
8704 cmd->duplex != DUPLEX_HALF)
8705 return -EINVAL;
8706
8707 if (cmd->autoneg == AUTONEG_ENABLE) {
8708 u32 mask = ADVERTISED_Autoneg |
8709 ADVERTISED_Pause |
8710 ADVERTISED_Asym_Pause;
8711
8712 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8713 mask |= ADVERTISED_1000baseT_Half |
8714 ADVERTISED_1000baseT_Full;
8715
8716 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8717 mask |= ADVERTISED_100baseT_Half |
8718 ADVERTISED_100baseT_Full |
8719 ADVERTISED_10baseT_Half |
8720 ADVERTISED_10baseT_Full |
8721 ADVERTISED_TP;
8722 else
8723 mask |= ADVERTISED_FIBRE;
8724
8725 if (cmd->advertising & ~mask)
8726 return -EINVAL;
8727
8728 mask &= (ADVERTISED_1000baseT_Half |
8729 ADVERTISED_1000baseT_Full |
8730 ADVERTISED_100baseT_Half |
8731 ADVERTISED_100baseT_Full |
8732 ADVERTISED_10baseT_Half |
8733 ADVERTISED_10baseT_Full);
8734
8735 cmd->advertising &= mask;
8736 } else {
8737 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8738 if (cmd->speed != SPEED_1000)
8739 return -EINVAL;
8740
8741 if (cmd->duplex != DUPLEX_FULL)
8742 return -EINVAL;
8743 } else {
8744 if (cmd->speed != SPEED_100 &&
8745 cmd->speed != SPEED_10)
8746 return -EINVAL;
8747 }
8748 }
8749
8750 tg3_full_lock(tp, 0);
8751
8752 tp->link_config.autoneg = cmd->autoneg;
8753 if (cmd->autoneg == AUTONEG_ENABLE) {
8754 tp->link_config.advertising = (cmd->advertising |
8755 ADVERTISED_Autoneg);
8756 tp->link_config.speed = SPEED_INVALID;
8757 tp->link_config.duplex = DUPLEX_INVALID;
8758 } else {
8759 tp->link_config.advertising = 0;
8760 tp->link_config.speed = cmd->speed;
8761 tp->link_config.duplex = cmd->duplex;
8762 }
8763
8764 tp->link_config.orig_speed = tp->link_config.speed;
8765 tp->link_config.orig_duplex = tp->link_config.duplex;
8766 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8767
8768 if (netif_running(dev))
8769 tg3_setup_phy(tp, 1);
8770
8771 tg3_full_unlock(tp);
8772
8773 return 0;
8774 }
8775
8776 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8777 {
8778 struct tg3 *tp = netdev_priv(dev);
8779
8780 strcpy(info->driver, DRV_MODULE_NAME);
8781 strcpy(info->version, DRV_MODULE_VERSION);
8782 strcpy(info->fw_version, tp->fw_ver);
8783 strcpy(info->bus_info, pci_name(tp->pdev));
8784 }
8785
8786 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8787 {
8788 struct tg3 *tp = netdev_priv(dev);
8789
8790 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8791 device_can_wakeup(&tp->pdev->dev))
8792 wol->supported = WAKE_MAGIC;
8793 else
8794 wol->supported = 0;
8795 wol->wolopts = 0;
8796 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8797 device_can_wakeup(&tp->pdev->dev))
8798 wol->wolopts = WAKE_MAGIC;
8799 memset(&wol->sopass, 0, sizeof(wol->sopass));
8800 }
8801
8802 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8803 {
8804 struct tg3 *tp = netdev_priv(dev);
8805 struct device *dp = &tp->pdev->dev;
8806
8807 if (wol->wolopts & ~WAKE_MAGIC)
8808 return -EINVAL;
8809 if ((wol->wolopts & WAKE_MAGIC) &&
8810 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8811 return -EINVAL;
8812
8813 spin_lock_bh(&tp->lock);
8814 if (wol->wolopts & WAKE_MAGIC) {
8815 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8816 device_set_wakeup_enable(dp, true);
8817 } else {
8818 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8819 device_set_wakeup_enable(dp, false);
8820 }
8821 spin_unlock_bh(&tp->lock);
8822
8823 return 0;
8824 }
8825
8826 static u32 tg3_get_msglevel(struct net_device *dev)
8827 {
8828 struct tg3 *tp = netdev_priv(dev);
8829 return tp->msg_enable;
8830 }
8831
8832 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8833 {
8834 struct tg3 *tp = netdev_priv(dev);
8835 tp->msg_enable = value;
8836 }
8837
8838 static int tg3_set_tso(struct net_device *dev, u32 value)
8839 {
8840 struct tg3 *tp = netdev_priv(dev);
8841
8842 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8843 if (value)
8844 return -EINVAL;
8845 return 0;
8846 }
8847 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8848 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
8849 if (value) {
8850 dev->features |= NETIF_F_TSO6;
8851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8852 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8853 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
8854 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8856 dev->features |= NETIF_F_TSO_ECN;
8857 } else
8858 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8859 }
8860 return ethtool_op_set_tso(dev, value);
8861 }
8862
8863 static int tg3_nway_reset(struct net_device *dev)
8864 {
8865 struct tg3 *tp = netdev_priv(dev);
8866 int r;
8867
8868 if (!netif_running(dev))
8869 return -EAGAIN;
8870
8871 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8872 return -EINVAL;
8873
8874 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8875 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8876 return -EAGAIN;
8877 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
8878 } else {
8879 u32 bmcr;
8880
8881 spin_lock_bh(&tp->lock);
8882 r = -EINVAL;
8883 tg3_readphy(tp, MII_BMCR, &bmcr);
8884 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8885 ((bmcr & BMCR_ANENABLE) ||
8886 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8887 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8888 BMCR_ANENABLE);
8889 r = 0;
8890 }
8891 spin_unlock_bh(&tp->lock);
8892 }
8893
8894 return r;
8895 }
8896
8897 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8898 {
8899 struct tg3 *tp = netdev_priv(dev);
8900
8901 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8902 ering->rx_mini_max_pending = 0;
8903 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8904 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8905 else
8906 ering->rx_jumbo_max_pending = 0;
8907
8908 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8909
8910 ering->rx_pending = tp->rx_pending;
8911 ering->rx_mini_pending = 0;
8912 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8913 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8914 else
8915 ering->rx_jumbo_pending = 0;
8916
8917 ering->tx_pending = tp->tx_pending;
8918 }
8919
8920 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8921 {
8922 struct tg3 *tp = netdev_priv(dev);
8923 int irq_sync = 0, err = 0;
8924
8925 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8926 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8927 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8928 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8929 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8930 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8931 return -EINVAL;
8932
8933 if (netif_running(dev)) {
8934 tg3_phy_stop(tp);
8935 tg3_netif_stop(tp);
8936 irq_sync = 1;
8937 }
8938
8939 tg3_full_lock(tp, irq_sync);
8940
8941 tp->rx_pending = ering->rx_pending;
8942
8943 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8944 tp->rx_pending > 63)
8945 tp->rx_pending = 63;
8946 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8947 tp->tx_pending = ering->tx_pending;
8948
8949 if (netif_running(dev)) {
8950 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8951 err = tg3_restart_hw(tp, 1);
8952 if (!err)
8953 tg3_netif_start(tp);
8954 }
8955
8956 tg3_full_unlock(tp);
8957
8958 if (irq_sync && !err)
8959 tg3_phy_start(tp);
8960
8961 return err;
8962 }
8963
8964 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8965 {
8966 struct tg3 *tp = netdev_priv(dev);
8967
8968 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8969
8970 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8971 epause->rx_pause = 1;
8972 else
8973 epause->rx_pause = 0;
8974
8975 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8976 epause->tx_pause = 1;
8977 else
8978 epause->tx_pause = 0;
8979 }
8980
8981 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8982 {
8983 struct tg3 *tp = netdev_priv(dev);
8984 int err = 0;
8985
8986 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8987 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8988 return -EAGAIN;
8989
8990 if (epause->autoneg) {
8991 u32 newadv;
8992 struct phy_device *phydev;
8993
8994 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
8995
8996 if (epause->rx_pause) {
8997 if (epause->tx_pause)
8998 newadv = ADVERTISED_Pause;
8999 else
9000 newadv = ADVERTISED_Pause |
9001 ADVERTISED_Asym_Pause;
9002 } else if (epause->tx_pause) {
9003 newadv = ADVERTISED_Asym_Pause;
9004 } else
9005 newadv = 0;
9006
9007 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9008 u32 oldadv = phydev->advertising &
9009 (ADVERTISED_Pause |
9010 ADVERTISED_Asym_Pause);
9011 if (oldadv != newadv) {
9012 phydev->advertising &=
9013 ~(ADVERTISED_Pause |
9014 ADVERTISED_Asym_Pause);
9015 phydev->advertising |= newadv;
9016 err = phy_start_aneg(phydev);
9017 }
9018 } else {
9019 tp->link_config.advertising &=
9020 ~(ADVERTISED_Pause |
9021 ADVERTISED_Asym_Pause);
9022 tp->link_config.advertising |= newadv;
9023 }
9024 } else {
9025 if (epause->rx_pause)
9026 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9027 else
9028 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9029
9030 if (epause->tx_pause)
9031 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9032 else
9033 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9034
9035 if (netif_running(dev))
9036 tg3_setup_flow_control(tp, 0, 0);
9037 }
9038 } else {
9039 int irq_sync = 0;
9040
9041 if (netif_running(dev)) {
9042 tg3_netif_stop(tp);
9043 irq_sync = 1;
9044 }
9045
9046 tg3_full_lock(tp, irq_sync);
9047
9048 if (epause->autoneg)
9049 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9050 else
9051 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9052 if (epause->rx_pause)
9053 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9054 else
9055 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9056 if (epause->tx_pause)
9057 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9058 else
9059 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9060
9061 if (netif_running(dev)) {
9062 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9063 err = tg3_restart_hw(tp, 1);
9064 if (!err)
9065 tg3_netif_start(tp);
9066 }
9067
9068 tg3_full_unlock(tp);
9069 }
9070
9071 return err;
9072 }
9073
9074 static u32 tg3_get_rx_csum(struct net_device *dev)
9075 {
9076 struct tg3 *tp = netdev_priv(dev);
9077 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9078 }
9079
9080 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9081 {
9082 struct tg3 *tp = netdev_priv(dev);
9083
9084 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9085 if (data != 0)
9086 return -EINVAL;
9087 return 0;
9088 }
9089
9090 spin_lock_bh(&tp->lock);
9091 if (data)
9092 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9093 else
9094 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9095 spin_unlock_bh(&tp->lock);
9096
9097 return 0;
9098 }
9099
9100 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9101 {
9102 struct tg3 *tp = netdev_priv(dev);
9103
9104 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9105 if (data != 0)
9106 return -EINVAL;
9107 return 0;
9108 }
9109
9110 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9111 ethtool_op_set_tx_ipv6_csum(dev, data);
9112 else
9113 ethtool_op_set_tx_csum(dev, data);
9114
9115 return 0;
9116 }
9117
9118 static int tg3_get_sset_count (struct net_device *dev, int sset)
9119 {
9120 switch (sset) {
9121 case ETH_SS_TEST:
9122 return TG3_NUM_TEST;
9123 case ETH_SS_STATS:
9124 return TG3_NUM_STATS;
9125 default:
9126 return -EOPNOTSUPP;
9127 }
9128 }
9129
9130 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9131 {
9132 switch (stringset) {
9133 case ETH_SS_STATS:
9134 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9135 break;
9136 case ETH_SS_TEST:
9137 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9138 break;
9139 default:
9140 WARN_ON(1); /* we need a WARN() */
9141 break;
9142 }
9143 }
9144
9145 static int tg3_phys_id(struct net_device *dev, u32 data)
9146 {
9147 struct tg3 *tp = netdev_priv(dev);
9148 int i;
9149
9150 if (!netif_running(tp->dev))
9151 return -EAGAIN;
9152
9153 if (data == 0)
9154 data = UINT_MAX / 2;
9155
9156 for (i = 0; i < (data * 2); i++) {
9157 if ((i % 2) == 0)
9158 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9159 LED_CTRL_1000MBPS_ON |
9160 LED_CTRL_100MBPS_ON |
9161 LED_CTRL_10MBPS_ON |
9162 LED_CTRL_TRAFFIC_OVERRIDE |
9163 LED_CTRL_TRAFFIC_BLINK |
9164 LED_CTRL_TRAFFIC_LED);
9165
9166 else
9167 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9168 LED_CTRL_TRAFFIC_OVERRIDE);
9169
9170 if (msleep_interruptible(500))
9171 break;
9172 }
9173 tw32(MAC_LED_CTRL, tp->led_ctrl);
9174 return 0;
9175 }
9176
9177 static void tg3_get_ethtool_stats (struct net_device *dev,
9178 struct ethtool_stats *estats, u64 *tmp_stats)
9179 {
9180 struct tg3 *tp = netdev_priv(dev);
9181 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9182 }
9183
9184 #define NVRAM_TEST_SIZE 0x100
9185 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9186 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9187 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9188 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9189 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9190
9191 static int tg3_test_nvram(struct tg3 *tp)
9192 {
9193 u32 csum, magic;
9194 __be32 *buf;
9195 int i, j, k, err = 0, size;
9196
9197 if (tg3_nvram_read(tp, 0, &magic) != 0)
9198 return -EIO;
9199
9200 if (magic == TG3_EEPROM_MAGIC)
9201 size = NVRAM_TEST_SIZE;
9202 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9203 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9204 TG3_EEPROM_SB_FORMAT_1) {
9205 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9206 case TG3_EEPROM_SB_REVISION_0:
9207 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9208 break;
9209 case TG3_EEPROM_SB_REVISION_2:
9210 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9211 break;
9212 case TG3_EEPROM_SB_REVISION_3:
9213 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9214 break;
9215 default:
9216 return 0;
9217 }
9218 } else
9219 return 0;
9220 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9221 size = NVRAM_SELFBOOT_HW_SIZE;
9222 else
9223 return -EIO;
9224
9225 buf = kmalloc(size, GFP_KERNEL);
9226 if (buf == NULL)
9227 return -ENOMEM;
9228
9229 err = -EIO;
9230 for (i = 0, j = 0; i < size; i += 4, j++) {
9231 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9232 if (err)
9233 break;
9234 }
9235 if (i < size)
9236 goto out;
9237
9238 /* Selfboot format */
9239 magic = be32_to_cpu(buf[0]);
9240 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9241 TG3_EEPROM_MAGIC_FW) {
9242 u8 *buf8 = (u8 *) buf, csum8 = 0;
9243
9244 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9245 TG3_EEPROM_SB_REVISION_2) {
9246 /* For rev 2, the csum doesn't include the MBA. */
9247 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9248 csum8 += buf8[i];
9249 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9250 csum8 += buf8[i];
9251 } else {
9252 for (i = 0; i < size; i++)
9253 csum8 += buf8[i];
9254 }
9255
9256 if (csum8 == 0) {
9257 err = 0;
9258 goto out;
9259 }
9260
9261 err = -EIO;
9262 goto out;
9263 }
9264
9265 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9266 TG3_EEPROM_MAGIC_HW) {
9267 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9268 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9269 u8 *buf8 = (u8 *) buf;
9270
9271 /* Separate the parity bits and the data bytes. */
9272 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9273 if ((i == 0) || (i == 8)) {
9274 int l;
9275 u8 msk;
9276
9277 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9278 parity[k++] = buf8[i] & msk;
9279 i++;
9280 }
9281 else if (i == 16) {
9282 int l;
9283 u8 msk;
9284
9285 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9286 parity[k++] = buf8[i] & msk;
9287 i++;
9288
9289 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9290 parity[k++] = buf8[i] & msk;
9291 i++;
9292 }
9293 data[j++] = buf8[i];
9294 }
9295
9296 err = -EIO;
9297 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9298 u8 hw8 = hweight8(data[i]);
9299
9300 if ((hw8 & 0x1) && parity[i])
9301 goto out;
9302 else if (!(hw8 & 0x1) && !parity[i])
9303 goto out;
9304 }
9305 err = 0;
9306 goto out;
9307 }
9308
9309 /* Bootstrap checksum at offset 0x10 */
9310 csum = calc_crc((unsigned char *) buf, 0x10);
9311 if (csum != be32_to_cpu(buf[0x10/4]))
9312 goto out;
9313
9314 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9315 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9316 if (csum != be32_to_cpu(buf[0xfc/4]))
9317 goto out;
9318
9319 err = 0;
9320
9321 out:
9322 kfree(buf);
9323 return err;
9324 }
9325
9326 #define TG3_SERDES_TIMEOUT_SEC 2
9327 #define TG3_COPPER_TIMEOUT_SEC 6
9328
9329 static int tg3_test_link(struct tg3 *tp)
9330 {
9331 int i, max;
9332
9333 if (!netif_running(tp->dev))
9334 return -ENODEV;
9335
9336 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9337 max = TG3_SERDES_TIMEOUT_SEC;
9338 else
9339 max = TG3_COPPER_TIMEOUT_SEC;
9340
9341 for (i = 0; i < max; i++) {
9342 if (netif_carrier_ok(tp->dev))
9343 return 0;
9344
9345 if (msleep_interruptible(1000))
9346 break;
9347 }
9348
9349 return -EIO;
9350 }
9351
9352 /* Only test the commonly used registers */
9353 static int tg3_test_registers(struct tg3 *tp)
9354 {
9355 int i, is_5705, is_5750;
9356 u32 offset, read_mask, write_mask, val, save_val, read_val;
9357 static struct {
9358 u16 offset;
9359 u16 flags;
9360 #define TG3_FL_5705 0x1
9361 #define TG3_FL_NOT_5705 0x2
9362 #define TG3_FL_NOT_5788 0x4
9363 #define TG3_FL_NOT_5750 0x8
9364 u32 read_mask;
9365 u32 write_mask;
9366 } reg_tbl[] = {
9367 /* MAC Control Registers */
9368 { MAC_MODE, TG3_FL_NOT_5705,
9369 0x00000000, 0x00ef6f8c },
9370 { MAC_MODE, TG3_FL_5705,
9371 0x00000000, 0x01ef6b8c },
9372 { MAC_STATUS, TG3_FL_NOT_5705,
9373 0x03800107, 0x00000000 },
9374 { MAC_STATUS, TG3_FL_5705,
9375 0x03800100, 0x00000000 },
9376 { MAC_ADDR_0_HIGH, 0x0000,
9377 0x00000000, 0x0000ffff },
9378 { MAC_ADDR_0_LOW, 0x0000,
9379 0x00000000, 0xffffffff },
9380 { MAC_RX_MTU_SIZE, 0x0000,
9381 0x00000000, 0x0000ffff },
9382 { MAC_TX_MODE, 0x0000,
9383 0x00000000, 0x00000070 },
9384 { MAC_TX_LENGTHS, 0x0000,
9385 0x00000000, 0x00003fff },
9386 { MAC_RX_MODE, TG3_FL_NOT_5705,
9387 0x00000000, 0x000007fc },
9388 { MAC_RX_MODE, TG3_FL_5705,
9389 0x00000000, 0x000007dc },
9390 { MAC_HASH_REG_0, 0x0000,
9391 0x00000000, 0xffffffff },
9392 { MAC_HASH_REG_1, 0x0000,
9393 0x00000000, 0xffffffff },
9394 { MAC_HASH_REG_2, 0x0000,
9395 0x00000000, 0xffffffff },
9396 { MAC_HASH_REG_3, 0x0000,
9397 0x00000000, 0xffffffff },
9398
9399 /* Receive Data and Receive BD Initiator Control Registers. */
9400 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9401 0x00000000, 0xffffffff },
9402 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9403 0x00000000, 0xffffffff },
9404 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9405 0x00000000, 0x00000003 },
9406 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9407 0x00000000, 0xffffffff },
9408 { RCVDBDI_STD_BD+0, 0x0000,
9409 0x00000000, 0xffffffff },
9410 { RCVDBDI_STD_BD+4, 0x0000,
9411 0x00000000, 0xffffffff },
9412 { RCVDBDI_STD_BD+8, 0x0000,
9413 0x00000000, 0xffff0002 },
9414 { RCVDBDI_STD_BD+0xc, 0x0000,
9415 0x00000000, 0xffffffff },
9416
9417 /* Receive BD Initiator Control Registers. */
9418 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9419 0x00000000, 0xffffffff },
9420 { RCVBDI_STD_THRESH, TG3_FL_5705,
9421 0x00000000, 0x000003ff },
9422 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9423 0x00000000, 0xffffffff },
9424
9425 /* Host Coalescing Control Registers. */
9426 { HOSTCC_MODE, TG3_FL_NOT_5705,
9427 0x00000000, 0x00000004 },
9428 { HOSTCC_MODE, TG3_FL_5705,
9429 0x00000000, 0x000000f6 },
9430 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9431 0x00000000, 0xffffffff },
9432 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9433 0x00000000, 0x000003ff },
9434 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9435 0x00000000, 0xffffffff },
9436 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9437 0x00000000, 0x000003ff },
9438 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9439 0x00000000, 0xffffffff },
9440 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9441 0x00000000, 0x000000ff },
9442 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9443 0x00000000, 0xffffffff },
9444 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9445 0x00000000, 0x000000ff },
9446 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9447 0x00000000, 0xffffffff },
9448 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9449 0x00000000, 0xffffffff },
9450 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9451 0x00000000, 0xffffffff },
9452 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9453 0x00000000, 0x000000ff },
9454 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9455 0x00000000, 0xffffffff },
9456 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9457 0x00000000, 0x000000ff },
9458 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9459 0x00000000, 0xffffffff },
9460 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9461 0x00000000, 0xffffffff },
9462 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9463 0x00000000, 0xffffffff },
9464 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9465 0x00000000, 0xffffffff },
9466 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9467 0x00000000, 0xffffffff },
9468 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9469 0xffffffff, 0x00000000 },
9470 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9471 0xffffffff, 0x00000000 },
9472
9473 /* Buffer Manager Control Registers. */
9474 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9475 0x00000000, 0x007fff80 },
9476 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9477 0x00000000, 0x007fffff },
9478 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9479 0x00000000, 0x0000003f },
9480 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9481 0x00000000, 0x000001ff },
9482 { BUFMGR_MB_HIGH_WATER, 0x0000,
9483 0x00000000, 0x000001ff },
9484 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9485 0xffffffff, 0x00000000 },
9486 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9487 0xffffffff, 0x00000000 },
9488
9489 /* Mailbox Registers */
9490 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9491 0x00000000, 0x000001ff },
9492 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9493 0x00000000, 0x000001ff },
9494 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9495 0x00000000, 0x000007ff },
9496 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9497 0x00000000, 0x000001ff },
9498
9499 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9500 };
9501
9502 is_5705 = is_5750 = 0;
9503 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9504 is_5705 = 1;
9505 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9506 is_5750 = 1;
9507 }
9508
9509 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9510 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9511 continue;
9512
9513 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9514 continue;
9515
9516 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9517 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9518 continue;
9519
9520 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9521 continue;
9522
9523 offset = (u32) reg_tbl[i].offset;
9524 read_mask = reg_tbl[i].read_mask;
9525 write_mask = reg_tbl[i].write_mask;
9526
9527 /* Save the original register content */
9528 save_val = tr32(offset);
9529
9530 /* Determine the read-only value. */
9531 read_val = save_val & read_mask;
9532
9533 /* Write zero to the register, then make sure the read-only bits
9534 * are not changed and the read/write bits are all zeros.
9535 */
9536 tw32(offset, 0);
9537
9538 val = tr32(offset);
9539
9540 /* Test the read-only and read/write bits. */
9541 if (((val & read_mask) != read_val) || (val & write_mask))
9542 goto out;
9543
9544 /* Write ones to all the bits defined by RdMask and WrMask, then
9545 * make sure the read-only bits are not changed and the
9546 * read/write bits are all ones.
9547 */
9548 tw32(offset, read_mask | write_mask);
9549
9550 val = tr32(offset);
9551
9552 /* Test the read-only bits. */
9553 if ((val & read_mask) != read_val)
9554 goto out;
9555
9556 /* Test the read/write bits. */
9557 if ((val & write_mask) != write_mask)
9558 goto out;
9559
9560 tw32(offset, save_val);
9561 }
9562
9563 return 0;
9564
9565 out:
9566 if (netif_msg_hw(tp))
9567 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9568 offset);
9569 tw32(offset, save_val);
9570 return -EIO;
9571 }
9572
9573 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9574 {
9575 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9576 int i;
9577 u32 j;
9578
9579 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9580 for (j = 0; j < len; j += 4) {
9581 u32 val;
9582
9583 tg3_write_mem(tp, offset + j, test_pattern[i]);
9584 tg3_read_mem(tp, offset + j, &val);
9585 if (val != test_pattern[i])
9586 return -EIO;
9587 }
9588 }
9589 return 0;
9590 }
9591
9592 static int tg3_test_memory(struct tg3 *tp)
9593 {
9594 static struct mem_entry {
9595 u32 offset;
9596 u32 len;
9597 } mem_tbl_570x[] = {
9598 { 0x00000000, 0x00b50},
9599 { 0x00002000, 0x1c000},
9600 { 0xffffffff, 0x00000}
9601 }, mem_tbl_5705[] = {
9602 { 0x00000100, 0x0000c},
9603 { 0x00000200, 0x00008},
9604 { 0x00004000, 0x00800},
9605 { 0x00006000, 0x01000},
9606 { 0x00008000, 0x02000},
9607 { 0x00010000, 0x0e000},
9608 { 0xffffffff, 0x00000}
9609 }, mem_tbl_5755[] = {
9610 { 0x00000200, 0x00008},
9611 { 0x00004000, 0x00800},
9612 { 0x00006000, 0x00800},
9613 { 0x00008000, 0x02000},
9614 { 0x00010000, 0x0c000},
9615 { 0xffffffff, 0x00000}
9616 }, mem_tbl_5906[] = {
9617 { 0x00000200, 0x00008},
9618 { 0x00004000, 0x00400},
9619 { 0x00006000, 0x00400},
9620 { 0x00008000, 0x01000},
9621 { 0x00010000, 0x01000},
9622 { 0xffffffff, 0x00000}
9623 };
9624 struct mem_entry *mem_tbl;
9625 int err = 0;
9626 int i;
9627
9628 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9629 mem_tbl = mem_tbl_5755;
9630 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9631 mem_tbl = mem_tbl_5906;
9632 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9633 mem_tbl = mem_tbl_5705;
9634 else
9635 mem_tbl = mem_tbl_570x;
9636
9637 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9638 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9639 mem_tbl[i].len)) != 0)
9640 break;
9641 }
9642
9643 return err;
9644 }
9645
9646 #define TG3_MAC_LOOPBACK 0
9647 #define TG3_PHY_LOOPBACK 1
9648
9649 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9650 {
9651 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9652 u32 desc_idx;
9653 struct sk_buff *skb, *rx_skb;
9654 u8 *tx_data;
9655 dma_addr_t map;
9656 int num_pkts, tx_len, rx_len, i, err;
9657 struct tg3_rx_buffer_desc *desc;
9658
9659 if (loopback_mode == TG3_MAC_LOOPBACK) {
9660 /* HW errata - mac loopback fails in some cases on 5780.
9661 * Normal traffic and PHY loopback are not affected by
9662 * errata.
9663 */
9664 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9665 return 0;
9666
9667 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9668 MAC_MODE_PORT_INT_LPBACK;
9669 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9670 mac_mode |= MAC_MODE_LINK_POLARITY;
9671 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9672 mac_mode |= MAC_MODE_PORT_MODE_MII;
9673 else
9674 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9675 tw32(MAC_MODE, mac_mode);
9676 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9677 u32 val;
9678
9679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9680 u32 phytest;
9681
9682 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9683 u32 phy;
9684
9685 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9686 phytest | MII_TG3_EPHY_SHADOW_EN);
9687 if (!tg3_readphy(tp, 0x1b, &phy))
9688 tg3_writephy(tp, 0x1b, phy & ~0x20);
9689 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9690 }
9691 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9692 } else
9693 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9694
9695 tg3_phy_toggle_automdix(tp, 0);
9696
9697 tg3_writephy(tp, MII_BMCR, val);
9698 udelay(40);
9699
9700 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9702 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9703 mac_mode |= MAC_MODE_PORT_MODE_MII;
9704 } else
9705 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9706
9707 /* reset to prevent losing 1st rx packet intermittently */
9708 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9709 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9710 udelay(10);
9711 tw32_f(MAC_RX_MODE, tp->rx_mode);
9712 }
9713 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9714 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9715 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9716 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9717 mac_mode |= MAC_MODE_LINK_POLARITY;
9718 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9719 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9720 }
9721 tw32(MAC_MODE, mac_mode);
9722 }
9723 else
9724 return -EINVAL;
9725
9726 err = -EIO;
9727
9728 tx_len = 1514;
9729 skb = netdev_alloc_skb(tp->dev, tx_len);
9730 if (!skb)
9731 return -ENOMEM;
9732
9733 tx_data = skb_put(skb, tx_len);
9734 memcpy(tx_data, tp->dev->dev_addr, 6);
9735 memset(tx_data + 6, 0x0, 8);
9736
9737 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9738
9739 for (i = 14; i < tx_len; i++)
9740 tx_data[i] = (u8) (i & 0xff);
9741
9742 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9743
9744 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9745 HOSTCC_MODE_NOW);
9746
9747 udelay(10);
9748
9749 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9750
9751 num_pkts = 0;
9752
9753 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9754
9755 tp->tx_prod++;
9756 num_pkts++;
9757
9758 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9759 tp->tx_prod);
9760 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9761
9762 udelay(10);
9763
9764 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9765 for (i = 0; i < 25; i++) {
9766 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9767 HOSTCC_MODE_NOW);
9768
9769 udelay(10);
9770
9771 tx_idx = tp->hw_status->idx[0].tx_consumer;
9772 rx_idx = tp->hw_status->idx[0].rx_producer;
9773 if ((tx_idx == tp->tx_prod) &&
9774 (rx_idx == (rx_start_idx + num_pkts)))
9775 break;
9776 }
9777
9778 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9779 dev_kfree_skb(skb);
9780
9781 if (tx_idx != tp->tx_prod)
9782 goto out;
9783
9784 if (rx_idx != rx_start_idx + num_pkts)
9785 goto out;
9786
9787 desc = &tp->rx_rcb[rx_start_idx];
9788 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9789 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9790 if (opaque_key != RXD_OPAQUE_RING_STD)
9791 goto out;
9792
9793 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9794 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9795 goto out;
9796
9797 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9798 if (rx_len != tx_len)
9799 goto out;
9800
9801 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9802
9803 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9804 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9805
9806 for (i = 14; i < tx_len; i++) {
9807 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9808 goto out;
9809 }
9810 err = 0;
9811
9812 /* tg3_free_rings will unmap and free the rx_skb */
9813 out:
9814 return err;
9815 }
9816
9817 #define TG3_MAC_LOOPBACK_FAILED 1
9818 #define TG3_PHY_LOOPBACK_FAILED 2
9819 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9820 TG3_PHY_LOOPBACK_FAILED)
9821
9822 static int tg3_test_loopback(struct tg3 *tp)
9823 {
9824 int err = 0;
9825 u32 cpmuctrl = 0;
9826
9827 if (!netif_running(tp->dev))
9828 return TG3_LOOPBACK_FAILED;
9829
9830 err = tg3_reset_hw(tp, 1);
9831 if (err)
9832 return TG3_LOOPBACK_FAILED;
9833
9834 /* Turn off gphy autopowerdown. */
9835 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9836 tg3_phy_toggle_apd(tp, false);
9837
9838 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9839 int i;
9840 u32 status;
9841
9842 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9843
9844 /* Wait for up to 40 microseconds to acquire lock. */
9845 for (i = 0; i < 4; i++) {
9846 status = tr32(TG3_CPMU_MUTEX_GNT);
9847 if (status == CPMU_MUTEX_GNT_DRIVER)
9848 break;
9849 udelay(10);
9850 }
9851
9852 if (status != CPMU_MUTEX_GNT_DRIVER)
9853 return TG3_LOOPBACK_FAILED;
9854
9855 /* Turn off link-based power management. */
9856 cpmuctrl = tr32(TG3_CPMU_CTRL);
9857 tw32(TG3_CPMU_CTRL,
9858 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9859 CPMU_CTRL_LINK_AWARE_MODE));
9860 }
9861
9862 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9863 err |= TG3_MAC_LOOPBACK_FAILED;
9864
9865 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9866 tw32(TG3_CPMU_CTRL, cpmuctrl);
9867
9868 /* Release the mutex */
9869 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9870 }
9871
9872 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9873 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9874 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9875 err |= TG3_PHY_LOOPBACK_FAILED;
9876 }
9877
9878 /* Re-enable gphy autopowerdown. */
9879 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9880 tg3_phy_toggle_apd(tp, true);
9881
9882 return err;
9883 }
9884
9885 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9886 u64 *data)
9887 {
9888 struct tg3 *tp = netdev_priv(dev);
9889
9890 if (tp->link_config.phy_is_low_power)
9891 tg3_set_power_state(tp, PCI_D0);
9892
9893 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9894
9895 if (tg3_test_nvram(tp) != 0) {
9896 etest->flags |= ETH_TEST_FL_FAILED;
9897 data[0] = 1;
9898 }
9899 if (tg3_test_link(tp) != 0) {
9900 etest->flags |= ETH_TEST_FL_FAILED;
9901 data[1] = 1;
9902 }
9903 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9904 int err, err2 = 0, irq_sync = 0;
9905
9906 if (netif_running(dev)) {
9907 tg3_phy_stop(tp);
9908 tg3_netif_stop(tp);
9909 irq_sync = 1;
9910 }
9911
9912 tg3_full_lock(tp, irq_sync);
9913
9914 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9915 err = tg3_nvram_lock(tp);
9916 tg3_halt_cpu(tp, RX_CPU_BASE);
9917 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9918 tg3_halt_cpu(tp, TX_CPU_BASE);
9919 if (!err)
9920 tg3_nvram_unlock(tp);
9921
9922 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9923 tg3_phy_reset(tp);
9924
9925 if (tg3_test_registers(tp) != 0) {
9926 etest->flags |= ETH_TEST_FL_FAILED;
9927 data[2] = 1;
9928 }
9929 if (tg3_test_memory(tp) != 0) {
9930 etest->flags |= ETH_TEST_FL_FAILED;
9931 data[3] = 1;
9932 }
9933 if ((data[4] = tg3_test_loopback(tp)) != 0)
9934 etest->flags |= ETH_TEST_FL_FAILED;
9935
9936 tg3_full_unlock(tp);
9937
9938 if (tg3_test_interrupt(tp) != 0) {
9939 etest->flags |= ETH_TEST_FL_FAILED;
9940 data[5] = 1;
9941 }
9942
9943 tg3_full_lock(tp, 0);
9944
9945 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9946 if (netif_running(dev)) {
9947 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9948 err2 = tg3_restart_hw(tp, 1);
9949 if (!err2)
9950 tg3_netif_start(tp);
9951 }
9952
9953 tg3_full_unlock(tp);
9954
9955 if (irq_sync && !err2)
9956 tg3_phy_start(tp);
9957 }
9958 if (tp->link_config.phy_is_low_power)
9959 tg3_set_power_state(tp, PCI_D3hot);
9960
9961 }
9962
9963 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9964 {
9965 struct mii_ioctl_data *data = if_mii(ifr);
9966 struct tg3 *tp = netdev_priv(dev);
9967 int err;
9968
9969 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9970 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9971 return -EAGAIN;
9972 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
9973 }
9974
9975 switch(cmd) {
9976 case SIOCGMIIPHY:
9977 data->phy_id = PHY_ADDR;
9978
9979 /* fallthru */
9980 case SIOCGMIIREG: {
9981 u32 mii_regval;
9982
9983 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9984 break; /* We have no PHY */
9985
9986 if (tp->link_config.phy_is_low_power)
9987 return -EAGAIN;
9988
9989 spin_lock_bh(&tp->lock);
9990 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9991 spin_unlock_bh(&tp->lock);
9992
9993 data->val_out = mii_regval;
9994
9995 return err;
9996 }
9997
9998 case SIOCSMIIREG:
9999 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10000 break; /* We have no PHY */
10001
10002 if (!capable(CAP_NET_ADMIN))
10003 return -EPERM;
10004
10005 if (tp->link_config.phy_is_low_power)
10006 return -EAGAIN;
10007
10008 spin_lock_bh(&tp->lock);
10009 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10010 spin_unlock_bh(&tp->lock);
10011
10012 return err;
10013
10014 default:
10015 /* do nothing */
10016 break;
10017 }
10018 return -EOPNOTSUPP;
10019 }
10020
10021 #if TG3_VLAN_TAG_USED
10022 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10023 {
10024 struct tg3 *tp = netdev_priv(dev);
10025
10026 if (!netif_running(dev)) {
10027 tp->vlgrp = grp;
10028 return;
10029 }
10030
10031 tg3_netif_stop(tp);
10032
10033 tg3_full_lock(tp, 0);
10034
10035 tp->vlgrp = grp;
10036
10037 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10038 __tg3_set_rx_mode(dev);
10039
10040 tg3_netif_start(tp);
10041
10042 tg3_full_unlock(tp);
10043 }
10044 #endif
10045
10046 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10047 {
10048 struct tg3 *tp = netdev_priv(dev);
10049
10050 memcpy(ec, &tp->coal, sizeof(*ec));
10051 return 0;
10052 }
10053
10054 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10055 {
10056 struct tg3 *tp = netdev_priv(dev);
10057 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10058 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10059
10060 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10061 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10062 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10063 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10064 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10065 }
10066
10067 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10068 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10069 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10070 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10071 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10072 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10073 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10074 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10075 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10076 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10077 return -EINVAL;
10078
10079 /* No rx interrupts will be generated if both are zero */
10080 if ((ec->rx_coalesce_usecs == 0) &&
10081 (ec->rx_max_coalesced_frames == 0))
10082 return -EINVAL;
10083
10084 /* No tx interrupts will be generated if both are zero */
10085 if ((ec->tx_coalesce_usecs == 0) &&
10086 (ec->tx_max_coalesced_frames == 0))
10087 return -EINVAL;
10088
10089 /* Only copy relevant parameters, ignore all others. */
10090 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10091 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10092 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10093 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10094 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10095 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10096 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10097 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10098 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10099
10100 if (netif_running(dev)) {
10101 tg3_full_lock(tp, 0);
10102 __tg3_set_coalesce(tp, &tp->coal);
10103 tg3_full_unlock(tp);
10104 }
10105 return 0;
10106 }
10107
10108 static const struct ethtool_ops tg3_ethtool_ops = {
10109 .get_settings = tg3_get_settings,
10110 .set_settings = tg3_set_settings,
10111 .get_drvinfo = tg3_get_drvinfo,
10112 .get_regs_len = tg3_get_regs_len,
10113 .get_regs = tg3_get_regs,
10114 .get_wol = tg3_get_wol,
10115 .set_wol = tg3_set_wol,
10116 .get_msglevel = tg3_get_msglevel,
10117 .set_msglevel = tg3_set_msglevel,
10118 .nway_reset = tg3_nway_reset,
10119 .get_link = ethtool_op_get_link,
10120 .get_eeprom_len = tg3_get_eeprom_len,
10121 .get_eeprom = tg3_get_eeprom,
10122 .set_eeprom = tg3_set_eeprom,
10123 .get_ringparam = tg3_get_ringparam,
10124 .set_ringparam = tg3_set_ringparam,
10125 .get_pauseparam = tg3_get_pauseparam,
10126 .set_pauseparam = tg3_set_pauseparam,
10127 .get_rx_csum = tg3_get_rx_csum,
10128 .set_rx_csum = tg3_set_rx_csum,
10129 .set_tx_csum = tg3_set_tx_csum,
10130 .set_sg = ethtool_op_set_sg,
10131 .set_tso = tg3_set_tso,
10132 .self_test = tg3_self_test,
10133 .get_strings = tg3_get_strings,
10134 .phys_id = tg3_phys_id,
10135 .get_ethtool_stats = tg3_get_ethtool_stats,
10136 .get_coalesce = tg3_get_coalesce,
10137 .set_coalesce = tg3_set_coalesce,
10138 .get_sset_count = tg3_get_sset_count,
10139 };
10140
10141 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10142 {
10143 u32 cursize, val, magic;
10144
10145 tp->nvram_size = EEPROM_CHIP_SIZE;
10146
10147 if (tg3_nvram_read(tp, 0, &magic) != 0)
10148 return;
10149
10150 if ((magic != TG3_EEPROM_MAGIC) &&
10151 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10152 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10153 return;
10154
10155 /*
10156 * Size the chip by reading offsets at increasing powers of two.
10157 * When we encounter our validation signature, we know the addressing
10158 * has wrapped around, and thus have our chip size.
10159 */
10160 cursize = 0x10;
10161
10162 while (cursize < tp->nvram_size) {
10163 if (tg3_nvram_read(tp, cursize, &val) != 0)
10164 return;
10165
10166 if (val == magic)
10167 break;
10168
10169 cursize <<= 1;
10170 }
10171
10172 tp->nvram_size = cursize;
10173 }
10174
10175 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10176 {
10177 u32 val;
10178
10179 if (tg3_nvram_read(tp, 0, &val) != 0)
10180 return;
10181
10182 /* Selfboot format */
10183 if (val != TG3_EEPROM_MAGIC) {
10184 tg3_get_eeprom_size(tp);
10185 return;
10186 }
10187
10188 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10189 if (val != 0) {
10190 /* This is confusing. We want to operate on the
10191 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10192 * call will read from NVRAM and byteswap the data
10193 * according to the byteswapping settings for all
10194 * other register accesses. This ensures the data we
10195 * want will always reside in the lower 16-bits.
10196 * However, the data in NVRAM is in LE format, which
10197 * means the data from the NVRAM read will always be
10198 * opposite the endianness of the CPU. The 16-bit
10199 * byteswap then brings the data to CPU endianness.
10200 */
10201 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10202 return;
10203 }
10204 }
10205 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10206 }
10207
10208 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10209 {
10210 u32 nvcfg1;
10211
10212 nvcfg1 = tr32(NVRAM_CFG1);
10213 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10214 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10215 }
10216 else {
10217 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10218 tw32(NVRAM_CFG1, nvcfg1);
10219 }
10220
10221 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10222 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10223 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10224 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10225 tp->nvram_jedecnum = JEDEC_ATMEL;
10226 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10227 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10228 break;
10229 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10230 tp->nvram_jedecnum = JEDEC_ATMEL;
10231 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10232 break;
10233 case FLASH_VENDOR_ATMEL_EEPROM:
10234 tp->nvram_jedecnum = JEDEC_ATMEL;
10235 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10236 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10237 break;
10238 case FLASH_VENDOR_ST:
10239 tp->nvram_jedecnum = JEDEC_ST;
10240 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10241 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10242 break;
10243 case FLASH_VENDOR_SAIFUN:
10244 tp->nvram_jedecnum = JEDEC_SAIFUN;
10245 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10246 break;
10247 case FLASH_VENDOR_SST_SMALL:
10248 case FLASH_VENDOR_SST_LARGE:
10249 tp->nvram_jedecnum = JEDEC_SST;
10250 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10251 break;
10252 }
10253 }
10254 else {
10255 tp->nvram_jedecnum = JEDEC_ATMEL;
10256 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10257 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10258 }
10259 }
10260
10261 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10262 {
10263 u32 nvcfg1;
10264
10265 nvcfg1 = tr32(NVRAM_CFG1);
10266
10267 /* NVRAM protection for TPM */
10268 if (nvcfg1 & (1 << 27))
10269 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10270
10271 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10272 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10273 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10274 tp->nvram_jedecnum = JEDEC_ATMEL;
10275 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10276 break;
10277 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10278 tp->nvram_jedecnum = JEDEC_ATMEL;
10279 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10280 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10281 break;
10282 case FLASH_5752VENDOR_ST_M45PE10:
10283 case FLASH_5752VENDOR_ST_M45PE20:
10284 case FLASH_5752VENDOR_ST_M45PE40:
10285 tp->nvram_jedecnum = JEDEC_ST;
10286 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10287 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10288 break;
10289 }
10290
10291 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10292 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10293 case FLASH_5752PAGE_SIZE_256:
10294 tp->nvram_pagesize = 256;
10295 break;
10296 case FLASH_5752PAGE_SIZE_512:
10297 tp->nvram_pagesize = 512;
10298 break;
10299 case FLASH_5752PAGE_SIZE_1K:
10300 tp->nvram_pagesize = 1024;
10301 break;
10302 case FLASH_5752PAGE_SIZE_2K:
10303 tp->nvram_pagesize = 2048;
10304 break;
10305 case FLASH_5752PAGE_SIZE_4K:
10306 tp->nvram_pagesize = 4096;
10307 break;
10308 case FLASH_5752PAGE_SIZE_264:
10309 tp->nvram_pagesize = 264;
10310 break;
10311 }
10312 }
10313 else {
10314 /* For eeprom, set pagesize to maximum eeprom size */
10315 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10316
10317 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10318 tw32(NVRAM_CFG1, nvcfg1);
10319 }
10320 }
10321
10322 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10323 {
10324 u32 nvcfg1, protect = 0;
10325
10326 nvcfg1 = tr32(NVRAM_CFG1);
10327
10328 /* NVRAM protection for TPM */
10329 if (nvcfg1 & (1 << 27)) {
10330 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10331 protect = 1;
10332 }
10333
10334 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10335 switch (nvcfg1) {
10336 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10337 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10338 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10339 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10340 tp->nvram_jedecnum = JEDEC_ATMEL;
10341 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10342 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10343 tp->nvram_pagesize = 264;
10344 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10345 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10346 tp->nvram_size = (protect ? 0x3e200 :
10347 TG3_NVRAM_SIZE_512KB);
10348 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10349 tp->nvram_size = (protect ? 0x1f200 :
10350 TG3_NVRAM_SIZE_256KB);
10351 else
10352 tp->nvram_size = (protect ? 0x1f200 :
10353 TG3_NVRAM_SIZE_128KB);
10354 break;
10355 case FLASH_5752VENDOR_ST_M45PE10:
10356 case FLASH_5752VENDOR_ST_M45PE20:
10357 case FLASH_5752VENDOR_ST_M45PE40:
10358 tp->nvram_jedecnum = JEDEC_ST;
10359 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10360 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10361 tp->nvram_pagesize = 256;
10362 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10363 tp->nvram_size = (protect ?
10364 TG3_NVRAM_SIZE_64KB :
10365 TG3_NVRAM_SIZE_128KB);
10366 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10367 tp->nvram_size = (protect ?
10368 TG3_NVRAM_SIZE_64KB :
10369 TG3_NVRAM_SIZE_256KB);
10370 else
10371 tp->nvram_size = (protect ?
10372 TG3_NVRAM_SIZE_128KB :
10373 TG3_NVRAM_SIZE_512KB);
10374 break;
10375 }
10376 }
10377
10378 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10379 {
10380 u32 nvcfg1;
10381
10382 nvcfg1 = tr32(NVRAM_CFG1);
10383
10384 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10385 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10386 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10387 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10388 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10389 tp->nvram_jedecnum = JEDEC_ATMEL;
10390 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10391 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10392
10393 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10394 tw32(NVRAM_CFG1, nvcfg1);
10395 break;
10396 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10397 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10398 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10399 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10400 tp->nvram_jedecnum = JEDEC_ATMEL;
10401 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10402 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10403 tp->nvram_pagesize = 264;
10404 break;
10405 case FLASH_5752VENDOR_ST_M45PE10:
10406 case FLASH_5752VENDOR_ST_M45PE20:
10407 case FLASH_5752VENDOR_ST_M45PE40:
10408 tp->nvram_jedecnum = JEDEC_ST;
10409 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10410 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10411 tp->nvram_pagesize = 256;
10412 break;
10413 }
10414 }
10415
10416 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10417 {
10418 u32 nvcfg1, protect = 0;
10419
10420 nvcfg1 = tr32(NVRAM_CFG1);
10421
10422 /* NVRAM protection for TPM */
10423 if (nvcfg1 & (1 << 27)) {
10424 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10425 protect = 1;
10426 }
10427
10428 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10429 switch (nvcfg1) {
10430 case FLASH_5761VENDOR_ATMEL_ADB021D:
10431 case FLASH_5761VENDOR_ATMEL_ADB041D:
10432 case FLASH_5761VENDOR_ATMEL_ADB081D:
10433 case FLASH_5761VENDOR_ATMEL_ADB161D:
10434 case FLASH_5761VENDOR_ATMEL_MDB021D:
10435 case FLASH_5761VENDOR_ATMEL_MDB041D:
10436 case FLASH_5761VENDOR_ATMEL_MDB081D:
10437 case FLASH_5761VENDOR_ATMEL_MDB161D:
10438 tp->nvram_jedecnum = JEDEC_ATMEL;
10439 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10440 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10441 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10442 tp->nvram_pagesize = 256;
10443 break;
10444 case FLASH_5761VENDOR_ST_A_M45PE20:
10445 case FLASH_5761VENDOR_ST_A_M45PE40:
10446 case FLASH_5761VENDOR_ST_A_M45PE80:
10447 case FLASH_5761VENDOR_ST_A_M45PE16:
10448 case FLASH_5761VENDOR_ST_M_M45PE20:
10449 case FLASH_5761VENDOR_ST_M_M45PE40:
10450 case FLASH_5761VENDOR_ST_M_M45PE80:
10451 case FLASH_5761VENDOR_ST_M_M45PE16:
10452 tp->nvram_jedecnum = JEDEC_ST;
10453 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10454 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10455 tp->nvram_pagesize = 256;
10456 break;
10457 }
10458
10459 if (protect) {
10460 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10461 } else {
10462 switch (nvcfg1) {
10463 case FLASH_5761VENDOR_ATMEL_ADB161D:
10464 case FLASH_5761VENDOR_ATMEL_MDB161D:
10465 case FLASH_5761VENDOR_ST_A_M45PE16:
10466 case FLASH_5761VENDOR_ST_M_M45PE16:
10467 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10468 break;
10469 case FLASH_5761VENDOR_ATMEL_ADB081D:
10470 case FLASH_5761VENDOR_ATMEL_MDB081D:
10471 case FLASH_5761VENDOR_ST_A_M45PE80:
10472 case FLASH_5761VENDOR_ST_M_M45PE80:
10473 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10474 break;
10475 case FLASH_5761VENDOR_ATMEL_ADB041D:
10476 case FLASH_5761VENDOR_ATMEL_MDB041D:
10477 case FLASH_5761VENDOR_ST_A_M45PE40:
10478 case FLASH_5761VENDOR_ST_M_M45PE40:
10479 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10480 break;
10481 case FLASH_5761VENDOR_ATMEL_ADB021D:
10482 case FLASH_5761VENDOR_ATMEL_MDB021D:
10483 case FLASH_5761VENDOR_ST_A_M45PE20:
10484 case FLASH_5761VENDOR_ST_M_M45PE20:
10485 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10486 break;
10487 }
10488 }
10489 }
10490
10491 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10492 {
10493 tp->nvram_jedecnum = JEDEC_ATMEL;
10494 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10495 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10496 }
10497
10498 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10499 {
10500 u32 nvcfg1;
10501
10502 nvcfg1 = tr32(NVRAM_CFG1);
10503
10504 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10505 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10506 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10507 tp->nvram_jedecnum = JEDEC_ATMEL;
10508 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10509 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10510
10511 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10512 tw32(NVRAM_CFG1, nvcfg1);
10513 return;
10514 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10515 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10516 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10517 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10518 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10519 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10520 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10521 tp->nvram_jedecnum = JEDEC_ATMEL;
10522 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10523 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10524
10525 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10526 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10527 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10528 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10529 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10530 break;
10531 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10532 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10533 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10534 break;
10535 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10536 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10537 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10538 break;
10539 }
10540 break;
10541 case FLASH_5752VENDOR_ST_M45PE10:
10542 case FLASH_5752VENDOR_ST_M45PE20:
10543 case FLASH_5752VENDOR_ST_M45PE40:
10544 tp->nvram_jedecnum = JEDEC_ST;
10545 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10546 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10547
10548 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10549 case FLASH_5752VENDOR_ST_M45PE10:
10550 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10551 break;
10552 case FLASH_5752VENDOR_ST_M45PE20:
10553 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10554 break;
10555 case FLASH_5752VENDOR_ST_M45PE40:
10556 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10557 break;
10558 }
10559 break;
10560 default:
10561 return;
10562 }
10563
10564 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10565 case FLASH_5752PAGE_SIZE_256:
10566 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10567 tp->nvram_pagesize = 256;
10568 break;
10569 case FLASH_5752PAGE_SIZE_512:
10570 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10571 tp->nvram_pagesize = 512;
10572 break;
10573 case FLASH_5752PAGE_SIZE_1K:
10574 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10575 tp->nvram_pagesize = 1024;
10576 break;
10577 case FLASH_5752PAGE_SIZE_2K:
10578 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10579 tp->nvram_pagesize = 2048;
10580 break;
10581 case FLASH_5752PAGE_SIZE_4K:
10582 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10583 tp->nvram_pagesize = 4096;
10584 break;
10585 case FLASH_5752PAGE_SIZE_264:
10586 tp->nvram_pagesize = 264;
10587 break;
10588 case FLASH_5752PAGE_SIZE_528:
10589 tp->nvram_pagesize = 528;
10590 break;
10591 }
10592 }
10593
10594 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10595 static void __devinit tg3_nvram_init(struct tg3 *tp)
10596 {
10597 tw32_f(GRC_EEPROM_ADDR,
10598 (EEPROM_ADDR_FSM_RESET |
10599 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10600 EEPROM_ADDR_CLKPERD_SHIFT)));
10601
10602 msleep(1);
10603
10604 /* Enable seeprom accesses. */
10605 tw32_f(GRC_LOCAL_CTRL,
10606 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10607 udelay(100);
10608
10609 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10610 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10611 tp->tg3_flags |= TG3_FLAG_NVRAM;
10612
10613 if (tg3_nvram_lock(tp)) {
10614 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10615 "tg3_nvram_init failed.\n", tp->dev->name);
10616 return;
10617 }
10618 tg3_enable_nvram_access(tp);
10619
10620 tp->nvram_size = 0;
10621
10622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10623 tg3_get_5752_nvram_info(tp);
10624 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10625 tg3_get_5755_nvram_info(tp);
10626 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10627 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10628 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10629 tg3_get_5787_nvram_info(tp);
10630 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10631 tg3_get_5761_nvram_info(tp);
10632 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10633 tg3_get_5906_nvram_info(tp);
10634 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10635 tg3_get_57780_nvram_info(tp);
10636 else
10637 tg3_get_nvram_info(tp);
10638
10639 if (tp->nvram_size == 0)
10640 tg3_get_nvram_size(tp);
10641
10642 tg3_disable_nvram_access(tp);
10643 tg3_nvram_unlock(tp);
10644
10645 } else {
10646 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10647
10648 tg3_get_eeprom_size(tp);
10649 }
10650 }
10651
10652 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10653 u32 offset, u32 len, u8 *buf)
10654 {
10655 int i, j, rc = 0;
10656 u32 val;
10657
10658 for (i = 0; i < len; i += 4) {
10659 u32 addr;
10660 __be32 data;
10661
10662 addr = offset + i;
10663
10664 memcpy(&data, buf + i, 4);
10665
10666 tw32(GRC_EEPROM_DATA, be32_to_cpu(data));
10667
10668 val = tr32(GRC_EEPROM_ADDR);
10669 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10670
10671 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10672 EEPROM_ADDR_READ);
10673 tw32(GRC_EEPROM_ADDR, val |
10674 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10675 (addr & EEPROM_ADDR_ADDR_MASK) |
10676 EEPROM_ADDR_START |
10677 EEPROM_ADDR_WRITE);
10678
10679 for (j = 0; j < 1000; j++) {
10680 val = tr32(GRC_EEPROM_ADDR);
10681
10682 if (val & EEPROM_ADDR_COMPLETE)
10683 break;
10684 msleep(1);
10685 }
10686 if (!(val & EEPROM_ADDR_COMPLETE)) {
10687 rc = -EBUSY;
10688 break;
10689 }
10690 }
10691
10692 return rc;
10693 }
10694
10695 /* offset and length are dword aligned */
10696 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10697 u8 *buf)
10698 {
10699 int ret = 0;
10700 u32 pagesize = tp->nvram_pagesize;
10701 u32 pagemask = pagesize - 1;
10702 u32 nvram_cmd;
10703 u8 *tmp;
10704
10705 tmp = kmalloc(pagesize, GFP_KERNEL);
10706 if (tmp == NULL)
10707 return -ENOMEM;
10708
10709 while (len) {
10710 int j;
10711 u32 phy_addr, page_off, size;
10712
10713 phy_addr = offset & ~pagemask;
10714
10715 for (j = 0; j < pagesize; j += 4) {
10716 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10717 (__be32 *) (tmp + j));
10718 if (ret)
10719 break;
10720 }
10721 if (ret)
10722 break;
10723
10724 page_off = offset & pagemask;
10725 size = pagesize;
10726 if (len < size)
10727 size = len;
10728
10729 len -= size;
10730
10731 memcpy(tmp + page_off, buf, size);
10732
10733 offset = offset + (pagesize - page_off);
10734
10735 tg3_enable_nvram_access(tp);
10736
10737 /*
10738 * Before we can erase the flash page, we need
10739 * to issue a special "write enable" command.
10740 */
10741 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10742
10743 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10744 break;
10745
10746 /* Erase the target page */
10747 tw32(NVRAM_ADDR, phy_addr);
10748
10749 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10750 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10751
10752 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10753 break;
10754
10755 /* Issue another write enable to start the write. */
10756 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10757
10758 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10759 break;
10760
10761 for (j = 0; j < pagesize; j += 4) {
10762 __be32 data;
10763
10764 data = *((__be32 *) (tmp + j));
10765
10766 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10767
10768 tw32(NVRAM_ADDR, phy_addr + j);
10769
10770 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10771 NVRAM_CMD_WR;
10772
10773 if (j == 0)
10774 nvram_cmd |= NVRAM_CMD_FIRST;
10775 else if (j == (pagesize - 4))
10776 nvram_cmd |= NVRAM_CMD_LAST;
10777
10778 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10779 break;
10780 }
10781 if (ret)
10782 break;
10783 }
10784
10785 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10786 tg3_nvram_exec_cmd(tp, nvram_cmd);
10787
10788 kfree(tmp);
10789
10790 return ret;
10791 }
10792
10793 /* offset and length are dword aligned */
10794 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10795 u8 *buf)
10796 {
10797 int i, ret = 0;
10798
10799 for (i = 0; i < len; i += 4, offset += 4) {
10800 u32 page_off, phy_addr, nvram_cmd;
10801 __be32 data;
10802
10803 memcpy(&data, buf + i, 4);
10804 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10805
10806 page_off = offset % tp->nvram_pagesize;
10807
10808 phy_addr = tg3_nvram_phys_addr(tp, offset);
10809
10810 tw32(NVRAM_ADDR, phy_addr);
10811
10812 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10813
10814 if ((page_off == 0) || (i == 0))
10815 nvram_cmd |= NVRAM_CMD_FIRST;
10816 if (page_off == (tp->nvram_pagesize - 4))
10817 nvram_cmd |= NVRAM_CMD_LAST;
10818
10819 if (i == (len - 4))
10820 nvram_cmd |= NVRAM_CMD_LAST;
10821
10822 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10823 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10824 (tp->nvram_jedecnum == JEDEC_ST) &&
10825 (nvram_cmd & NVRAM_CMD_FIRST)) {
10826
10827 if ((ret = tg3_nvram_exec_cmd(tp,
10828 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10829 NVRAM_CMD_DONE)))
10830
10831 break;
10832 }
10833 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10834 /* We always do complete word writes to eeprom. */
10835 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10836 }
10837
10838 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10839 break;
10840 }
10841 return ret;
10842 }
10843
10844 /* offset and length are dword aligned */
10845 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10846 {
10847 int ret;
10848
10849 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10850 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10851 ~GRC_LCLCTRL_GPIO_OUTPUT1);
10852 udelay(40);
10853 }
10854
10855 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10856 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10857 }
10858 else {
10859 u32 grc_mode;
10860
10861 ret = tg3_nvram_lock(tp);
10862 if (ret)
10863 return ret;
10864
10865 tg3_enable_nvram_access(tp);
10866 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10867 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10868 tw32(NVRAM_WRITE1, 0x406);
10869
10870 grc_mode = tr32(GRC_MODE);
10871 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10872
10873 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10874 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10875
10876 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10877 buf);
10878 }
10879 else {
10880 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10881 buf);
10882 }
10883
10884 grc_mode = tr32(GRC_MODE);
10885 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10886
10887 tg3_disable_nvram_access(tp);
10888 tg3_nvram_unlock(tp);
10889 }
10890
10891 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10892 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10893 udelay(40);
10894 }
10895
10896 return ret;
10897 }
10898
10899 struct subsys_tbl_ent {
10900 u16 subsys_vendor, subsys_devid;
10901 u32 phy_id;
10902 };
10903
10904 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10905 /* Broadcom boards. */
10906 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10907 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10908 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10909 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10910 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10911 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10912 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10913 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10914 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10915 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10916 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10917
10918 /* 3com boards. */
10919 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10920 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10921 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10922 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10923 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10924
10925 /* DELL boards. */
10926 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10927 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10928 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10929 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10930
10931 /* Compaq boards. */
10932 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10933 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10934 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10935 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10936 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10937
10938 /* IBM boards. */
10939 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10940 };
10941
10942 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10943 {
10944 int i;
10945
10946 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10947 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10948 tp->pdev->subsystem_vendor) &&
10949 (subsys_id_to_phy_id[i].subsys_devid ==
10950 tp->pdev->subsystem_device))
10951 return &subsys_id_to_phy_id[i];
10952 }
10953 return NULL;
10954 }
10955
10956 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10957 {
10958 u32 val;
10959 u16 pmcsr;
10960
10961 /* On some early chips the SRAM cannot be accessed in D3hot state,
10962 * so need make sure we're in D0.
10963 */
10964 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10965 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10966 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10967 msleep(1);
10968
10969 /* Make sure register accesses (indirect or otherwise)
10970 * will function correctly.
10971 */
10972 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10973 tp->misc_host_ctrl);
10974
10975 /* The memory arbiter has to be enabled in order for SRAM accesses
10976 * to succeed. Normally on powerup the tg3 chip firmware will make
10977 * sure it is enabled, but other entities such as system netboot
10978 * code might disable it.
10979 */
10980 val = tr32(MEMARB_MODE);
10981 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10982
10983 tp->phy_id = PHY_ID_INVALID;
10984 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10985
10986 /* Assume an onboard device and WOL capable by default. */
10987 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10988
10989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10990 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10991 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10992 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10993 }
10994 val = tr32(VCPU_CFGSHDW);
10995 if (val & VCPU_CFGSHDW_ASPM_DBNC)
10996 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10997 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
10998 (val & VCPU_CFGSHDW_WOL_MAGPKT))
10999 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11000 goto done;
11001 }
11002
11003 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11004 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11005 u32 nic_cfg, led_cfg;
11006 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11007 int eeprom_phy_serdes = 0;
11008
11009 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11010 tp->nic_sram_data_cfg = nic_cfg;
11011
11012 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11013 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11014 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11015 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11016 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11017 (ver > 0) && (ver < 0x100))
11018 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11019
11020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11021 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11022
11023 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11024 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11025 eeprom_phy_serdes = 1;
11026
11027 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11028 if (nic_phy_id != 0) {
11029 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11030 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11031
11032 eeprom_phy_id = (id1 >> 16) << 10;
11033 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11034 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11035 } else
11036 eeprom_phy_id = 0;
11037
11038 tp->phy_id = eeprom_phy_id;
11039 if (eeprom_phy_serdes) {
11040 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11041 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11042 else
11043 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11044 }
11045
11046 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11047 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11048 SHASTA_EXT_LED_MODE_MASK);
11049 else
11050 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11051
11052 switch (led_cfg) {
11053 default:
11054 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11055 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11056 break;
11057
11058 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11059 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11060 break;
11061
11062 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11063 tp->led_ctrl = LED_CTRL_MODE_MAC;
11064
11065 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11066 * read on some older 5700/5701 bootcode.
11067 */
11068 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11069 ASIC_REV_5700 ||
11070 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11071 ASIC_REV_5701)
11072 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11073
11074 break;
11075
11076 case SHASTA_EXT_LED_SHARED:
11077 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11078 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11079 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11080 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11081 LED_CTRL_MODE_PHY_2);
11082 break;
11083
11084 case SHASTA_EXT_LED_MAC:
11085 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11086 break;
11087
11088 case SHASTA_EXT_LED_COMBO:
11089 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11090 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11091 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11092 LED_CTRL_MODE_PHY_2);
11093 break;
11094
11095 }
11096
11097 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11099 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11100 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11101
11102 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11103 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11104
11105 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11106 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11107 if ((tp->pdev->subsystem_vendor ==
11108 PCI_VENDOR_ID_ARIMA) &&
11109 (tp->pdev->subsystem_device == 0x205a ||
11110 tp->pdev->subsystem_device == 0x2063))
11111 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11112 } else {
11113 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11114 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11115 }
11116
11117 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11118 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11119 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11120 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11121 }
11122
11123 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11124 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11125 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11126
11127 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11128 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11129 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11130
11131 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11132 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11133 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11134
11135 if (cfg2 & (1 << 17))
11136 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11137
11138 /* serdes signal pre-emphasis in register 0x590 set by */
11139 /* bootcode if bit 18 is set */
11140 if (cfg2 & (1 << 18))
11141 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11142
11143 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11144 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11145 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11146 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11147
11148 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11149 u32 cfg3;
11150
11151 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11152 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11153 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11154 }
11155
11156 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11157 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11158 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11159 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11160 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11161 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11162 }
11163 done:
11164 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11165 device_set_wakeup_enable(&tp->pdev->dev,
11166 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11167 }
11168
11169 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11170 {
11171 int i;
11172 u32 val;
11173
11174 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11175 tw32(OTP_CTRL, cmd);
11176
11177 /* Wait for up to 1 ms for command to execute. */
11178 for (i = 0; i < 100; i++) {
11179 val = tr32(OTP_STATUS);
11180 if (val & OTP_STATUS_CMD_DONE)
11181 break;
11182 udelay(10);
11183 }
11184
11185 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11186 }
11187
11188 /* Read the gphy configuration from the OTP region of the chip. The gphy
11189 * configuration is a 32-bit value that straddles the alignment boundary.
11190 * We do two 32-bit reads and then shift and merge the results.
11191 */
11192 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11193 {
11194 u32 bhalf_otp, thalf_otp;
11195
11196 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11197
11198 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11199 return 0;
11200
11201 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11202
11203 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11204 return 0;
11205
11206 thalf_otp = tr32(OTP_READ_DATA);
11207
11208 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11209
11210 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11211 return 0;
11212
11213 bhalf_otp = tr32(OTP_READ_DATA);
11214
11215 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11216 }
11217
11218 static int __devinit tg3_phy_probe(struct tg3 *tp)
11219 {
11220 u32 hw_phy_id_1, hw_phy_id_2;
11221 u32 hw_phy_id, hw_phy_id_masked;
11222 int err;
11223
11224 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11225 return tg3_phy_init(tp);
11226
11227 /* Reading the PHY ID register can conflict with ASF
11228 * firwmare access to the PHY hardware.
11229 */
11230 err = 0;
11231 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11232 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11233 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11234 } else {
11235 /* Now read the physical PHY_ID from the chip and verify
11236 * that it is sane. If it doesn't look good, we fall back
11237 * to either the hard-coded table based PHY_ID and failing
11238 * that the value found in the eeprom area.
11239 */
11240 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11241 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11242
11243 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11244 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11245 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11246
11247 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11248 }
11249
11250 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11251 tp->phy_id = hw_phy_id;
11252 if (hw_phy_id_masked == PHY_ID_BCM8002)
11253 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11254 else
11255 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11256 } else {
11257 if (tp->phy_id != PHY_ID_INVALID) {
11258 /* Do nothing, phy ID already set up in
11259 * tg3_get_eeprom_hw_cfg().
11260 */
11261 } else {
11262 struct subsys_tbl_ent *p;
11263
11264 /* No eeprom signature? Try the hardcoded
11265 * subsys device table.
11266 */
11267 p = lookup_by_subsys(tp);
11268 if (!p)
11269 return -ENODEV;
11270
11271 tp->phy_id = p->phy_id;
11272 if (!tp->phy_id ||
11273 tp->phy_id == PHY_ID_BCM8002)
11274 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11275 }
11276 }
11277
11278 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11279 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11280 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11281 u32 bmsr, adv_reg, tg3_ctrl, mask;
11282
11283 tg3_readphy(tp, MII_BMSR, &bmsr);
11284 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11285 (bmsr & BMSR_LSTATUS))
11286 goto skip_phy_reset;
11287
11288 err = tg3_phy_reset(tp);
11289 if (err)
11290 return err;
11291
11292 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11293 ADVERTISE_100HALF | ADVERTISE_100FULL |
11294 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11295 tg3_ctrl = 0;
11296 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11297 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11298 MII_TG3_CTRL_ADV_1000_FULL);
11299 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11300 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11301 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11302 MII_TG3_CTRL_ENABLE_AS_MASTER);
11303 }
11304
11305 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11306 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11307 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11308 if (!tg3_copper_is_advertising_all(tp, mask)) {
11309 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11310
11311 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11312 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11313
11314 tg3_writephy(tp, MII_BMCR,
11315 BMCR_ANENABLE | BMCR_ANRESTART);
11316 }
11317 tg3_phy_set_wirespeed(tp);
11318
11319 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11320 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11321 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11322 }
11323
11324 skip_phy_reset:
11325 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11326 err = tg3_init_5401phy_dsp(tp);
11327 if (err)
11328 return err;
11329 }
11330
11331 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11332 err = tg3_init_5401phy_dsp(tp);
11333 }
11334
11335 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11336 tp->link_config.advertising =
11337 (ADVERTISED_1000baseT_Half |
11338 ADVERTISED_1000baseT_Full |
11339 ADVERTISED_Autoneg |
11340 ADVERTISED_FIBRE);
11341 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11342 tp->link_config.advertising &=
11343 ~(ADVERTISED_1000baseT_Half |
11344 ADVERTISED_1000baseT_Full);
11345
11346 return err;
11347 }
11348
11349 static void __devinit tg3_read_partno(struct tg3 *tp)
11350 {
11351 unsigned char vpd_data[256]; /* in little-endian format */
11352 unsigned int i;
11353 u32 magic;
11354
11355 if (tg3_nvram_read(tp, 0x0, &magic))
11356 goto out_not_found;
11357
11358 if (magic == TG3_EEPROM_MAGIC) {
11359 for (i = 0; i < 256; i += 4) {
11360 u32 tmp;
11361
11362 /* The data is in little-endian format in NVRAM.
11363 * Use the big-endian read routines to preserve
11364 * the byte order as it exists in NVRAM.
11365 */
11366 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11367 goto out_not_found;
11368
11369 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11370 }
11371 } else {
11372 int vpd_cap;
11373
11374 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11375 for (i = 0; i < 256; i += 4) {
11376 u32 tmp, j = 0;
11377 __le32 v;
11378 u16 tmp16;
11379
11380 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11381 i);
11382 while (j++ < 100) {
11383 pci_read_config_word(tp->pdev, vpd_cap +
11384 PCI_VPD_ADDR, &tmp16);
11385 if (tmp16 & 0x8000)
11386 break;
11387 msleep(1);
11388 }
11389 if (!(tmp16 & 0x8000))
11390 goto out_not_found;
11391
11392 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11393 &tmp);
11394 v = cpu_to_le32(tmp);
11395 memcpy(&vpd_data[i], &v, sizeof(v));
11396 }
11397 }
11398
11399 /* Now parse and find the part number. */
11400 for (i = 0; i < 254; ) {
11401 unsigned char val = vpd_data[i];
11402 unsigned int block_end;
11403
11404 if (val == 0x82 || val == 0x91) {
11405 i = (i + 3 +
11406 (vpd_data[i + 1] +
11407 (vpd_data[i + 2] << 8)));
11408 continue;
11409 }
11410
11411 if (val != 0x90)
11412 goto out_not_found;
11413
11414 block_end = (i + 3 +
11415 (vpd_data[i + 1] +
11416 (vpd_data[i + 2] << 8)));
11417 i += 3;
11418
11419 if (block_end > 256)
11420 goto out_not_found;
11421
11422 while (i < (block_end - 2)) {
11423 if (vpd_data[i + 0] == 'P' &&
11424 vpd_data[i + 1] == 'N') {
11425 int partno_len = vpd_data[i + 2];
11426
11427 i += 3;
11428 if (partno_len > 24 || (partno_len + i) > 256)
11429 goto out_not_found;
11430
11431 memcpy(tp->board_part_number,
11432 &vpd_data[i], partno_len);
11433
11434 /* Success. */
11435 return;
11436 }
11437 i += 3 + vpd_data[i + 2];
11438 }
11439
11440 /* Part number not found. */
11441 goto out_not_found;
11442 }
11443
11444 out_not_found:
11445 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11446 strcpy(tp->board_part_number, "BCM95906");
11447 else
11448 strcpy(tp->board_part_number, "none");
11449 }
11450
11451 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11452 {
11453 u32 val;
11454
11455 if (tg3_nvram_read(tp, offset, &val) ||
11456 (val & 0xfc000000) != 0x0c000000 ||
11457 tg3_nvram_read(tp, offset + 4, &val) ||
11458 val != 0)
11459 return 0;
11460
11461 return 1;
11462 }
11463
11464 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11465 {
11466 u32 val, offset, start, ver_offset;
11467 int i;
11468 bool newver = false;
11469
11470 if (tg3_nvram_read(tp, 0xc, &offset) ||
11471 tg3_nvram_read(tp, 0x4, &start))
11472 return;
11473
11474 offset = tg3_nvram_logical_addr(tp, offset);
11475
11476 if (tg3_nvram_read(tp, offset, &val))
11477 return;
11478
11479 if ((val & 0xfc000000) == 0x0c000000) {
11480 if (tg3_nvram_read(tp, offset + 4, &val))
11481 return;
11482
11483 if (val == 0)
11484 newver = true;
11485 }
11486
11487 if (newver) {
11488 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11489 return;
11490
11491 offset = offset + ver_offset - start;
11492 for (i = 0; i < 16; i += 4) {
11493 __be32 v;
11494 if (tg3_nvram_read_be32(tp, offset + i, &v))
11495 return;
11496
11497 memcpy(tp->fw_ver + i, &v, sizeof(v));
11498 }
11499 } else {
11500 u32 major, minor;
11501
11502 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11503 return;
11504
11505 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11506 TG3_NVM_BCVER_MAJSFT;
11507 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11508 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11509 }
11510 }
11511
11512 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11513 {
11514 u32 val, major, minor;
11515
11516 /* Use native endian representation */
11517 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11518 return;
11519
11520 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11521 TG3_NVM_HWSB_CFG1_MAJSFT;
11522 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11523 TG3_NVM_HWSB_CFG1_MINSFT;
11524
11525 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11526 }
11527
11528 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11529 {
11530 u32 offset, major, minor, build;
11531
11532 tp->fw_ver[0] = 's';
11533 tp->fw_ver[1] = 'b';
11534 tp->fw_ver[2] = '\0';
11535
11536 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11537 return;
11538
11539 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11540 case TG3_EEPROM_SB_REVISION_0:
11541 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11542 break;
11543 case TG3_EEPROM_SB_REVISION_2:
11544 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11545 break;
11546 case TG3_EEPROM_SB_REVISION_3:
11547 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11548 break;
11549 default:
11550 return;
11551 }
11552
11553 if (tg3_nvram_read(tp, offset, &val))
11554 return;
11555
11556 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11557 TG3_EEPROM_SB_EDH_BLD_SHFT;
11558 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11559 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11560 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11561
11562 if (minor > 99 || build > 26)
11563 return;
11564
11565 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11566
11567 if (build > 0) {
11568 tp->fw_ver[8] = 'a' + build - 1;
11569 tp->fw_ver[9] = '\0';
11570 }
11571 }
11572
11573 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11574 {
11575 u32 val, offset, start;
11576 int i, vlen;
11577
11578 for (offset = TG3_NVM_DIR_START;
11579 offset < TG3_NVM_DIR_END;
11580 offset += TG3_NVM_DIRENT_SIZE) {
11581 if (tg3_nvram_read(tp, offset, &val))
11582 return;
11583
11584 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11585 break;
11586 }
11587
11588 if (offset == TG3_NVM_DIR_END)
11589 return;
11590
11591 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11592 start = 0x08000000;
11593 else if (tg3_nvram_read(tp, offset - 4, &start))
11594 return;
11595
11596 if (tg3_nvram_read(tp, offset + 4, &offset) ||
11597 !tg3_fw_img_is_valid(tp, offset) ||
11598 tg3_nvram_read(tp, offset + 8, &val))
11599 return;
11600
11601 offset += val - start;
11602
11603 vlen = strlen(tp->fw_ver);
11604
11605 tp->fw_ver[vlen++] = ',';
11606 tp->fw_ver[vlen++] = ' ';
11607
11608 for (i = 0; i < 4; i++) {
11609 __be32 v;
11610 if (tg3_nvram_read_be32(tp, offset, &v))
11611 return;
11612
11613 offset += sizeof(v);
11614
11615 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11616 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11617 break;
11618 }
11619
11620 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11621 vlen += sizeof(v);
11622 }
11623 }
11624
11625 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11626 {
11627 int vlen;
11628 u32 apedata;
11629
11630 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11631 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11632 return;
11633
11634 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11635 if (apedata != APE_SEG_SIG_MAGIC)
11636 return;
11637
11638 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11639 if (!(apedata & APE_FW_STATUS_READY))
11640 return;
11641
11642 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11643
11644 vlen = strlen(tp->fw_ver);
11645
11646 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11647 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11648 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11649 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11650 (apedata & APE_FW_VERSION_BLDMSK));
11651 }
11652
11653 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11654 {
11655 u32 val;
11656
11657 if (tg3_nvram_read(tp, 0, &val))
11658 return;
11659
11660 if (val == TG3_EEPROM_MAGIC)
11661 tg3_read_bc_ver(tp);
11662 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11663 tg3_read_sb_ver(tp, val);
11664 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11665 tg3_read_hwsb_ver(tp);
11666 else
11667 return;
11668
11669 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11670 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11671 return;
11672
11673 tg3_read_mgmtfw_ver(tp);
11674
11675 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11676 }
11677
11678 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11679
11680 static int __devinit tg3_get_invariants(struct tg3 *tp)
11681 {
11682 static struct pci_device_id write_reorder_chipsets[] = {
11683 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11684 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11685 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11686 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11687 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11688 PCI_DEVICE_ID_VIA_8385_0) },
11689 { },
11690 };
11691 u32 misc_ctrl_reg;
11692 u32 pci_state_reg, grc_misc_cfg;
11693 u32 val;
11694 u16 pci_cmd;
11695 int err;
11696
11697 /* Force memory write invalidate off. If we leave it on,
11698 * then on 5700_BX chips we have to enable a workaround.
11699 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11700 * to match the cacheline size. The Broadcom driver have this
11701 * workaround but turns MWI off all the times so never uses
11702 * it. This seems to suggest that the workaround is insufficient.
11703 */
11704 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11705 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11706 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11707
11708 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11709 * has the register indirect write enable bit set before
11710 * we try to access any of the MMIO registers. It is also
11711 * critical that the PCI-X hw workaround situation is decided
11712 * before that as well.
11713 */
11714 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11715 &misc_ctrl_reg);
11716
11717 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11718 MISC_HOST_CTRL_CHIPREV_SHIFT);
11719 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11720 u32 prod_id_asic_rev;
11721
11722 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11723 &prod_id_asic_rev);
11724 tp->pci_chip_rev_id = prod_id_asic_rev;
11725 }
11726
11727 /* Wrong chip ID in 5752 A0. This code can be removed later
11728 * as A0 is not in production.
11729 */
11730 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11731 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11732
11733 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11734 * we need to disable memory and use config. cycles
11735 * only to access all registers. The 5702/03 chips
11736 * can mistakenly decode the special cycles from the
11737 * ICH chipsets as memory write cycles, causing corruption
11738 * of register and memory space. Only certain ICH bridges
11739 * will drive special cycles with non-zero data during the
11740 * address phase which can fall within the 5703's address
11741 * range. This is not an ICH bug as the PCI spec allows
11742 * non-zero address during special cycles. However, only
11743 * these ICH bridges are known to drive non-zero addresses
11744 * during special cycles.
11745 *
11746 * Since special cycles do not cross PCI bridges, we only
11747 * enable this workaround if the 5703 is on the secondary
11748 * bus of these ICH bridges.
11749 */
11750 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11751 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11752 static struct tg3_dev_id {
11753 u32 vendor;
11754 u32 device;
11755 u32 rev;
11756 } ich_chipsets[] = {
11757 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11758 PCI_ANY_ID },
11759 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11760 PCI_ANY_ID },
11761 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11762 0xa },
11763 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11764 PCI_ANY_ID },
11765 { },
11766 };
11767 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11768 struct pci_dev *bridge = NULL;
11769
11770 while (pci_id->vendor != 0) {
11771 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11772 bridge);
11773 if (!bridge) {
11774 pci_id++;
11775 continue;
11776 }
11777 if (pci_id->rev != PCI_ANY_ID) {
11778 if (bridge->revision > pci_id->rev)
11779 continue;
11780 }
11781 if (bridge->subordinate &&
11782 (bridge->subordinate->number ==
11783 tp->pdev->bus->number)) {
11784
11785 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11786 pci_dev_put(bridge);
11787 break;
11788 }
11789 }
11790 }
11791
11792 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11793 static struct tg3_dev_id {
11794 u32 vendor;
11795 u32 device;
11796 } bridge_chipsets[] = {
11797 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11798 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11799 { },
11800 };
11801 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11802 struct pci_dev *bridge = NULL;
11803
11804 while (pci_id->vendor != 0) {
11805 bridge = pci_get_device(pci_id->vendor,
11806 pci_id->device,
11807 bridge);
11808 if (!bridge) {
11809 pci_id++;
11810 continue;
11811 }
11812 if (bridge->subordinate &&
11813 (bridge->subordinate->number <=
11814 tp->pdev->bus->number) &&
11815 (bridge->subordinate->subordinate >=
11816 tp->pdev->bus->number)) {
11817 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11818 pci_dev_put(bridge);
11819 break;
11820 }
11821 }
11822 }
11823
11824 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11825 * DMA addresses > 40-bit. This bridge may have other additional
11826 * 57xx devices behind it in some 4-port NIC designs for example.
11827 * Any tg3 device found behind the bridge will also need the 40-bit
11828 * DMA workaround.
11829 */
11830 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11831 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11832 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11833 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11834 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11835 }
11836 else {
11837 struct pci_dev *bridge = NULL;
11838
11839 do {
11840 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11841 PCI_DEVICE_ID_SERVERWORKS_EPB,
11842 bridge);
11843 if (bridge && bridge->subordinate &&
11844 (bridge->subordinate->number <=
11845 tp->pdev->bus->number) &&
11846 (bridge->subordinate->subordinate >=
11847 tp->pdev->bus->number)) {
11848 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11849 pci_dev_put(bridge);
11850 break;
11851 }
11852 } while (bridge);
11853 }
11854
11855 /* Initialize misc host control in PCI block. */
11856 tp->misc_host_ctrl |= (misc_ctrl_reg &
11857 MISC_HOST_CTRL_CHIPREV);
11858 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11859 tp->misc_host_ctrl);
11860
11861 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11862 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11863 tp->pdev_peer = tg3_find_peer(tp);
11864
11865 /* Intentionally exclude ASIC_REV_5906 */
11866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11868 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11869 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11870 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11871 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11872 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11873
11874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11876 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11877 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11878 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11879 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11880
11881 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11882 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11883 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11884
11885 /* 5700 B0 chips do not support checksumming correctly due
11886 * to hardware bugs.
11887 */
11888 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11889 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11890 else {
11891 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11892 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11893 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11894 tp->dev->features |= NETIF_F_IPV6_CSUM;
11895 }
11896
11897 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11898 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11899 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11900 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11901 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11902 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11903 tp->pdev_peer == tp->pdev))
11904 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11905
11906 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11907 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11908 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11909 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11910 } else {
11911 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11912 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11913 ASIC_REV_5750 &&
11914 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11915 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11916 }
11917 }
11918
11919 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11920 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11921 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11922
11923 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11924 &pci_state_reg);
11925
11926 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11927 if (tp->pcie_cap != 0) {
11928 u16 lnkctl;
11929
11930 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11931
11932 pcie_set_readrq(tp->pdev, 4096);
11933
11934 pci_read_config_word(tp->pdev,
11935 tp->pcie_cap + PCI_EXP_LNKCTL,
11936 &lnkctl);
11937 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11938 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11939 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11943 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
11944 }
11945 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
11946 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11947 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11948 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11949 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11950 if (!tp->pcix_cap) {
11951 printk(KERN_ERR PFX "Cannot find PCI-X "
11952 "capability, aborting.\n");
11953 return -EIO;
11954 }
11955
11956 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
11957 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11958 }
11959
11960 /* If we have an AMD 762 or VIA K8T800 chipset, write
11961 * reordering to the mailbox registers done by the host
11962 * controller can cause major troubles. We read back from
11963 * every mailbox register write to force the writes to be
11964 * posted to the chip in order.
11965 */
11966 if (pci_dev_present(write_reorder_chipsets) &&
11967 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11968 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11969
11970 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
11971 &tp->pci_cacheline_sz);
11972 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11973 &tp->pci_lat_timer);
11974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11975 tp->pci_lat_timer < 64) {
11976 tp->pci_lat_timer = 64;
11977 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11978 tp->pci_lat_timer);
11979 }
11980
11981 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11982 /* 5700 BX chips need to have their TX producer index
11983 * mailboxes written twice to workaround a bug.
11984 */
11985 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
11986
11987 /* If we are in PCI-X mode, enable register write workaround.
11988 *
11989 * The workaround is to use indirect register accesses
11990 * for all chip writes not to mailbox registers.
11991 */
11992 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11993 u32 pm_reg;
11994
11995 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11996
11997 /* The chip can have it's power management PCI config
11998 * space registers clobbered due to this bug.
11999 * So explicitly force the chip into D0 here.
12000 */
12001 pci_read_config_dword(tp->pdev,
12002 tp->pm_cap + PCI_PM_CTRL,
12003 &pm_reg);
12004 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12005 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12006 pci_write_config_dword(tp->pdev,
12007 tp->pm_cap + PCI_PM_CTRL,
12008 pm_reg);
12009
12010 /* Also, force SERR#/PERR# in PCI command. */
12011 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12012 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12013 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12014 }
12015 }
12016
12017 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12018 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12019 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12020 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12021
12022 /* Chip-specific fixup from Broadcom driver */
12023 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12024 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12025 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12026 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12027 }
12028
12029 /* Default fast path register access methods */
12030 tp->read32 = tg3_read32;
12031 tp->write32 = tg3_write32;
12032 tp->read32_mbox = tg3_read32;
12033 tp->write32_mbox = tg3_write32;
12034 tp->write32_tx_mbox = tg3_write32;
12035 tp->write32_rx_mbox = tg3_write32;
12036
12037 /* Various workaround register access methods */
12038 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12039 tp->write32 = tg3_write_indirect_reg32;
12040 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12041 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12042 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12043 /*
12044 * Back to back register writes can cause problems on these
12045 * chips, the workaround is to read back all reg writes
12046 * except those to mailbox regs.
12047 *
12048 * See tg3_write_indirect_reg32().
12049 */
12050 tp->write32 = tg3_write_flush_reg32;
12051 }
12052
12053
12054 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12055 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12056 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12057 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12058 tp->write32_rx_mbox = tg3_write_flush_reg32;
12059 }
12060
12061 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12062 tp->read32 = tg3_read_indirect_reg32;
12063 tp->write32 = tg3_write_indirect_reg32;
12064 tp->read32_mbox = tg3_read_indirect_mbox;
12065 tp->write32_mbox = tg3_write_indirect_mbox;
12066 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12067 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12068
12069 iounmap(tp->regs);
12070 tp->regs = NULL;
12071
12072 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12073 pci_cmd &= ~PCI_COMMAND_MEMORY;
12074 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12075 }
12076 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12077 tp->read32_mbox = tg3_read32_mbox_5906;
12078 tp->write32_mbox = tg3_write32_mbox_5906;
12079 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12080 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12081 }
12082
12083 if (tp->write32 == tg3_write_indirect_reg32 ||
12084 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12085 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12087 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12088
12089 /* Get eeprom hw config before calling tg3_set_power_state().
12090 * In particular, the TG3_FLG2_IS_NIC flag must be
12091 * determined before calling tg3_set_power_state() so that
12092 * we know whether or not to switch out of Vaux power.
12093 * When the flag is set, it means that GPIO1 is used for eeprom
12094 * write protect and also implies that it is a LOM where GPIOs
12095 * are not used to switch power.
12096 */
12097 tg3_get_eeprom_hw_cfg(tp);
12098
12099 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12100 /* Allow reads and writes to the
12101 * APE register and memory space.
12102 */
12103 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12104 PCISTATE_ALLOW_APE_SHMEM_WR;
12105 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12106 pci_state_reg);
12107 }
12108
12109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12113 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12114
12115 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12116 * GPIO1 driven high will bring 5700's external PHY out of reset.
12117 * It is also used as eeprom write protect on LOMs.
12118 */
12119 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12120 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12121 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12122 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12123 GRC_LCLCTRL_GPIO_OUTPUT1);
12124 /* Unused GPIO3 must be driven as output on 5752 because there
12125 * are no pull-up resistors on unused GPIO pins.
12126 */
12127 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12128 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12129
12130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12131 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12132 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12133
12134 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12135 /* Turn off the debug UART. */
12136 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12137 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12138 /* Keep VMain power. */
12139 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12140 GRC_LCLCTRL_GPIO_OUTPUT0;
12141 }
12142
12143 /* Force the chip into D0. */
12144 err = tg3_set_power_state(tp, PCI_D0);
12145 if (err) {
12146 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12147 pci_name(tp->pdev));
12148 return err;
12149 }
12150
12151 /* Derive initial jumbo mode from MTU assigned in
12152 * ether_setup() via the alloc_etherdev() call
12153 */
12154 if (tp->dev->mtu > ETH_DATA_LEN &&
12155 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12156 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12157
12158 /* Determine WakeOnLan speed to use. */
12159 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12160 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12161 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12162 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12163 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12164 } else {
12165 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12166 }
12167
12168 /* A few boards don't want Ethernet@WireSpeed phy feature */
12169 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12170 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12171 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12172 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12173 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12174 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12175 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12176
12177 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12178 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12179 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12180 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12181 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12182
12183 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12184 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12185 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12186 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12187 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12188 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12191 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12192 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12193 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12194 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12195 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12196 } else
12197 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12198 }
12199
12200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12201 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12202 tp->phy_otp = tg3_read_otp_phycfg(tp);
12203 if (tp->phy_otp == 0)
12204 tp->phy_otp = TG3_OTP_DEFAULT;
12205 }
12206
12207 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12208 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12209 else
12210 tp->mi_mode = MAC_MI_MODE_BASE;
12211
12212 tp->coalesce_mode = 0;
12213 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12214 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12215 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12216
12217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12219 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12220
12221 err = tg3_mdio_init(tp);
12222 if (err)
12223 return err;
12224
12225 /* Initialize data/descriptor byte/word swapping. */
12226 val = tr32(GRC_MODE);
12227 val &= GRC_MODE_HOST_STACKUP;
12228 tw32(GRC_MODE, val | tp->grc_mode);
12229
12230 tg3_switch_clocks(tp);
12231
12232 /* Clear this out for sanity. */
12233 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12234
12235 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12236 &pci_state_reg);
12237 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12238 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12239 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12240
12241 if (chiprevid == CHIPREV_ID_5701_A0 ||
12242 chiprevid == CHIPREV_ID_5701_B0 ||
12243 chiprevid == CHIPREV_ID_5701_B2 ||
12244 chiprevid == CHIPREV_ID_5701_B5) {
12245 void __iomem *sram_base;
12246
12247 /* Write some dummy words into the SRAM status block
12248 * area, see if it reads back correctly. If the return
12249 * value is bad, force enable the PCIX workaround.
12250 */
12251 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12252
12253 writel(0x00000000, sram_base);
12254 writel(0x00000000, sram_base + 4);
12255 writel(0xffffffff, sram_base + 4);
12256 if (readl(sram_base) != 0x00000000)
12257 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12258 }
12259 }
12260
12261 udelay(50);
12262 tg3_nvram_init(tp);
12263
12264 grc_misc_cfg = tr32(GRC_MISC_CFG);
12265 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12266
12267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12268 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12269 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12270 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12271
12272 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12273 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12274 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12275 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12276 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12277 HOSTCC_MODE_CLRTICK_TXBD);
12278
12279 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12280 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12281 tp->misc_host_ctrl);
12282 }
12283
12284 /* Preserve the APE MAC_MODE bits */
12285 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12286 tp->mac_mode = tr32(MAC_MODE) |
12287 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12288 else
12289 tp->mac_mode = TG3_DEF_MAC_MODE;
12290
12291 /* these are limited to 10/100 only */
12292 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12293 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12294 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12295 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12296 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12297 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12298 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12299 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12300 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12301 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12302 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12303 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12304 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12305 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12306
12307 err = tg3_phy_probe(tp);
12308 if (err) {
12309 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12310 pci_name(tp->pdev), err);
12311 /* ... but do not return immediately ... */
12312 tg3_mdio_fini(tp);
12313 }
12314
12315 tg3_read_partno(tp);
12316 tg3_read_fw_ver(tp);
12317
12318 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12319 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12320 } else {
12321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12322 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12323 else
12324 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12325 }
12326
12327 /* 5700 {AX,BX} chips have a broken status block link
12328 * change bit implementation, so we must use the
12329 * status register in those cases.
12330 */
12331 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12332 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12333 else
12334 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12335
12336 /* The led_ctrl is set during tg3_phy_probe, here we might
12337 * have to force the link status polling mechanism based
12338 * upon subsystem IDs.
12339 */
12340 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12341 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12342 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12343 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12344 TG3_FLAG_USE_LINKCHG_REG);
12345 }
12346
12347 /* For all SERDES we poll the MAC status register. */
12348 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12349 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12350 else
12351 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12352
12353 tp->rx_offset = NET_IP_ALIGN;
12354 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12355 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12356 tp->rx_offset = 0;
12357
12358 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12359
12360 /* Increment the rx prod index on the rx std ring by at most
12361 * 8 for these chips to workaround hw errata.
12362 */
12363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12365 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12366 tp->rx_std_max_post = 8;
12367
12368 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12369 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12370 PCIE_PWR_MGMT_L1_THRESH_MSK;
12371
12372 return err;
12373 }
12374
12375 #ifdef CONFIG_SPARC
12376 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12377 {
12378 struct net_device *dev = tp->dev;
12379 struct pci_dev *pdev = tp->pdev;
12380 struct device_node *dp = pci_device_to_OF_node(pdev);
12381 const unsigned char *addr;
12382 int len;
12383
12384 addr = of_get_property(dp, "local-mac-address", &len);
12385 if (addr && len == 6) {
12386 memcpy(dev->dev_addr, addr, 6);
12387 memcpy(dev->perm_addr, dev->dev_addr, 6);
12388 return 0;
12389 }
12390 return -ENODEV;
12391 }
12392
12393 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12394 {
12395 struct net_device *dev = tp->dev;
12396
12397 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12398 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12399 return 0;
12400 }
12401 #endif
12402
12403 static int __devinit tg3_get_device_address(struct tg3 *tp)
12404 {
12405 struct net_device *dev = tp->dev;
12406 u32 hi, lo, mac_offset;
12407 int addr_ok = 0;
12408
12409 #ifdef CONFIG_SPARC
12410 if (!tg3_get_macaddr_sparc(tp))
12411 return 0;
12412 #endif
12413
12414 mac_offset = 0x7c;
12415 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12416 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12417 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12418 mac_offset = 0xcc;
12419 if (tg3_nvram_lock(tp))
12420 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12421 else
12422 tg3_nvram_unlock(tp);
12423 }
12424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12425 mac_offset = 0x10;
12426
12427 /* First try to get it from MAC address mailbox. */
12428 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12429 if ((hi >> 16) == 0x484b) {
12430 dev->dev_addr[0] = (hi >> 8) & 0xff;
12431 dev->dev_addr[1] = (hi >> 0) & 0xff;
12432
12433 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12434 dev->dev_addr[2] = (lo >> 24) & 0xff;
12435 dev->dev_addr[3] = (lo >> 16) & 0xff;
12436 dev->dev_addr[4] = (lo >> 8) & 0xff;
12437 dev->dev_addr[5] = (lo >> 0) & 0xff;
12438
12439 /* Some old bootcode may report a 0 MAC address in SRAM */
12440 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12441 }
12442 if (!addr_ok) {
12443 /* Next, try NVRAM. */
12444 if (!tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12445 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12446 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12447 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12448 }
12449 /* Finally just fetch it out of the MAC control regs. */
12450 else {
12451 hi = tr32(MAC_ADDR_0_HIGH);
12452 lo = tr32(MAC_ADDR_0_LOW);
12453
12454 dev->dev_addr[5] = lo & 0xff;
12455 dev->dev_addr[4] = (lo >> 8) & 0xff;
12456 dev->dev_addr[3] = (lo >> 16) & 0xff;
12457 dev->dev_addr[2] = (lo >> 24) & 0xff;
12458 dev->dev_addr[1] = hi & 0xff;
12459 dev->dev_addr[0] = (hi >> 8) & 0xff;
12460 }
12461 }
12462
12463 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12464 #ifdef CONFIG_SPARC
12465 if (!tg3_get_default_macaddr_sparc(tp))
12466 return 0;
12467 #endif
12468 return -EINVAL;
12469 }
12470 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12471 return 0;
12472 }
12473
12474 #define BOUNDARY_SINGLE_CACHELINE 1
12475 #define BOUNDARY_MULTI_CACHELINE 2
12476
12477 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12478 {
12479 int cacheline_size;
12480 u8 byte;
12481 int goal;
12482
12483 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12484 if (byte == 0)
12485 cacheline_size = 1024;
12486 else
12487 cacheline_size = (int) byte * 4;
12488
12489 /* On 5703 and later chips, the boundary bits have no
12490 * effect.
12491 */
12492 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12493 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12494 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12495 goto out;
12496
12497 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12498 goal = BOUNDARY_MULTI_CACHELINE;
12499 #else
12500 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12501 goal = BOUNDARY_SINGLE_CACHELINE;
12502 #else
12503 goal = 0;
12504 #endif
12505 #endif
12506
12507 if (!goal)
12508 goto out;
12509
12510 /* PCI controllers on most RISC systems tend to disconnect
12511 * when a device tries to burst across a cache-line boundary.
12512 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12513 *
12514 * Unfortunately, for PCI-E there are only limited
12515 * write-side controls for this, and thus for reads
12516 * we will still get the disconnects. We'll also waste
12517 * these PCI cycles for both read and write for chips
12518 * other than 5700 and 5701 which do not implement the
12519 * boundary bits.
12520 */
12521 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12522 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12523 switch (cacheline_size) {
12524 case 16:
12525 case 32:
12526 case 64:
12527 case 128:
12528 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12529 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12530 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12531 } else {
12532 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12533 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12534 }
12535 break;
12536
12537 case 256:
12538 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12539 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12540 break;
12541
12542 default:
12543 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12544 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12545 break;
12546 }
12547 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12548 switch (cacheline_size) {
12549 case 16:
12550 case 32:
12551 case 64:
12552 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12553 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12554 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12555 break;
12556 }
12557 /* fallthrough */
12558 case 128:
12559 default:
12560 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12561 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12562 break;
12563 }
12564 } else {
12565 switch (cacheline_size) {
12566 case 16:
12567 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12568 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12569 DMA_RWCTRL_WRITE_BNDRY_16);
12570 break;
12571 }
12572 /* fallthrough */
12573 case 32:
12574 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12575 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12576 DMA_RWCTRL_WRITE_BNDRY_32);
12577 break;
12578 }
12579 /* fallthrough */
12580 case 64:
12581 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12582 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12583 DMA_RWCTRL_WRITE_BNDRY_64);
12584 break;
12585 }
12586 /* fallthrough */
12587 case 128:
12588 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12589 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12590 DMA_RWCTRL_WRITE_BNDRY_128);
12591 break;
12592 }
12593 /* fallthrough */
12594 case 256:
12595 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12596 DMA_RWCTRL_WRITE_BNDRY_256);
12597 break;
12598 case 512:
12599 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12600 DMA_RWCTRL_WRITE_BNDRY_512);
12601 break;
12602 case 1024:
12603 default:
12604 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12605 DMA_RWCTRL_WRITE_BNDRY_1024);
12606 break;
12607 }
12608 }
12609
12610 out:
12611 return val;
12612 }
12613
12614 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12615 {
12616 struct tg3_internal_buffer_desc test_desc;
12617 u32 sram_dma_descs;
12618 int i, ret;
12619
12620 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12621
12622 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12623 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12624 tw32(RDMAC_STATUS, 0);
12625 tw32(WDMAC_STATUS, 0);
12626
12627 tw32(BUFMGR_MODE, 0);
12628 tw32(FTQ_RESET, 0);
12629
12630 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12631 test_desc.addr_lo = buf_dma & 0xffffffff;
12632 test_desc.nic_mbuf = 0x00002100;
12633 test_desc.len = size;
12634
12635 /*
12636 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12637 * the *second* time the tg3 driver was getting loaded after an
12638 * initial scan.
12639 *
12640 * Broadcom tells me:
12641 * ...the DMA engine is connected to the GRC block and a DMA
12642 * reset may affect the GRC block in some unpredictable way...
12643 * The behavior of resets to individual blocks has not been tested.
12644 *
12645 * Broadcom noted the GRC reset will also reset all sub-components.
12646 */
12647 if (to_device) {
12648 test_desc.cqid_sqid = (13 << 8) | 2;
12649
12650 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12651 udelay(40);
12652 } else {
12653 test_desc.cqid_sqid = (16 << 8) | 7;
12654
12655 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12656 udelay(40);
12657 }
12658 test_desc.flags = 0x00000005;
12659
12660 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12661 u32 val;
12662
12663 val = *(((u32 *)&test_desc) + i);
12664 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12665 sram_dma_descs + (i * sizeof(u32)));
12666 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12667 }
12668 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12669
12670 if (to_device) {
12671 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12672 } else {
12673 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12674 }
12675
12676 ret = -ENODEV;
12677 for (i = 0; i < 40; i++) {
12678 u32 val;
12679
12680 if (to_device)
12681 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12682 else
12683 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12684 if ((val & 0xffff) == sram_dma_descs) {
12685 ret = 0;
12686 break;
12687 }
12688
12689 udelay(100);
12690 }
12691
12692 return ret;
12693 }
12694
12695 #define TEST_BUFFER_SIZE 0x2000
12696
12697 static int __devinit tg3_test_dma(struct tg3 *tp)
12698 {
12699 dma_addr_t buf_dma;
12700 u32 *buf, saved_dma_rwctrl;
12701 int ret;
12702
12703 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12704 if (!buf) {
12705 ret = -ENOMEM;
12706 goto out_nofree;
12707 }
12708
12709 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12710 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12711
12712 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12713
12714 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12715 /* DMA read watermark not used on PCIE */
12716 tp->dma_rwctrl |= 0x00180000;
12717 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12719 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12720 tp->dma_rwctrl |= 0x003f0000;
12721 else
12722 tp->dma_rwctrl |= 0x003f000f;
12723 } else {
12724 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12725 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12726 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12727 u32 read_water = 0x7;
12728
12729 /* If the 5704 is behind the EPB bridge, we can
12730 * do the less restrictive ONE_DMA workaround for
12731 * better performance.
12732 */
12733 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12734 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12735 tp->dma_rwctrl |= 0x8000;
12736 else if (ccval == 0x6 || ccval == 0x7)
12737 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12738
12739 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12740 read_water = 4;
12741 /* Set bit 23 to enable PCIX hw bug fix */
12742 tp->dma_rwctrl |=
12743 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12744 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12745 (1 << 23);
12746 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12747 /* 5780 always in PCIX mode */
12748 tp->dma_rwctrl |= 0x00144000;
12749 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12750 /* 5714 always in PCIX mode */
12751 tp->dma_rwctrl |= 0x00148000;
12752 } else {
12753 tp->dma_rwctrl |= 0x001b000f;
12754 }
12755 }
12756
12757 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12758 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12759 tp->dma_rwctrl &= 0xfffffff0;
12760
12761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12762 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12763 /* Remove this if it causes problems for some boards. */
12764 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12765
12766 /* On 5700/5701 chips, we need to set this bit.
12767 * Otherwise the chip will issue cacheline transactions
12768 * to streamable DMA memory with not all the byte
12769 * enables turned on. This is an error on several
12770 * RISC PCI controllers, in particular sparc64.
12771 *
12772 * On 5703/5704 chips, this bit has been reassigned
12773 * a different meaning. In particular, it is used
12774 * on those chips to enable a PCI-X workaround.
12775 */
12776 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12777 }
12778
12779 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12780
12781 #if 0
12782 /* Unneeded, already done by tg3_get_invariants. */
12783 tg3_switch_clocks(tp);
12784 #endif
12785
12786 ret = 0;
12787 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12788 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12789 goto out;
12790
12791 /* It is best to perform DMA test with maximum write burst size
12792 * to expose the 5700/5701 write DMA bug.
12793 */
12794 saved_dma_rwctrl = tp->dma_rwctrl;
12795 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12796 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12797
12798 while (1) {
12799 u32 *p = buf, i;
12800
12801 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12802 p[i] = i;
12803
12804 /* Send the buffer to the chip. */
12805 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12806 if (ret) {
12807 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12808 break;
12809 }
12810
12811 #if 0
12812 /* validate data reached card RAM correctly. */
12813 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12814 u32 val;
12815 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12816 if (le32_to_cpu(val) != p[i]) {
12817 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12818 /* ret = -ENODEV here? */
12819 }
12820 p[i] = 0;
12821 }
12822 #endif
12823 /* Now read it back. */
12824 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12825 if (ret) {
12826 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12827
12828 break;
12829 }
12830
12831 /* Verify it. */
12832 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12833 if (p[i] == i)
12834 continue;
12835
12836 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12837 DMA_RWCTRL_WRITE_BNDRY_16) {
12838 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12839 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12840 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12841 break;
12842 } else {
12843 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12844 ret = -ENODEV;
12845 goto out;
12846 }
12847 }
12848
12849 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12850 /* Success. */
12851 ret = 0;
12852 break;
12853 }
12854 }
12855 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12856 DMA_RWCTRL_WRITE_BNDRY_16) {
12857 static struct pci_device_id dma_wait_state_chipsets[] = {
12858 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12859 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12860 { },
12861 };
12862
12863 /* DMA test passed without adjusting DMA boundary,
12864 * now look for chipsets that are known to expose the
12865 * DMA bug without failing the test.
12866 */
12867 if (pci_dev_present(dma_wait_state_chipsets)) {
12868 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12869 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12870 }
12871 else
12872 /* Safe to use the calculated DMA boundary. */
12873 tp->dma_rwctrl = saved_dma_rwctrl;
12874
12875 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12876 }
12877
12878 out:
12879 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12880 out_nofree:
12881 return ret;
12882 }
12883
12884 static void __devinit tg3_init_link_config(struct tg3 *tp)
12885 {
12886 tp->link_config.advertising =
12887 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12888 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12889 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12890 ADVERTISED_Autoneg | ADVERTISED_MII);
12891 tp->link_config.speed = SPEED_INVALID;
12892 tp->link_config.duplex = DUPLEX_INVALID;
12893 tp->link_config.autoneg = AUTONEG_ENABLE;
12894 tp->link_config.active_speed = SPEED_INVALID;
12895 tp->link_config.active_duplex = DUPLEX_INVALID;
12896 tp->link_config.phy_is_low_power = 0;
12897 tp->link_config.orig_speed = SPEED_INVALID;
12898 tp->link_config.orig_duplex = DUPLEX_INVALID;
12899 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12900 }
12901
12902 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12903 {
12904 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12905 tp->bufmgr_config.mbuf_read_dma_low_water =
12906 DEFAULT_MB_RDMA_LOW_WATER_5705;
12907 tp->bufmgr_config.mbuf_mac_rx_low_water =
12908 DEFAULT_MB_MACRX_LOW_WATER_5705;
12909 tp->bufmgr_config.mbuf_high_water =
12910 DEFAULT_MB_HIGH_WATER_5705;
12911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12912 tp->bufmgr_config.mbuf_mac_rx_low_water =
12913 DEFAULT_MB_MACRX_LOW_WATER_5906;
12914 tp->bufmgr_config.mbuf_high_water =
12915 DEFAULT_MB_HIGH_WATER_5906;
12916 }
12917
12918 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12919 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12920 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12921 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12922 tp->bufmgr_config.mbuf_high_water_jumbo =
12923 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12924 } else {
12925 tp->bufmgr_config.mbuf_read_dma_low_water =
12926 DEFAULT_MB_RDMA_LOW_WATER;
12927 tp->bufmgr_config.mbuf_mac_rx_low_water =
12928 DEFAULT_MB_MACRX_LOW_WATER;
12929 tp->bufmgr_config.mbuf_high_water =
12930 DEFAULT_MB_HIGH_WATER;
12931
12932 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12933 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12934 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12935 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12936 tp->bufmgr_config.mbuf_high_water_jumbo =
12937 DEFAULT_MB_HIGH_WATER_JUMBO;
12938 }
12939
12940 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12941 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12942 }
12943
12944 static char * __devinit tg3_phy_string(struct tg3 *tp)
12945 {
12946 switch (tp->phy_id & PHY_ID_MASK) {
12947 case PHY_ID_BCM5400: return "5400";
12948 case PHY_ID_BCM5401: return "5401";
12949 case PHY_ID_BCM5411: return "5411";
12950 case PHY_ID_BCM5701: return "5701";
12951 case PHY_ID_BCM5703: return "5703";
12952 case PHY_ID_BCM5704: return "5704";
12953 case PHY_ID_BCM5705: return "5705";
12954 case PHY_ID_BCM5750: return "5750";
12955 case PHY_ID_BCM5752: return "5752";
12956 case PHY_ID_BCM5714: return "5714";
12957 case PHY_ID_BCM5780: return "5780";
12958 case PHY_ID_BCM5755: return "5755";
12959 case PHY_ID_BCM5787: return "5787";
12960 case PHY_ID_BCM5784: return "5784";
12961 case PHY_ID_BCM5756: return "5722/5756";
12962 case PHY_ID_BCM5906: return "5906";
12963 case PHY_ID_BCM5761: return "5761";
12964 case PHY_ID_BCM8002: return "8002/serdes";
12965 case 0: return "serdes";
12966 default: return "unknown";
12967 }
12968 }
12969
12970 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12971 {
12972 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12973 strcpy(str, "PCI Express");
12974 return str;
12975 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12976 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12977
12978 strcpy(str, "PCIX:");
12979
12980 if ((clock_ctrl == 7) ||
12981 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12982 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12983 strcat(str, "133MHz");
12984 else if (clock_ctrl == 0)
12985 strcat(str, "33MHz");
12986 else if (clock_ctrl == 2)
12987 strcat(str, "50MHz");
12988 else if (clock_ctrl == 4)
12989 strcat(str, "66MHz");
12990 else if (clock_ctrl == 6)
12991 strcat(str, "100MHz");
12992 } else {
12993 strcpy(str, "PCI:");
12994 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12995 strcat(str, "66MHz");
12996 else
12997 strcat(str, "33MHz");
12998 }
12999 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13000 strcat(str, ":32-bit");
13001 else
13002 strcat(str, ":64-bit");
13003 return str;
13004 }
13005
13006 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13007 {
13008 struct pci_dev *peer;
13009 unsigned int func, devnr = tp->pdev->devfn & ~7;
13010
13011 for (func = 0; func < 8; func++) {
13012 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13013 if (peer && peer != tp->pdev)
13014 break;
13015 pci_dev_put(peer);
13016 }
13017 /* 5704 can be configured in single-port mode, set peer to
13018 * tp->pdev in that case.
13019 */
13020 if (!peer) {
13021 peer = tp->pdev;
13022 return peer;
13023 }
13024
13025 /*
13026 * We don't need to keep the refcount elevated; there's no way
13027 * to remove one half of this device without removing the other
13028 */
13029 pci_dev_put(peer);
13030
13031 return peer;
13032 }
13033
13034 static void __devinit tg3_init_coal(struct tg3 *tp)
13035 {
13036 struct ethtool_coalesce *ec = &tp->coal;
13037
13038 memset(ec, 0, sizeof(*ec));
13039 ec->cmd = ETHTOOL_GCOALESCE;
13040 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13041 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13042 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13043 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13044 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13045 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13046 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13047 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13048 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13049
13050 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13051 HOSTCC_MODE_CLRTICK_TXBD)) {
13052 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13053 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13054 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13055 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13056 }
13057
13058 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13059 ec->rx_coalesce_usecs_irq = 0;
13060 ec->tx_coalesce_usecs_irq = 0;
13061 ec->stats_block_coalesce_usecs = 0;
13062 }
13063 }
13064
13065 static const struct net_device_ops tg3_netdev_ops = {
13066 .ndo_open = tg3_open,
13067 .ndo_stop = tg3_close,
13068 .ndo_start_xmit = tg3_start_xmit,
13069 .ndo_get_stats = tg3_get_stats,
13070 .ndo_validate_addr = eth_validate_addr,
13071 .ndo_set_multicast_list = tg3_set_rx_mode,
13072 .ndo_set_mac_address = tg3_set_mac_addr,
13073 .ndo_do_ioctl = tg3_ioctl,
13074 .ndo_tx_timeout = tg3_tx_timeout,
13075 .ndo_change_mtu = tg3_change_mtu,
13076 #if TG3_VLAN_TAG_USED
13077 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13078 #endif
13079 #ifdef CONFIG_NET_POLL_CONTROLLER
13080 .ndo_poll_controller = tg3_poll_controller,
13081 #endif
13082 };
13083
13084 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13085 .ndo_open = tg3_open,
13086 .ndo_stop = tg3_close,
13087 .ndo_start_xmit = tg3_start_xmit_dma_bug,
13088 .ndo_get_stats = tg3_get_stats,
13089 .ndo_validate_addr = eth_validate_addr,
13090 .ndo_set_multicast_list = tg3_set_rx_mode,
13091 .ndo_set_mac_address = tg3_set_mac_addr,
13092 .ndo_do_ioctl = tg3_ioctl,
13093 .ndo_tx_timeout = tg3_tx_timeout,
13094 .ndo_change_mtu = tg3_change_mtu,
13095 #if TG3_VLAN_TAG_USED
13096 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13097 #endif
13098 #ifdef CONFIG_NET_POLL_CONTROLLER
13099 .ndo_poll_controller = tg3_poll_controller,
13100 #endif
13101 };
13102
13103 static int __devinit tg3_init_one(struct pci_dev *pdev,
13104 const struct pci_device_id *ent)
13105 {
13106 static int tg3_version_printed = 0;
13107 struct net_device *dev;
13108 struct tg3 *tp;
13109 int err, pm_cap;
13110 char str[40];
13111 u64 dma_mask, persist_dma_mask;
13112
13113 if (tg3_version_printed++ == 0)
13114 printk(KERN_INFO "%s", version);
13115
13116 err = pci_enable_device(pdev);
13117 if (err) {
13118 printk(KERN_ERR PFX "Cannot enable PCI device, "
13119 "aborting.\n");
13120 return err;
13121 }
13122
13123 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13124 if (err) {
13125 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13126 "aborting.\n");
13127 goto err_out_disable_pdev;
13128 }
13129
13130 pci_set_master(pdev);
13131
13132 /* Find power-management capability. */
13133 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13134 if (pm_cap == 0) {
13135 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13136 "aborting.\n");
13137 err = -EIO;
13138 goto err_out_free_res;
13139 }
13140
13141 dev = alloc_etherdev(sizeof(*tp));
13142 if (!dev) {
13143 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13144 err = -ENOMEM;
13145 goto err_out_free_res;
13146 }
13147
13148 SET_NETDEV_DEV(dev, &pdev->dev);
13149
13150 #if TG3_VLAN_TAG_USED
13151 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13152 #endif
13153
13154 tp = netdev_priv(dev);
13155 tp->pdev = pdev;
13156 tp->dev = dev;
13157 tp->pm_cap = pm_cap;
13158 tp->rx_mode = TG3_DEF_RX_MODE;
13159 tp->tx_mode = TG3_DEF_TX_MODE;
13160
13161 if (tg3_debug > 0)
13162 tp->msg_enable = tg3_debug;
13163 else
13164 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13165
13166 /* The word/byte swap controls here control register access byte
13167 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13168 * setting below.
13169 */
13170 tp->misc_host_ctrl =
13171 MISC_HOST_CTRL_MASK_PCI_INT |
13172 MISC_HOST_CTRL_WORD_SWAP |
13173 MISC_HOST_CTRL_INDIR_ACCESS |
13174 MISC_HOST_CTRL_PCISTATE_RW;
13175
13176 /* The NONFRM (non-frame) byte/word swap controls take effect
13177 * on descriptor entries, anything which isn't packet data.
13178 *
13179 * The StrongARM chips on the board (one for tx, one for rx)
13180 * are running in big-endian mode.
13181 */
13182 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13183 GRC_MODE_WSWAP_NONFRM_DATA);
13184 #ifdef __BIG_ENDIAN
13185 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13186 #endif
13187 spin_lock_init(&tp->lock);
13188 spin_lock_init(&tp->indirect_lock);
13189 INIT_WORK(&tp->reset_task, tg3_reset_task);
13190
13191 tp->regs = pci_ioremap_bar(pdev, BAR_0);
13192 if (!tp->regs) {
13193 printk(KERN_ERR PFX "Cannot map device registers, "
13194 "aborting.\n");
13195 err = -ENOMEM;
13196 goto err_out_free_dev;
13197 }
13198
13199 tg3_init_link_config(tp);
13200
13201 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13202 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13203 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13204
13205 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13206 dev->ethtool_ops = &tg3_ethtool_ops;
13207 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13208 dev->irq = pdev->irq;
13209
13210 err = tg3_get_invariants(tp);
13211 if (err) {
13212 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13213 "aborting.\n");
13214 goto err_out_iounmap;
13215 }
13216
13217 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13219 dev->netdev_ops = &tg3_netdev_ops;
13220 else
13221 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13222
13223
13224 /* The EPB bridge inside 5714, 5715, and 5780 and any
13225 * device behind the EPB cannot support DMA addresses > 40-bit.
13226 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13227 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13228 * do DMA address check in tg3_start_xmit().
13229 */
13230 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13231 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13232 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13233 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13234 #ifdef CONFIG_HIGHMEM
13235 dma_mask = DMA_64BIT_MASK;
13236 #endif
13237 } else
13238 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13239
13240 /* Configure DMA attributes. */
13241 if (dma_mask > DMA_32BIT_MASK) {
13242 err = pci_set_dma_mask(pdev, dma_mask);
13243 if (!err) {
13244 dev->features |= NETIF_F_HIGHDMA;
13245 err = pci_set_consistent_dma_mask(pdev,
13246 persist_dma_mask);
13247 if (err < 0) {
13248 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13249 "DMA for consistent allocations\n");
13250 goto err_out_iounmap;
13251 }
13252 }
13253 }
13254 if (err || dma_mask == DMA_32BIT_MASK) {
13255 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13256 if (err) {
13257 printk(KERN_ERR PFX "No usable DMA configuration, "
13258 "aborting.\n");
13259 goto err_out_iounmap;
13260 }
13261 }
13262
13263 tg3_init_bufmgr_config(tp);
13264
13265 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13266 tp->fw_needed = FIRMWARE_TG3;
13267
13268 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13269 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13270 }
13271 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13272 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13273 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13274 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13275 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13276 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13277 } else {
13278 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13279 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13280 tp->fw_needed = FIRMWARE_TG3TSO5;
13281 else
13282 tp->fw_needed = FIRMWARE_TG3TSO;
13283 }
13284
13285 /* TSO is on by default on chips that support hardware TSO.
13286 * Firmware TSO on older chips gives lower performance, so it
13287 * is off by default, but can be enabled using ethtool.
13288 */
13289 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13290 if (dev->features & NETIF_F_IP_CSUM)
13291 dev->features |= NETIF_F_TSO;
13292 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13293 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13294 dev->features |= NETIF_F_TSO6;
13295 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13296 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13297 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13298 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13299 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13300 dev->features |= NETIF_F_TSO_ECN;
13301 }
13302
13303
13304 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13305 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13306 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13307 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13308 tp->rx_pending = 63;
13309 }
13310
13311 err = tg3_get_device_address(tp);
13312 if (err) {
13313 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13314 "aborting.\n");
13315 goto err_out_fw;
13316 }
13317
13318 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13319 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13320 if (!tp->aperegs) {
13321 printk(KERN_ERR PFX "Cannot map APE registers, "
13322 "aborting.\n");
13323 err = -ENOMEM;
13324 goto err_out_fw;
13325 }
13326
13327 tg3_ape_lock_init(tp);
13328
13329 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13330 tg3_read_dash_ver(tp);
13331 }
13332
13333 /*
13334 * Reset chip in case UNDI or EFI driver did not shutdown
13335 * DMA self test will enable WDMAC and we'll see (spurious)
13336 * pending DMA on the PCI bus at that point.
13337 */
13338 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13339 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13340 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13341 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13342 }
13343
13344 err = tg3_test_dma(tp);
13345 if (err) {
13346 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13347 goto err_out_apeunmap;
13348 }
13349
13350 /* flow control autonegotiation is default behavior */
13351 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13352 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13353
13354 tg3_init_coal(tp);
13355
13356 pci_set_drvdata(pdev, dev);
13357
13358 err = register_netdev(dev);
13359 if (err) {
13360 printk(KERN_ERR PFX "Cannot register net device, "
13361 "aborting.\n");
13362 goto err_out_apeunmap;
13363 }
13364
13365 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13366 dev->name,
13367 tp->board_part_number,
13368 tp->pci_chip_rev_id,
13369 tg3_bus_string(tp, str),
13370 dev->dev_addr);
13371
13372 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13373 printk(KERN_INFO
13374 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13375 tp->dev->name,
13376 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13377 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13378 else
13379 printk(KERN_INFO
13380 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13381 tp->dev->name, tg3_phy_string(tp),
13382 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13383 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13384 "10/100/1000Base-T")),
13385 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13386
13387 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13388 dev->name,
13389 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13390 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13391 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13392 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13393 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13394 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13395 dev->name, tp->dma_rwctrl,
13396 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13397 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13398
13399 return 0;
13400
13401 err_out_apeunmap:
13402 if (tp->aperegs) {
13403 iounmap(tp->aperegs);
13404 tp->aperegs = NULL;
13405 }
13406
13407 err_out_fw:
13408 if (tp->fw)
13409 release_firmware(tp->fw);
13410
13411 err_out_iounmap:
13412 if (tp->regs) {
13413 iounmap(tp->regs);
13414 tp->regs = NULL;
13415 }
13416
13417 err_out_free_dev:
13418 free_netdev(dev);
13419
13420 err_out_free_res:
13421 pci_release_regions(pdev);
13422
13423 err_out_disable_pdev:
13424 pci_disable_device(pdev);
13425 pci_set_drvdata(pdev, NULL);
13426 return err;
13427 }
13428
13429 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13430 {
13431 struct net_device *dev = pci_get_drvdata(pdev);
13432
13433 if (dev) {
13434 struct tg3 *tp = netdev_priv(dev);
13435
13436 if (tp->fw)
13437 release_firmware(tp->fw);
13438
13439 flush_scheduled_work();
13440
13441 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13442 tg3_phy_fini(tp);
13443 tg3_mdio_fini(tp);
13444 }
13445
13446 unregister_netdev(dev);
13447 if (tp->aperegs) {
13448 iounmap(tp->aperegs);
13449 tp->aperegs = NULL;
13450 }
13451 if (tp->regs) {
13452 iounmap(tp->regs);
13453 tp->regs = NULL;
13454 }
13455 free_netdev(dev);
13456 pci_release_regions(pdev);
13457 pci_disable_device(pdev);
13458 pci_set_drvdata(pdev, NULL);
13459 }
13460 }
13461
13462 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13463 {
13464 struct net_device *dev = pci_get_drvdata(pdev);
13465 struct tg3 *tp = netdev_priv(dev);
13466 pci_power_t target_state;
13467 int err;
13468
13469 /* PCI register 4 needs to be saved whether netif_running() or not.
13470 * MSI address and data need to be saved if using MSI and
13471 * netif_running().
13472 */
13473 pci_save_state(pdev);
13474
13475 if (!netif_running(dev))
13476 return 0;
13477
13478 flush_scheduled_work();
13479 tg3_phy_stop(tp);
13480 tg3_netif_stop(tp);
13481
13482 del_timer_sync(&tp->timer);
13483
13484 tg3_full_lock(tp, 1);
13485 tg3_disable_ints(tp);
13486 tg3_full_unlock(tp);
13487
13488 netif_device_detach(dev);
13489
13490 tg3_full_lock(tp, 0);
13491 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13492 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13493 tg3_full_unlock(tp);
13494
13495 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13496
13497 err = tg3_set_power_state(tp, target_state);
13498 if (err) {
13499 int err2;
13500
13501 tg3_full_lock(tp, 0);
13502
13503 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13504 err2 = tg3_restart_hw(tp, 1);
13505 if (err2)
13506 goto out;
13507
13508 tp->timer.expires = jiffies + tp->timer_offset;
13509 add_timer(&tp->timer);
13510
13511 netif_device_attach(dev);
13512 tg3_netif_start(tp);
13513
13514 out:
13515 tg3_full_unlock(tp);
13516
13517 if (!err2)
13518 tg3_phy_start(tp);
13519 }
13520
13521 return err;
13522 }
13523
13524 static int tg3_resume(struct pci_dev *pdev)
13525 {
13526 struct net_device *dev = pci_get_drvdata(pdev);
13527 struct tg3 *tp = netdev_priv(dev);
13528 int err;
13529
13530 pci_restore_state(tp->pdev);
13531
13532 if (!netif_running(dev))
13533 return 0;
13534
13535 err = tg3_set_power_state(tp, PCI_D0);
13536 if (err)
13537 return err;
13538
13539 netif_device_attach(dev);
13540
13541 tg3_full_lock(tp, 0);
13542
13543 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13544 err = tg3_restart_hw(tp, 1);
13545 if (err)
13546 goto out;
13547
13548 tp->timer.expires = jiffies + tp->timer_offset;
13549 add_timer(&tp->timer);
13550
13551 tg3_netif_start(tp);
13552
13553 out:
13554 tg3_full_unlock(tp);
13555
13556 if (!err)
13557 tg3_phy_start(tp);
13558
13559 return err;
13560 }
13561
13562 static struct pci_driver tg3_driver = {
13563 .name = DRV_MODULE_NAME,
13564 .id_table = tg3_pci_tbl,
13565 .probe = tg3_init_one,
13566 .remove = __devexit_p(tg3_remove_one),
13567 .suspend = tg3_suspend,
13568 .resume = tg3_resume
13569 };
13570
13571 static int __init tg3_init(void)
13572 {
13573 return pci_register_driver(&tg3_driver);
13574 }
13575
13576 static void __exit tg3_cleanup(void)
13577 {
13578 pci_unregister_driver(&tg3_driver);
13579 }
13580
13581 module_init(tg3_init);
13582 module_exit(tg3_cleanup);
Linux with added FPC-III support