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net: smc91x: ACPI Enable lan91x adapters
[linux/fpc-iii.git] / drivers / mtd / nand / jz4740_nand.c
blob5551c36adbdf173b7df20629c36b065551f9d4ba
1 /*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC NAND controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16 #include <linux/ioport.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/nand.h>
24 #include <linux/mtd/partitions.h>
25
26 #include <linux/gpio.h>
27
28 #include <asm/mach-jz4740/gpio.h>
29 #include <asm/mach-jz4740/jz4740_nand.h>
30
31 #define JZ_REG_NAND_CTRL 0x50
32 #define JZ_REG_NAND_ECC_CTRL 0x100
33 #define JZ_REG_NAND_DATA 0x104
34 #define JZ_REG_NAND_PAR0 0x108
35 #define JZ_REG_NAND_PAR1 0x10C
36 #define JZ_REG_NAND_PAR2 0x110
37 #define JZ_REG_NAND_IRQ_STAT 0x114
38 #define JZ_REG_NAND_IRQ_CTRL 0x118
39 #define JZ_REG_NAND_ERR(x) (0x11C + ((x) << 2))
40
41 #define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
42 #define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
43 #define JZ_NAND_ECC_CTRL_RS BIT(2)
44 #define JZ_NAND_ECC_CTRL_RESET BIT(1)
45 #define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
46
47 #define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29))
48 #define JZ_NAND_STATUS_PAD_FINISH BIT(4)
49 #define JZ_NAND_STATUS_DEC_FINISH BIT(3)
50 #define JZ_NAND_STATUS_ENC_FINISH BIT(2)
51 #define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
52 #define JZ_NAND_STATUS_ERROR BIT(0)
53
54 #define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
55 #define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
56 #define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
57
58 #define JZ_NAND_MEM_CMD_OFFSET 0x08000
59 #define JZ_NAND_MEM_ADDR_OFFSET 0x10000
60
61 struct jz_nand {
62 struct nand_chip chip;
63 void __iomem *base;
64 struct resource *mem;
65
66 unsigned char banks[JZ_NAND_NUM_BANKS];
67 void __iomem *bank_base[JZ_NAND_NUM_BANKS];
68 struct resource *bank_mem[JZ_NAND_NUM_BANKS];
69
70 int selected_bank;
71
72 struct gpio_desc *busy_gpio;
73 bool is_reading;
74 };
75
76 static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
77 {
78 return container_of(mtd_to_nand(mtd), struct jz_nand, chip);
79 }
80
81 static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr)
82 {
83 struct jz_nand *nand = mtd_to_jz_nand(mtd);
84 struct nand_chip *chip = mtd_to_nand(mtd);
85 uint32_t ctrl;
86 int banknr;
87
88 ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
89 ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
90
91 if (chipnr == -1) {
92 banknr = -1;
93 } else {
94 banknr = nand->banks[chipnr] - 1;
95 chip->IO_ADDR_R = nand->bank_base[banknr];
96 chip->IO_ADDR_W = nand->bank_base[banknr];
97 }
98 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
99
100 nand->selected_bank = banknr;
101 }
102
103 static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
104 {
105 struct jz_nand *nand = mtd_to_jz_nand(mtd);
106 struct nand_chip *chip = mtd_to_nand(mtd);
107 uint32_t reg;
108 void __iomem *bank_base = nand->bank_base[nand->selected_bank];
109
110 BUG_ON(nand->selected_bank < 0);
111
112 if (ctrl & NAND_CTRL_CHANGE) {
113 BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
114 if (ctrl & NAND_ALE)
115 bank_base += JZ_NAND_MEM_ADDR_OFFSET;
116 else if (ctrl & NAND_CLE)
117 bank_base += JZ_NAND_MEM_CMD_OFFSET;
118 chip->IO_ADDR_W = bank_base;
119
120 reg = readl(nand->base + JZ_REG_NAND_CTRL);
121 if (ctrl & NAND_NCE)
122 reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
123 else
124 reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
125 writel(reg, nand->base + JZ_REG_NAND_CTRL);
126 }
127 if (dat != NAND_CMD_NONE)
128 writeb(dat, chip->IO_ADDR_W);
129 }
130
131 static int jz_nand_dev_ready(struct mtd_info *mtd)
132 {
133 struct jz_nand *nand = mtd_to_jz_nand(mtd);
134 return gpiod_get_value_cansleep(nand->busy_gpio);
135 }
136
137 static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
138 {
139 struct jz_nand *nand = mtd_to_jz_nand(mtd);
140 uint32_t reg;
141
142 writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
143 reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
144
145 reg |= JZ_NAND_ECC_CTRL_RESET;
146 reg |= JZ_NAND_ECC_CTRL_ENABLE;
147 reg |= JZ_NAND_ECC_CTRL_RS;
148
149 switch (mode) {
150 case NAND_ECC_READ:
151 reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
152 nand->is_reading = true;
153 break;
154 case NAND_ECC_WRITE:
155 reg |= JZ_NAND_ECC_CTRL_ENCODING;
156 nand->is_reading = false;
157 break;
158 default:
159 break;
160 }
161
162 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
163 }
164
165 static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat,
166 uint8_t *ecc_code)
167 {
168 struct jz_nand *nand = mtd_to_jz_nand(mtd);
169 uint32_t reg, status;
170 int i;
171 unsigned int timeout = 1000;
172 static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
173 0x8b, 0xff, 0xb7, 0x6f};
174
175 if (nand->is_reading)
176 return 0;
177
178 do {
179 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
180 } while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
181
182 if (timeout == 0)
183 return -1;
184
185 reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
186 reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
187 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
188
189 for (i = 0; i < 9; ++i)
190 ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
191
192 /* If the written data is completly 0xff, we also want to write 0xff as
193 * ecc, otherwise we will get in trouble when doing subpage writes. */
194 if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
195 memset(ecc_code, 0xff, 9);
196
197 return 0;
198 }
199
200 static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
201 {
202 int offset = index & 0x7;
203 uint16_t data;
204
205 index += (index >> 3);
206
207 data = dat[index];
208 data |= dat[index+1] << 8;
209
210 mask ^= (data >> offset) & 0x1ff;
211 data &= ~(0x1ff << offset);
212 data |= (mask << offset);
213
214 dat[index] = data & 0xff;
215 dat[index+1] = (data >> 8) & 0xff;
216 }
217
218 static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
219 uint8_t *read_ecc, uint8_t *calc_ecc)
220 {
221 struct jz_nand *nand = mtd_to_jz_nand(mtd);
222 int i, error_count, index;
223 uint32_t reg, status, error;
224 unsigned int timeout = 1000;
225
226 for (i = 0; i < 9; ++i)
227 writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
228
229 reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
230 reg |= JZ_NAND_ECC_CTRL_PAR_READY;
231 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
232
233 do {
234 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
235 } while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
236
237 if (timeout == 0)
238 return -ETIMEDOUT;
239
240 reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
241 reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
242 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
243
244 if (status & JZ_NAND_STATUS_ERROR) {
245 if (status & JZ_NAND_STATUS_UNCOR_ERROR)
246 return -EBADMSG;
247
248 error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
249
250 for (i = 0; i < error_count; ++i) {
251 error = readl(nand->base + JZ_REG_NAND_ERR(i));
252 index = ((error >> 16) & 0x1ff) - 1;
253 if (index >= 0 && index < 512)
254 jz_nand_correct_data(dat, index, error & 0x1ff);
255 }
256
257 return error_count;
258 }
259
260 return 0;
261 }
262
263 static int jz_nand_ioremap_resource(struct platform_device *pdev,
264 const char *name, struct resource **res, void *__iomem *base)
265 {
266 int ret;
267
268 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
269 if (!*res) {
270 dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
271 ret = -ENXIO;
272 goto err;
273 }
274
275 *res = request_mem_region((*res)->start, resource_size(*res),
276 pdev->name);
277 if (!*res) {
278 dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
279 ret = -EBUSY;
280 goto err;
281 }
282
283 *base = ioremap((*res)->start, resource_size(*res));
284 if (!*base) {
285 dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
286 ret = -EBUSY;
287 goto err_release_mem;
288 }
289
290 return 0;
291
292 err_release_mem:
293 release_mem_region((*res)->start, resource_size(*res));
294 err:
295 *res = NULL;
296 *base = NULL;
297 return ret;
298 }
299
300 static inline void jz_nand_iounmap_resource(struct resource *res,
301 void __iomem *base)
302 {
303 iounmap(base);
304 release_mem_region(res->start, resource_size(res));
305 }
306
307 static int jz_nand_detect_bank(struct platform_device *pdev,
308 struct jz_nand *nand, unsigned char bank,
309 size_t chipnr, uint8_t *nand_maf_id,
310 uint8_t *nand_dev_id)
311 {
312 int ret;
313 int gpio;
314 char gpio_name[9];
315 char res_name[6];
316 uint32_t ctrl;
317 struct nand_chip *chip = &nand->chip;
318 struct mtd_info *mtd = nand_to_mtd(chip);
319
320 /* Request GPIO port. */
321 gpio = JZ_GPIO_MEM_CS0 + bank - 1;
322 sprintf(gpio_name, "NAND CS%d", bank);
323 ret = gpio_request(gpio, gpio_name);
324 if (ret) {
325 dev_warn(&pdev->dev,
326 "Failed to request %s gpio %d: %d\n",
327 gpio_name, gpio, ret);
328 goto notfound_gpio;
329 }
330
331 /* Request I/O resource. */
332 sprintf(res_name, "bank%d", bank);
333 ret = jz_nand_ioremap_resource(pdev, res_name,
334 &nand->bank_mem[bank - 1],
335 &nand->bank_base[bank - 1]);
336 if (ret)
337 goto notfound_resource;
338
339 /* Enable chip in bank. */
340 jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
341 ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
342 ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
343 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
344
345 if (chipnr == 0) {
346 /* Detect first chip. */
347 ret = nand_scan_ident(mtd, 1, NULL);
348 if (ret)
349 goto notfound_id;
350
351 /* Retrieve the IDs from the first chip. */
352 chip->select_chip(mtd, 0);
353 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
354 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
355 *nand_maf_id = chip->read_byte(mtd);
356 *nand_dev_id = chip->read_byte(mtd);
357 } else {
358 /* Detect additional chip. */
359 chip->select_chip(mtd, chipnr);
360 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
361 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
362 if (*nand_maf_id != chip->read_byte(mtd)
363 || *nand_dev_id != chip->read_byte(mtd)) {
364 ret = -ENODEV;
365 goto notfound_id;
366 }
367
368 /* Update size of the MTD. */
369 chip->numchips++;
370 mtd->size += chip->chipsize;
371 }
372
373 dev_info(&pdev->dev, "Found chip %i on bank %i\n", chipnr, bank);
374 return 0;
375
376 notfound_id:
377 dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
378 ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
379 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
380 jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
381 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
382 nand->bank_base[bank - 1]);
383 notfound_resource:
384 gpio_free(gpio);
385 notfound_gpio:
386 return ret;
387 }
388
389 static int jz_nand_probe(struct platform_device *pdev)
390 {
391 int ret;
392 struct jz_nand *nand;
393 struct nand_chip *chip;
394 struct mtd_info *mtd;
395 struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
396 size_t chipnr, bank_idx;
397 uint8_t nand_maf_id = 0, nand_dev_id = 0;
398
399 nand = kzalloc(sizeof(*nand), GFP_KERNEL);
400 if (!nand)
401 return -ENOMEM;
402
403 ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
404 if (ret)
405 goto err_free;
406
407 nand->busy_gpio = devm_gpiod_get_optional(&pdev->dev, "busy", GPIOD_IN);
408 if (IS_ERR(nand->busy_gpio)) {
409 ret = PTR_ERR(nand->busy_gpio);
410 dev_err(&pdev->dev, "Failed to request busy gpio %d\n",
411 ret);
412 goto err_iounmap_mmio;
413 }
414
415 chip = &nand->chip;
416 mtd = nand_to_mtd(chip);
417 mtd->dev.parent = &pdev->dev;
418 mtd->name = "jz4740-nand";
419
420 chip->ecc.hwctl = jz_nand_hwctl;
421 chip->ecc.calculate = jz_nand_calculate_ecc_rs;
422 chip->ecc.correct = jz_nand_correct_ecc_rs;
423 chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
424 chip->ecc.size = 512;
425 chip->ecc.bytes = 9;
426 chip->ecc.strength = 4;
427 chip->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
428
429 chip->chip_delay = 50;
430 chip->cmd_ctrl = jz_nand_cmd_ctrl;
431 chip->select_chip = jz_nand_select_chip;
432
433 if (nand->busy_gpio)
434 chip->dev_ready = jz_nand_dev_ready;
435
436 platform_set_drvdata(pdev, nand);
437
438 /* We are going to autodetect NAND chips in the banks specified in the
439 * platform data. Although nand_scan_ident() can detect multiple chips,
440 * it requires those chips to be numbered consecuitively, which is not
441 * always the case for external memory banks. And a fixed chip-to-bank
442 * mapping is not practical either, since for example Dingoo units
443 * produced at different times have NAND chips in different banks.
444 */
445 chipnr = 0;
446 for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
447 unsigned char bank;
448
449 /* If there is no platform data, look for NAND in bank 1,
450 * which is the most likely bank since it is the only one
451 * that can be booted from.
452 */
453 bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
454 if (bank == 0)
455 break;
456 if (bank > JZ_NAND_NUM_BANKS) {
457 dev_warn(&pdev->dev,
458 "Skipping non-existing bank: %d\n", bank);
459 continue;
460 }
461 /* The detection routine will directly or indirectly call
462 * jz_nand_select_chip(), so nand->banks has to contain the
463 * bank we're checking.
464 */
465 nand->banks[chipnr] = bank;
466 if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
467 &nand_maf_id, &nand_dev_id) == 0)
468 chipnr++;
469 else
470 nand->banks[chipnr] = 0;
471 }
472 if (chipnr == 0) {
473 dev_err(&pdev->dev, "No NAND chips found\n");
474 goto err_iounmap_mmio;
475 }
476
477 if (pdata && pdata->ident_callback) {
478 pdata->ident_callback(pdev, mtd, &pdata->partitions,
479 &pdata->num_partitions);
480 }
481
482 ret = nand_scan_tail(mtd);
483 if (ret) {
484 dev_err(&pdev->dev, "Failed to scan NAND\n");
485 goto err_unclaim_banks;
486 }
487
488 ret = mtd_device_parse_register(mtd, NULL, NULL,
489 pdata ? pdata->partitions : NULL,
490 pdata ? pdata->num_partitions : 0);
491
492 if (ret) {
493 dev_err(&pdev->dev, "Failed to add mtd device\n");
494 goto err_nand_release;
495 }
496
497 dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
498
499 return 0;
500
501 err_nand_release:
502 nand_release(mtd);
503 err_unclaim_banks:
504 while (chipnr--) {
505 unsigned char bank = nand->banks[chipnr];
506 gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
507 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
508 nand->bank_base[bank - 1]);
509 }
510 writel(0, nand->base + JZ_REG_NAND_CTRL);
511 err_iounmap_mmio:
512 jz_nand_iounmap_resource(nand->mem, nand->base);
513 err_free:
514 kfree(nand);
515 return ret;
516 }
517
518 static int jz_nand_remove(struct platform_device *pdev)
519 {
520 struct jz_nand *nand = platform_get_drvdata(pdev);
521 size_t i;
522
523 nand_release(nand_to_mtd(&nand->chip));
524
525 /* Deassert and disable all chips */
526 writel(0, nand->base + JZ_REG_NAND_CTRL);
527
528 for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
529 unsigned char bank = nand->banks[i];
530 if (bank != 0) {
531 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
532 nand->bank_base[bank - 1]);
533 gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
534 }
535 }
536
537 jz_nand_iounmap_resource(nand->mem, nand->base);
538
539 kfree(nand);
540
541 return 0;
542 }
543
544 static struct platform_driver jz_nand_driver = {
545 .probe = jz_nand_probe,
546 .remove = jz_nand_remove,
547 .driver = {
548 .name = "jz4740-nand",
549 },
550 };
551
552 module_platform_driver(jz_nand_driver);
553
554 MODULE_LICENSE("GPL");
555 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
556 MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
557 MODULE_ALIAS("platform:jz4740-nand");
Linux with added FPC-III support