| blob | 3f047afb982c8d17ad9e9c41e04b35d1fc02cffe |
1 # SPDX-License-Identifier: GPL-2.0-only
2 config ARM64
3 def_bool y
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE
22 select ARCH_HAS_KCOV
23 select ARCH_HAS_KEEPINITRD
24 select ARCH_HAS_MEMBARRIER_SYNC_CORE
25 select ARCH_HAS_PTE_DEVMAP
26 select ARCH_HAS_PTE_SPECIAL
27 select ARCH_HAS_SETUP_DMA_OPS
28 select ARCH_HAS_SET_DIRECT_MAP
29 select ARCH_HAS_SET_MEMORY
30 select ARCH_HAS_STRICT_KERNEL_RWX
31 select ARCH_HAS_STRICT_MODULE_RWX
32 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
33 select ARCH_HAS_SYNC_DMA_FOR_CPU
34 select ARCH_HAS_SYSCALL_WRAPPER
35 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
36 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
37 select ARCH_HAVE_NMI_SAFE_CMPXCHG
38 select ARCH_INLINE_READ_LOCK if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
55 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
64 select ARCH_KEEP_MEMBLOCK
65 select ARCH_USE_CMPXCHG_LOCKREF
66 select ARCH_USE_QUEUED_RWLOCKS
67 select ARCH_USE_QUEUED_SPINLOCKS
68 select ARCH_SUPPORTS_MEMORY_FAILURE
69 select ARCH_SUPPORTS_ATOMIC_RMW
70 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
71 select ARCH_SUPPORTS_NUMA_BALANCING
72 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
73 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
74 select ARCH_WANT_FRAME_POINTERS
75 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
76 select ARCH_HAS_UBSAN_SANITIZE_ALL
77 select ARM_AMBA
78 select ARM_ARCH_TIMER
79 select ARM_GIC
80 select AUDIT_ARCH_COMPAT_GENERIC
81 select ARM_GIC_V2M if PCI
82 select ARM_GIC_V3
83 select ARM_GIC_V3_ITS if PCI
84 select ARM_PSCI_FW
85 select BUILDTIME_EXTABLE_SORT
86 select CLONE_BACKWARDS
87 select COMMON_CLK
88 select CPU_PM if (SUSPEND || CPU_IDLE)
89 select CRC32
90 select DCACHE_WORD_ACCESS
91 select DMA_DIRECT_REMAP
92 select EDAC_SUPPORT
93 select FRAME_POINTER
94 select GENERIC_ALLOCATOR
95 select GENERIC_ARCH_TOPOLOGY
96 select GENERIC_CLOCKEVENTS
97 select GENERIC_CLOCKEVENTS_BROADCAST
98 select GENERIC_CPU_AUTOPROBE
99 select GENERIC_CPU_VULNERABILITIES
100 select GENERIC_EARLY_IOREMAP
101 select GENERIC_IDLE_POLL_SETUP
102 select GENERIC_IRQ_MULTI_HANDLER
103 select GENERIC_IRQ_PROBE
104 select GENERIC_IRQ_SHOW
105 select GENERIC_IRQ_SHOW_LEVEL
106 select GENERIC_PCI_IOMAP
107 select GENERIC_SCHED_CLOCK
108 select GENERIC_SMP_IDLE_THREAD
109 select GENERIC_STRNCPY_FROM_USER
110 select GENERIC_STRNLEN_USER
111 select GENERIC_TIME_VSYSCALL
112 select GENERIC_GETTIMEOFDAY
113 select HANDLE_DOMAIN_IRQ
114 select HARDIRQS_SW_RESEND
115 select HAVE_PCI
116 select HAVE_ACPI_APEI if (ACPI && EFI)
117 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
118 select HAVE_ARCH_AUDITSYSCALL
119 select HAVE_ARCH_BITREVERSE
120 select HAVE_ARCH_HUGE_VMAP
121 select HAVE_ARCH_JUMP_LABEL
122 select HAVE_ARCH_JUMP_LABEL_RELATIVE
123 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
124 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
125 select HAVE_ARCH_KGDB
126 select HAVE_ARCH_MMAP_RND_BITS
127 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
128 select HAVE_ARCH_PREL32_RELOCATIONS
129 select HAVE_ARCH_SECCOMP_FILTER
130 select HAVE_ARCH_STACKLEAK
131 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
132 select HAVE_ARCH_TRACEHOOK
133 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
134 select HAVE_ARCH_VMAP_STACK
135 select HAVE_ARM_SMCCC
136 select HAVE_ASM_MODVERSIONS
137 select HAVE_EBPF_JIT
138 select HAVE_C_RECORDMCOUNT
139 select HAVE_CMPXCHG_DOUBLE
140 select HAVE_CMPXCHG_LOCAL
141 select HAVE_CONTEXT_TRACKING
142 select HAVE_DEBUG_BUGVERBOSE
143 select HAVE_DEBUG_KMEMLEAK
144 select HAVE_DMA_CONTIGUOUS
145 select HAVE_DYNAMIC_FTRACE
146 select HAVE_EFFICIENT_UNALIGNED_ACCESS
147 select HAVE_FAST_GUP
148 select HAVE_FTRACE_MCOUNT_RECORD
149 select HAVE_FUNCTION_TRACER
150 select HAVE_FUNCTION_ERROR_INJECTION
151 select HAVE_FUNCTION_GRAPH_TRACER
152 select HAVE_GCC_PLUGINS
153 select HAVE_HW_BREAKPOINT if PERF_EVENTS
154 select HAVE_IRQ_TIME_ACCOUNTING
155 select HAVE_MEMBLOCK_NODE_MAP if NUMA
156 select HAVE_NMI
157 select HAVE_PATA_PLATFORM
158 select HAVE_PERF_EVENTS
159 select HAVE_PERF_REGS
160 select HAVE_PERF_USER_STACK_DUMP
161 select HAVE_REGS_AND_STACK_ACCESS_API
162 select HAVE_FUNCTION_ARG_ACCESS_API
163 select HAVE_RCU_TABLE_FREE
164 select HAVE_RSEQ
165 select HAVE_STACKPROTECTOR
166 select HAVE_SYSCALL_TRACEPOINTS
167 select HAVE_KPROBES
168 select HAVE_KRETPROBES
169 select HAVE_GENERIC_VDSO
170 select IOMMU_DMA if IOMMU_SUPPORT
171 select IRQ_DOMAIN
172 select IRQ_FORCED_THREADING
173 select MODULES_USE_ELF_RELA
174 select NEED_DMA_MAP_STATE
175 select NEED_SG_DMA_LENGTH
176 select OF
177 select OF_EARLY_FLATTREE
178 select PCI_DOMAINS_GENERIC if PCI
179 select PCI_ECAM if (ACPI && PCI)
180 select PCI_SYSCALL if PCI
181 select POWER_RESET
182 select POWER_SUPPLY
183 select REFCOUNT_FULL
184 select SPARSE_IRQ
185 select SWIOTLB
186 select SYSCTL_EXCEPTION_TRACE
187 select THREAD_INFO_IN_TASK
188 help
189 ARM 64-bit (AArch64) Linux support.
191 config 64BIT
192 def_bool y
194 config MMU
195 def_bool y
197 config ARM64_PAGE_SHIFT
198 int
199 default 16 if ARM64_64K_PAGES
200 default 14 if ARM64_16K_PAGES
201 default 12
203 config ARM64_CONT_SHIFT
204 int
205 default 5 if ARM64_64K_PAGES
206 default 7 if ARM64_16K_PAGES
207 default 4
209 config ARCH_MMAP_RND_BITS_MIN
210 default 14 if ARM64_64K_PAGES
211 default 16 if ARM64_16K_PAGES
212 default 18
214 # max bits determined by the following formula:
215 # VA_BITS - PAGE_SHIFT - 3
216 config ARCH_MMAP_RND_BITS_MAX
217 default 19 if ARM64_VA_BITS=36
218 default 24 if ARM64_VA_BITS=39
219 default 27 if ARM64_VA_BITS=42
220 default 30 if ARM64_VA_BITS=47
221 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
222 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
223 default 33 if ARM64_VA_BITS=48
224 default 14 if ARM64_64K_PAGES
225 default 16 if ARM64_16K_PAGES
226 default 18
228 config ARCH_MMAP_RND_COMPAT_BITS_MIN
229 default 7 if ARM64_64K_PAGES
230 default 9 if ARM64_16K_PAGES
231 default 11
233 config ARCH_MMAP_RND_COMPAT_BITS_MAX
234 default 16
236 config NO_IOPORT_MAP
237 def_bool y if !PCI
239 config STACKTRACE_SUPPORT
240 def_bool y
242 config ILLEGAL_POINTER_VALUE
243 hex
244 default 0xdead000000000000
246 config LOCKDEP_SUPPORT
247 def_bool y
249 config TRACE_IRQFLAGS_SUPPORT
250 def_bool y
252 config GENERIC_BUG
253 def_bool y
254 depends on BUG
256 config GENERIC_BUG_RELATIVE_POINTERS
257 def_bool y
258 depends on GENERIC_BUG
260 config GENERIC_HWEIGHT
261 def_bool y
263 config GENERIC_CSUM
264 def_bool y
266 config GENERIC_CALIBRATE_DELAY
267 def_bool y
269 config ZONE_DMA32
270 bool "Support DMA32 zone" if EXPERT
271 default y
273 config ARCH_ENABLE_MEMORY_HOTPLUG
274 def_bool y
276 config SMP
277 def_bool y
279 config KERNEL_MODE_NEON
280 def_bool y
282 config FIX_EARLYCON_MEM
283 def_bool y
285 config PGTABLE_LEVELS
286 int
287 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
288 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
289 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
290 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
291 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
292 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
294 config ARCH_SUPPORTS_UPROBES
295 def_bool y
297 config ARCH_PROC_KCORE_TEXT
298 def_bool y
300 config KASAN_SHADOW_OFFSET
301 hex
302 depends on KASAN
303 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
304 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
305 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
306 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
307 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
308 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
309 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
310 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
311 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
312 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
313 default 0xffffffffffffffff
315 source "arch/arm64/Kconfig.platforms"
317 menu "Kernel Features"
319 menu "ARM errata workarounds via the alternatives framework"
321 config ARM64_WORKAROUND_CLEAN_CACHE
322 bool
324 config ARM64_ERRATUM_826319
325 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
326 default y
327 select ARM64_WORKAROUND_CLEAN_CACHE
328 help
329 This option adds an alternative code sequence to work around ARM
330 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
331 AXI master interface and an L2 cache.
333 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
334 and is unable to accept a certain write via this interface, it will
335 not progress on read data presented on the read data channel and the
336 system can deadlock.
338 The workaround promotes data cache clean instructions to
339 data cache clean-and-invalidate.
340 Please note that this does not necessarily enable the workaround,
341 as it depends on the alternative framework, which will only patch
342 the kernel if an affected CPU is detected.
344 If unsure, say Y.
346 config ARM64_ERRATUM_827319
347 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
348 default y
349 select ARM64_WORKAROUND_CLEAN_CACHE
350 help
351 This option adds an alternative code sequence to work around ARM
352 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
353 master interface and an L2 cache.
355 Under certain conditions this erratum can cause a clean line eviction
356 to occur at the same time as another transaction to the same address
357 on the AMBA 5 CHI interface, which can cause data corruption if the
358 interconnect reorders the two transactions.
360 The workaround promotes data cache clean instructions to
361 data cache clean-and-invalidate.
362 Please note that this does not necessarily enable the workaround,
363 as it depends on the alternative framework, which will only patch
364 the kernel if an affected CPU is detected.
366 If unsure, say Y.
368 config ARM64_ERRATUM_824069
369 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
370 default y
371 select ARM64_WORKAROUND_CLEAN_CACHE
372 help
373 This option adds an alternative code sequence to work around ARM
374 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
375 to a coherent interconnect.
377 If a Cortex-A53 processor is executing a store or prefetch for
378 write instruction at the same time as a processor in another
379 cluster is executing a cache maintenance operation to the same
380 address, then this erratum might cause a clean cache line to be
381 incorrectly marked as dirty.
383 The workaround promotes data cache clean instructions to
384 data cache clean-and-invalidate.
385 Please note that this option does not necessarily enable the
386 workaround, as it depends on the alternative framework, which will
387 only patch the kernel if an affected CPU is detected.
389 If unsure, say Y.
391 config ARM64_ERRATUM_819472
392 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
393 default y
394 select ARM64_WORKAROUND_CLEAN_CACHE
395 help
396 This option adds an alternative code sequence to work around ARM
397 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
398 present when it is connected to a coherent interconnect.
400 If the processor is executing a load and store exclusive sequence at
401 the same time as a processor in another cluster is executing a cache
402 maintenance operation to the same address, then this erratum might
403 cause data corruption.
405 The workaround promotes data cache clean instructions to
406 data cache clean-and-invalidate.
407 Please note that this does not necessarily enable the workaround,
408 as it depends on the alternative framework, which will only patch
409 the kernel if an affected CPU is detected.
411 If unsure, say Y.
413 config ARM64_ERRATUM_832075
414 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
415 default y
416 help
417 This option adds an alternative code sequence to work around ARM
418 erratum 832075 on Cortex-A57 parts up to r1p2.
420 Affected Cortex-A57 parts might deadlock when exclusive load/store
421 instructions to Write-Back memory are mixed with Device loads.
423 The workaround is to promote device loads to use Load-Acquire
424 semantics.
425 Please note that this does not necessarily enable the workaround,
426 as it depends on the alternative framework, which will only patch
427 the kernel if an affected CPU is detected.
429 If unsure, say Y.
431 config ARM64_ERRATUM_834220
432 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
433 depends on KVM
434 default y
435 help
436 This option adds an alternative code sequence to work around ARM
437 erratum 834220 on Cortex-A57 parts up to r1p2.
439 Affected Cortex-A57 parts might report a Stage 2 translation
440 fault as the result of a Stage 1 fault for load crossing a
441 page boundary when there is a permission or device memory
442 alignment fault at Stage 1 and a translation fault at Stage 2.
444 The workaround is to verify that the Stage 1 translation
445 doesn't generate a fault before handling the Stage 2 fault.
446 Please note that this does not necessarily enable the workaround,
447 as it depends on the alternative framework, which will only patch
448 the kernel if an affected CPU is detected.
450 If unsure, say Y.
452 config ARM64_ERRATUM_845719
453 bool "Cortex-A53: 845719: a load might read incorrect data"
454 depends on COMPAT
455 default y
456 help
457 This option adds an alternative code sequence to work around ARM
458 erratum 845719 on Cortex-A53 parts up to r0p4.
460 When running a compat (AArch32) userspace on an affected Cortex-A53
461 part, a load at EL0 from a virtual address that matches the bottom 32
462 bits of the virtual address used by a recent load at (AArch64) EL1
463 might return incorrect data.
465 The workaround is to write the contextidr_el1 register on exception
466 return to a 32-bit task.
467 Please note that this does not necessarily enable the workaround,
468 as it depends on the alternative framework, which will only patch
469 the kernel if an affected CPU is detected.
471 If unsure, say Y.
473 config ARM64_ERRATUM_843419
474 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
475 default y
476 select ARM64_MODULE_PLTS if MODULES
477 help
478 This option links the kernel with '--fix-cortex-a53-843419' and
479 enables PLT support to replace certain ADRP instructions, which can
480 cause subsequent memory accesses to use an incorrect address on
481 Cortex-A53 parts up to r0p4.
483 If unsure, say Y.
485 config ARM64_ERRATUM_1024718
486 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
487 default y
488 help
489 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
491 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
492 update of the hardware dirty bit when the DBM/AP bits are updated
493 without a break-before-make. The workaround is to disable the usage
494 of hardware DBM locally on the affected cores. CPUs not affected by
495 this erratum will continue to use the feature.
497 If unsure, say Y.
499 config ARM64_ERRATUM_1418040
500 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
501 default y
502 depends on COMPAT
503 help
504 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
505 errata 1188873 and 1418040.
507 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
508 cause register corruption when accessing the timer registers
509 from AArch32 userspace.
511 If unsure, say Y.
513 config ARM64_ERRATUM_1165522
514 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
515 default y
516 help
517 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
519 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
520 corrupted TLBs by speculating an AT instruction during a guest
521 context switch.
523 If unsure, say Y.
525 config ARM64_ERRATUM_1286807
526 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
527 default y
528 select ARM64_WORKAROUND_REPEAT_TLBI
529 help
530 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
532 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
533 address for a cacheable mapping of a location is being
534 accessed by a core while another core is remapping the virtual
535 address to a new physical page using the recommended
536 break-before-make sequence, then under very rare circumstances
537 TLBI+DSB completes before a read using the translation being
538 invalidated has been observed by other observers. The
539 workaround repeats the TLBI+DSB operation.
541 If unsure, say Y.
543 config ARM64_ERRATUM_1463225
544 bool "Cortex-A76: Software Step might prevent interrupt recognition"
545 default y
546 help
547 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
549 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
550 of a system call instruction (SVC) can prevent recognition of
551 subsequent interrupts when software stepping is disabled in the
552 exception handler of the system call and either kernel debugging
553 is enabled or VHE is in use.
555 Work around the erratum by triggering a dummy step exception
556 when handling a system call from a task that is being stepped
557 in a VHE configuration of the kernel.
559 If unsure, say Y.
561 config CAVIUM_ERRATUM_22375
562 bool "Cavium erratum 22375, 24313"
563 default y
564 help
565 Enable workaround for errata 22375 and 24313.
567 This implements two gicv3-its errata workarounds for ThunderX. Both
568 with a small impact affecting only ITS table allocation.
570 erratum 22375: only alloc 8MB table size
571 erratum 24313: ignore memory access type
573 The fixes are in ITS initialization and basically ignore memory access
574 type and table size provided by the TYPER and BASER registers.
576 If unsure, say Y.
578 config CAVIUM_ERRATUM_23144
579 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
580 depends on NUMA
581 default y
582 help
583 ITS SYNC command hang for cross node io and collections/cpu mapping.
585 If unsure, say Y.
587 config CAVIUM_ERRATUM_23154
588 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
589 default y
590 help
591 The gicv3 of ThunderX requires a modified version for
592 reading the IAR status to ensure data synchronization
593 (access to icc_iar1_el1 is not sync'ed before and after).
595 If unsure, say Y.
597 config CAVIUM_ERRATUM_27456
598 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
599 default y
600 help
601 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
602 instructions may cause the icache to become corrupted if it
603 contains data for a non-current ASID. The fix is to
604 invalidate the icache when changing the mm context.
606 If unsure, say Y.
608 config CAVIUM_ERRATUM_30115
609 bool "Cavium erratum 30115: Guest may disable interrupts in host"
610 default y
611 help
612 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
613 1.2, and T83 Pass 1.0, KVM guest execution may disable
614 interrupts in host. Trapping both GICv3 group-0 and group-1
615 accesses sidesteps the issue.
617 If unsure, say Y.
619 config CAVIUM_TX2_ERRATUM_219
620 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
621 default y
622 help
623 On Cavium ThunderX2, a load, store or prefetch instruction between a
624 TTBR update and the corresponding context synchronizing operation can
625 cause a spurious Data Abort to be delivered to any hardware thread in
626 the CPU core.
628 Work around the issue by avoiding the problematic code sequence and
629 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
630 trap handler performs the corresponding register access, skips the
631 instruction and ensures context synchronization by virtue of the
632 exception return.
634 If unsure, say Y.
636 config QCOM_FALKOR_ERRATUM_1003
637 bool "Falkor E1003: Incorrect translation due to ASID change"
638 default y
639 help
640 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
641 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
642 in TTBR1_EL1, this situation only occurs in the entry trampoline and
643 then only for entries in the walk cache, since the leaf translation
644 is unchanged. Work around the erratum by invalidating the walk cache
645 entries for the trampoline before entering the kernel proper.
647 config ARM64_WORKAROUND_REPEAT_TLBI
648 bool
650 config QCOM_FALKOR_ERRATUM_1009
651 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
652 default y
653 select ARM64_WORKAROUND_REPEAT_TLBI
654 help
655 On Falkor v1, the CPU may prematurely complete a DSB following a
656 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
657 one more time to fix the issue.
659 If unsure, say Y.
661 config QCOM_QDF2400_ERRATUM_0065
662 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
663 default y
664 help
665 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
666 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
667 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
669 If unsure, say Y.
671 config SOCIONEXT_SYNQUACER_PREITS
672 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
673 default y
674 help
675 Socionext Synquacer SoCs implement a separate h/w block to generate
676 MSI doorbell writes with non-zero values for the device ID.
678 If unsure, say Y.
680 config HISILICON_ERRATUM_161600802
681 bool "Hip07 161600802: Erroneous redistributor VLPI base"
682 default y
683 help
684 The HiSilicon Hip07 SoC uses the wrong redistributor base
685 when issued ITS commands such as VMOVP and VMAPP, and requires
686 a 128kB offset to be applied to the target address in this commands.
688 If unsure, say Y.
690 config QCOM_FALKOR_ERRATUM_E1041
691 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
692 default y
693 help
694 Falkor CPU may speculatively fetch instructions from an improper
695 memory location when MMU translation is changed from SCTLR_ELn[M]=1
696 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
698 If unsure, say Y.
700 config FUJITSU_ERRATUM_010001
701 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
702 default y
703 help
704 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
705 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
706 accesses may cause undefined fault (Data abort, DFSC=0b111111).
707 This fault occurs under a specific hardware condition when a
708 load/store instruction performs an address translation using:
709 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
710 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
711 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
712 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
714 The workaround is to ensure these bits are clear in TCR_ELx.
715 The workaround only affects the Fujitsu-A64FX.
717 If unsure, say Y.
719 endmenu
722 choice
723 prompt "Page size"
724 default ARM64_4K_PAGES
725 help
726 Page size (translation granule) configuration.
728 config ARM64_4K_PAGES
729 bool "4KB"
730 help
731 This feature enables 4KB pages support.
733 config ARM64_16K_PAGES
734 bool "16KB"
735 help
736 The system will use 16KB pages support. AArch32 emulation
737 requires applications compiled with 16K (or a multiple of 16K)
738 aligned segments.
740 config ARM64_64K_PAGES
741 bool "64KB"
742 help
743 This feature enables 64KB pages support (4KB by default)
744 allowing only two levels of page tables and faster TLB
745 look-up. AArch32 emulation requires applications compiled
746 with 64K aligned segments.
748 endchoice
750 choice
751 prompt "Virtual address space size"
752 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
753 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
754 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
755 help
756 Allows choosing one of multiple possible virtual address
757 space sizes. The level of translation table is determined by
758 a combination of page size and virtual address space size.
760 config ARM64_VA_BITS_36
761 bool "36-bit" if EXPERT
762 depends on ARM64_16K_PAGES
764 config ARM64_VA_BITS_39
765 bool "39-bit"
766 depends on ARM64_4K_PAGES
768 config ARM64_VA_BITS_42
769 bool "42-bit"
770 depends on ARM64_64K_PAGES
772 config ARM64_VA_BITS_47
773 bool "47-bit"
774 depends on ARM64_16K_PAGES
776 config ARM64_VA_BITS_48
777 bool "48-bit"
779 config ARM64_VA_BITS_52
780 bool "52-bit"
781 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
782 help
783 Enable 52-bit virtual addressing for userspace when explicitly
784 requested via a hint to mmap(). The kernel will also use 52-bit
785 virtual addresses for its own mappings (provided HW support for
786 this feature is available, otherwise it reverts to 48-bit).
788 NOTE: Enabling 52-bit virtual addressing in conjunction with
789 ARMv8.3 Pointer Authentication will result in the PAC being
790 reduced from 7 bits to 3 bits, which may have a significant
791 impact on its susceptibility to brute-force attacks.
793 If unsure, select 48-bit virtual addressing instead.
795 endchoice
797 config ARM64_FORCE_52BIT
798 bool "Force 52-bit virtual addresses for userspace"
799 depends on ARM64_VA_BITS_52 && EXPERT
800 help
801 For systems with 52-bit userspace VAs enabled, the kernel will attempt
802 to maintain compatibility with older software by providing 48-bit VAs
803 unless a hint is supplied to mmap.
805 This configuration option disables the 48-bit compatibility logic, and
806 forces all userspace addresses to be 52-bit on HW that supports it. One
807 should only enable this configuration option for stress testing userspace
808 memory management code. If unsure say N here.
810 config ARM64_VA_BITS
811 int
812 default 36 if ARM64_VA_BITS_36
813 default 39 if ARM64_VA_BITS_39
814 default 42 if ARM64_VA_BITS_42
815 default 47 if ARM64_VA_BITS_47
816 default 48 if ARM64_VA_BITS_48
817 default 52 if ARM64_VA_BITS_52
819 choice
820 prompt "Physical address space size"
821 default ARM64_PA_BITS_48
822 help
823 Choose the maximum physical address range that the kernel will
824 support.
826 config ARM64_PA_BITS_48
827 bool "48-bit"
829 config ARM64_PA_BITS_52
830 bool "52-bit (ARMv8.2)"
831 depends on ARM64_64K_PAGES
832 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
833 help
834 Enable support for a 52-bit physical address space, introduced as
835 part of the ARMv8.2-LPA extension.
837 With this enabled, the kernel will also continue to work on CPUs that
838 do not support ARMv8.2-LPA, but with some added memory overhead (and
839 minor performance overhead).
841 endchoice
843 config ARM64_PA_BITS
844 int
845 default 48 if ARM64_PA_BITS_48
846 default 52 if ARM64_PA_BITS_52
848 config CPU_BIG_ENDIAN
849 bool "Build big-endian kernel"
850 help
851 Say Y if you plan on running a kernel in big-endian mode.
853 config SCHED_MC
854 bool "Multi-core scheduler support"
855 help
856 Multi-core scheduler support improves the CPU scheduler's decision
857 making when dealing with multi-core CPU chips at a cost of slightly
858 increased overhead in some places. If unsure say N here.
860 config SCHED_SMT
861 bool "SMT scheduler support"
862 help
863 Improves the CPU scheduler's decision making when dealing with
864 MultiThreading at a cost of slightly increased overhead in some
865 places. If unsure say N here.
867 config NR_CPUS
868 int "Maximum number of CPUs (2-4096)"
869 range 2 4096
870 default "256"
872 config HOTPLUG_CPU
873 bool "Support for hot-pluggable CPUs"
874 select GENERIC_IRQ_MIGRATION
875 help
876 Say Y here to experiment with turning CPUs off and on. CPUs
877 can be controlled through /sys/devices/system/cpu.
879 # Common NUMA Features
880 config NUMA
881 bool "Numa Memory Allocation and Scheduler Support"
882 select ACPI_NUMA if ACPI
883 select OF_NUMA
884 help
885 Enable NUMA (Non Uniform Memory Access) support.
887 The kernel will try to allocate memory used by a CPU on the
888 local memory of the CPU and add some more
889 NUMA awareness to the kernel.
891 config NODES_SHIFT
892 int "Maximum NUMA Nodes (as a power of 2)"
893 range 1 10
894 default "2"
895 depends on NEED_MULTIPLE_NODES
896 help
897 Specify the maximum number of NUMA Nodes available on the target
898 system. Increases memory reserved to accommodate various tables.
900 config USE_PERCPU_NUMA_NODE_ID
901 def_bool y
902 depends on NUMA
904 config HAVE_SETUP_PER_CPU_AREA
905 def_bool y
906 depends on NUMA
908 config NEED_PER_CPU_EMBED_FIRST_CHUNK
909 def_bool y
910 depends on NUMA
912 config HOLES_IN_ZONE
913 def_bool y
915 source "kernel/Kconfig.hz"
917 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
918 def_bool y
920 config ARCH_SPARSEMEM_ENABLE
921 def_bool y
922 select SPARSEMEM_VMEMMAP_ENABLE
924 config ARCH_SPARSEMEM_DEFAULT
925 def_bool ARCH_SPARSEMEM_ENABLE
927 config ARCH_SELECT_MEMORY_MODEL
928 def_bool ARCH_SPARSEMEM_ENABLE
930 config ARCH_FLATMEM_ENABLE
931 def_bool !NUMA
933 config HAVE_ARCH_PFN_VALID
934 def_bool y
936 config HW_PERF_EVENTS
937 def_bool y
938 depends on ARM_PMU
940 config SYS_SUPPORTS_HUGETLBFS
941 def_bool y
943 config ARCH_WANT_HUGE_PMD_SHARE
945 config ARCH_HAS_CACHE_LINE_SIZE
946 def_bool y
948 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
949 def_bool y if PGTABLE_LEVELS > 2
951 config SECCOMP
952 bool "Enable seccomp to safely compute untrusted bytecode"
953 ---help---
954 This kernel feature is useful for number crunching applications
955 that may need to compute untrusted bytecode during their
956 execution. By using pipes or other transports made available to
957 the process as file descriptors supporting the read/write
958 syscalls, it's possible to isolate those applications in
959 their own address space using seccomp. Once seccomp is
960 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
961 and the task is only allowed to execute a few safe syscalls
962 defined by each seccomp mode.
964 config PARAVIRT
965 bool "Enable paravirtualization code"
966 help
967 This changes the kernel so it can modify itself when it is run
968 under a hypervisor, potentially improving performance significantly
969 over full virtualization.
971 config PARAVIRT_TIME_ACCOUNTING
972 bool "Paravirtual steal time accounting"
973 select PARAVIRT
974 help
975 Select this option to enable fine granularity task steal time
976 accounting. Time spent executing other tasks in parallel with
977 the current vCPU is discounted from the vCPU power. To account for
978 that, there can be a small performance impact.
980 If in doubt, say N here.
982 config KEXEC
983 depends on PM_SLEEP_SMP
984 select KEXEC_CORE
985 bool "kexec system call"
986 ---help---
987 kexec is a system call that implements the ability to shutdown your
988 current kernel, and to start another kernel. It is like a reboot
989 but it is independent of the system firmware. And like a reboot
990 you can start any kernel with it, not just Linux.
992 config KEXEC_FILE
993 bool "kexec file based system call"
994 select KEXEC_CORE
995 help
996 This is new version of kexec system call. This system call is
997 file based and takes file descriptors as system call argument
998 for kernel and initramfs as opposed to list of segments as
999 accepted by previous system call.
1001 config KEXEC_SIG
1002 bool "Verify kernel signature during kexec_file_load() syscall"
1003 depends on KEXEC_FILE
1004 help
1005 Select this option to verify a signature with loaded kernel
1006 image. If configured, any attempt of loading a image without
1007 valid signature will fail.
1009 In addition to that option, you need to enable signature
1010 verification for the corresponding kernel image type being
1011 loaded in order for this to work.
1013 config KEXEC_IMAGE_VERIFY_SIG
1014 bool "Enable Image signature verification support"
1015 default y
1016 depends on KEXEC_SIG
1017 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1018 help
1019 Enable Image signature verification support.
1021 comment "Support for PE file signature verification disabled"
1022 depends on KEXEC_SIG
1023 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1025 config CRASH_DUMP
1026 bool "Build kdump crash kernel"
1027 help
1028 Generate crash dump after being started by kexec. This should
1029 be normally only set in special crash dump kernels which are
1030 loaded in the main kernel with kexec-tools into a specially
1031 reserved region and then later executed after a crash by
1032 kdump/kexec.
1034 For more details see Documentation/admin-guide/kdump/kdump.rst
1036 config XEN_DOM0
1037 def_bool y
1038 depends on XEN
1040 config XEN
1041 bool "Xen guest support on ARM64"
1042 depends on ARM64 && OF
1043 select SWIOTLB_XEN
1044 select PARAVIRT
1045 help
1046 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1048 config FORCE_MAX_ZONEORDER
1049 int
1050 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1051 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1052 default "11"
1053 help
1054 The kernel memory allocator divides physically contiguous memory
1055 blocks into "zones", where each zone is a power of two number of
1056 pages. This option selects the largest power of two that the kernel
1057 keeps in the memory allocator. If you need to allocate very large
1058 blocks of physically contiguous memory, then you may need to
1059 increase this value.
1061 This config option is actually maximum order plus one. For example,
1062 a value of 11 means that the largest free memory block is 2^10 pages.
1064 We make sure that we can allocate upto a HugePage size for each configuration.
1065 Hence we have :
1066 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1068 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1069 4M allocations matching the default size used by generic code.
1071 config UNMAP_KERNEL_AT_EL0
1072 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1073 default y
1074 help
1075 Speculation attacks against some high-performance processors can
1076 be used to bypass MMU permission checks and leak kernel data to
1077 userspace. This can be defended against by unmapping the kernel
1078 when running in userspace, mapping it back in on exception entry
1079 via a trampoline page in the vector table.
1081 If unsure, say Y.
1083 config HARDEN_BRANCH_PREDICTOR
1084 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1085 default y
1086 help
1087 Speculation attacks against some high-performance processors rely on
1088 being able to manipulate the branch predictor for a victim context by
1089 executing aliasing branches in the attacker context. Such attacks
1090 can be partially mitigated against by clearing internal branch
1091 predictor state and limiting the prediction logic in some situations.
1093 This config option will take CPU-specific actions to harden the
1094 branch predictor against aliasing attacks and may rely on specific
1095 instruction sequences or control bits being set by the system
1096 firmware.
1098 If unsure, say Y.
1100 config HARDEN_EL2_VECTORS
1101 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1102 default y
1103 help
1104 Speculation attacks against some high-performance processors can
1105 be used to leak privileged information such as the vector base
1106 register, resulting in a potential defeat of the EL2 layout
1107 randomization.
1109 This config option will map the vectors to a fixed location,
1110 independent of the EL2 code mapping, so that revealing VBAR_EL2
1111 to an attacker does not give away any extra information. This
1112 only gets enabled on affected CPUs.
1114 If unsure, say Y.
1116 config ARM64_SSBD
1117 bool "Speculative Store Bypass Disable" if EXPERT
1118 default y
1119 help
1120 This enables mitigation of the bypassing of previous stores
1121 by speculative loads.
1123 If unsure, say Y.
1125 config RODATA_FULL_DEFAULT_ENABLED
1126 bool "Apply r/o permissions of VM areas also to their linear aliases"
1127 default y
1128 help
1129 Apply read-only attributes of VM areas to the linear alias of
1130 the backing pages as well. This prevents code or read-only data
1131 from being modified (inadvertently or intentionally) via another
1132 mapping of the same memory page. This additional enhancement can
1133 be turned off at runtime by passing rodata=[off|on] (and turned on
1134 with rodata=full if this option is set to 'n')
1136 This requires the linear region to be mapped down to pages,
1137 which may adversely affect performance in some cases.
1139 config ARM64_SW_TTBR0_PAN
1140 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1141 help
1142 Enabling this option prevents the kernel from accessing
1143 user-space memory directly by pointing TTBR0_EL1 to a reserved
1144 zeroed area and reserved ASID. The user access routines
1145 restore the valid TTBR0_EL1 temporarily.
1147 config ARM64_TAGGED_ADDR_ABI
1148 bool "Enable the tagged user addresses syscall ABI"
1149 default y
1150 help
1151 When this option is enabled, user applications can opt in to a
1152 relaxed ABI via prctl() allowing tagged addresses to be passed
1153 to system calls as pointer arguments. For details, see
1154 Documentation/arm64/tagged-address-abi.rst.
1156 menuconfig COMPAT
1157 bool "Kernel support for 32-bit EL0"
1158 depends on ARM64_4K_PAGES || EXPERT
1159 select COMPAT_BINFMT_ELF if BINFMT_ELF
1160 select HAVE_UID16
1161 select OLD_SIGSUSPEND3
1162 select COMPAT_OLD_SIGACTION
1163 help
1164 This option enables support for a 32-bit EL0 running under a 64-bit
1165 kernel at EL1. AArch32-specific components such as system calls,
1166 the user helper functions, VFP support and the ptrace interface are
1167 handled appropriately by the kernel.
1169 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1170 that you will only be able to execute AArch32 binaries that were compiled
1171 with page size aligned segments.
1173 If you want to execute 32-bit userspace applications, say Y.
1175 if COMPAT
1177 config KUSER_HELPERS
1178 bool "Enable kuser helpers page for 32-bit applications"
1179 default y
1180 help
1181 Warning: disabling this option may break 32-bit user programs.
1183 Provide kuser helpers to compat tasks. The kernel provides
1184 helper code to userspace in read only form at a fixed location
1185 to allow userspace to be independent of the CPU type fitted to
1186 the system. This permits binaries to be run on ARMv4 through
1187 to ARMv8 without modification.
1189 See Documentation/arm/kernel_user_helpers.rst for details.
1191 However, the fixed address nature of these helpers can be used
1192 by ROP (return orientated programming) authors when creating
1193 exploits.
1195 If all of the binaries and libraries which run on your platform
1196 are built specifically for your platform, and make no use of
1197 these helpers, then you can turn this option off to hinder
1198 such exploits. However, in that case, if a binary or library
1199 relying on those helpers is run, it will not function correctly.
1201 Say N here only if you are absolutely certain that you do not
1202 need these helpers; otherwise, the safe option is to say Y.
1204 config COMPAT_VDSO
1205 bool "Enable vDSO for 32-bit applications"
1206 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1207 select GENERIC_COMPAT_VDSO
1208 default y
1209 help
1210 Place in the process address space of 32-bit applications an
1211 ELF shared object providing fast implementations of gettimeofday
1212 and clock_gettime.
1214 You must have a 32-bit build of glibc 2.22 or later for programs
1215 to seamlessly take advantage of this.
1217 menuconfig ARMV8_DEPRECATED
1218 bool "Emulate deprecated/obsolete ARMv8 instructions"
1219 depends on SYSCTL
1220 help
1221 Legacy software support may require certain instructions
1222 that have been deprecated or obsoleted in the architecture.
1224 Enable this config to enable selective emulation of these
1225 features.
1227 If unsure, say Y
1229 if ARMV8_DEPRECATED
1231 config SWP_EMULATION
1232 bool "Emulate SWP/SWPB instructions"
1233 help
1234 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1235 they are always undefined. Say Y here to enable software
1236 emulation of these instructions for userspace using LDXR/STXR.
1238 In some older versions of glibc [<=2.8] SWP is used during futex
1239 trylock() operations with the assumption that the code will not
1240 be preempted. This invalid assumption may be more likely to fail
1241 with SWP emulation enabled, leading to deadlock of the user
1242 application.
1244 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1245 on an external transaction monitoring block called a global
1246 monitor to maintain update atomicity. If your system does not
1247 implement a global monitor, this option can cause programs that
1248 perform SWP operations to uncached memory to deadlock.
1250 If unsure, say Y
1252 config CP15_BARRIER_EMULATION
1253 bool "Emulate CP15 Barrier instructions"
1254 help
1255 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1256 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1257 strongly recommended to use the ISB, DSB, and DMB
1258 instructions instead.
1260 Say Y here to enable software emulation of these
1261 instructions for AArch32 userspace code. When this option is
1262 enabled, CP15 barrier usage is traced which can help
1263 identify software that needs updating.
1265 If unsure, say Y
1267 config SETEND_EMULATION
1268 bool "Emulate SETEND instruction"
1269 help
1270 The SETEND instruction alters the data-endianness of the
1271 AArch32 EL0, and is deprecated in ARMv8.
1273 Say Y here to enable software emulation of the instruction
1274 for AArch32 userspace code.
1276 Note: All the cpus on the system must have mixed endian support at EL0
1277 for this feature to be enabled. If a new CPU - which doesn't support mixed
1278 endian - is hotplugged in after this feature has been enabled, there could
1279 be unexpected results in the applications.
1281 If unsure, say Y
1282 endif
1284 endif
1286 menu "ARMv8.1 architectural features"
1288 config ARM64_HW_AFDBM
1289 bool "Support for hardware updates of the Access and Dirty page flags"
1290 default y
1291 help
1292 The ARMv8.1 architecture extensions introduce support for
1293 hardware updates of the access and dirty information in page
1294 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1295 capable processors, accesses to pages with PTE_AF cleared will
1296 set this bit instead of raising an access flag fault.
1297 Similarly, writes to read-only pages with the DBM bit set will
1298 clear the read-only bit (AP[2]) instead of raising a
1299 permission fault.
1301 Kernels built with this configuration option enabled continue
1302 to work on pre-ARMv8.1 hardware and the performance impact is
1303 minimal. If unsure, say Y.
1305 config ARM64_PAN
1306 bool "Enable support for Privileged Access Never (PAN)"
1307 default y
1308 help
1309 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1310 prevents the kernel or hypervisor from accessing user-space (EL0)
1311 memory directly.
1313 Choosing this option will cause any unprotected (not using
1314 copy_to_user et al) memory access to fail with a permission fault.
1316 The feature is detected at runtime, and will remain as a 'nop'
1317 instruction if the cpu does not implement the feature.
1319 config ARM64_LSE_ATOMICS
1320 bool "Atomic instructions"
1321 depends on JUMP_LABEL
1322 default y
1323 help
1324 As part of the Large System Extensions, ARMv8.1 introduces new
1325 atomic instructions that are designed specifically to scale in
1326 very large systems.
1328 Say Y here to make use of these instructions for the in-kernel
1329 atomic routines. This incurs a small overhead on CPUs that do
1330 not support these instructions and requires the kernel to be
1331 built with binutils >= 2.25 in order for the new instructions
1332 to be used.
1334 config ARM64_VHE
1335 bool "Enable support for Virtualization Host Extensions (VHE)"
1336 default y
1337 help
1338 Virtualization Host Extensions (VHE) allow the kernel to run
1339 directly at EL2 (instead of EL1) on processors that support
1340 it. This leads to better performance for KVM, as they reduce
1341 the cost of the world switch.
1343 Selecting this option allows the VHE feature to be detected
1344 at runtime, and does not affect processors that do not
1345 implement this feature.
1347 endmenu
1349 menu "ARMv8.2 architectural features"
1351 config ARM64_UAO
1352 bool "Enable support for User Access Override (UAO)"
1353 default y
1354 help
1355 User Access Override (UAO; part of the ARMv8.2 Extensions)
1356 causes the 'unprivileged' variant of the load/store instructions to
1357 be overridden to be privileged.
1359 This option changes get_user() and friends to use the 'unprivileged'
1360 variant of the load/store instructions. This ensures that user-space
1361 really did have access to the supplied memory. When addr_limit is
1362 set to kernel memory the UAO bit will be set, allowing privileged
1363 access to kernel memory.
1365 Choosing this option will cause copy_to_user() et al to use user-space
1366 memory permissions.
1368 The feature is detected at runtime, the kernel will use the
1369 regular load/store instructions if the cpu does not implement the
1370 feature.
1372 config ARM64_PMEM
1373 bool "Enable support for persistent memory"
1374 select ARCH_HAS_PMEM_API
1375 select ARCH_HAS_UACCESS_FLUSHCACHE
1376 help
1377 Say Y to enable support for the persistent memory API based on the
1378 ARMv8.2 DCPoP feature.
1380 The feature is detected at runtime, and the kernel will use DC CVAC
1381 operations if DC CVAP is not supported (following the behaviour of
1382 DC CVAP itself if the system does not define a point of persistence).
1384 config ARM64_RAS_EXTN
1385 bool "Enable support for RAS CPU Extensions"
1386 default y
1387 help
1388 CPUs that support the Reliability, Availability and Serviceability
1389 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1390 errors, classify them and report them to software.
1392 On CPUs with these extensions system software can use additional
1393 barriers to determine if faults are pending and read the
1394 classification from a new set of registers.
1396 Selecting this feature will allow the kernel to use these barriers
1397 and access the new registers if the system supports the extension.
1398 Platform RAS features may additionally depend on firmware support.
1400 config ARM64_CNP
1401 bool "Enable support for Common Not Private (CNP) translations"
1402 default y
1403 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1404 help
1405 Common Not Private (CNP) allows translation table entries to
1406 be shared between different PEs in the same inner shareable
1407 domain, so the hardware can use this fact to optimise the
1408 caching of such entries in the TLB.
1410 Selecting this option allows the CNP feature to be detected
1411 at runtime, and does not affect PEs that do not implement
1412 this feature.
1414 endmenu
1416 menu "ARMv8.3 architectural features"
1418 config ARM64_PTR_AUTH
1419 bool "Enable support for pointer authentication"
1420 default y
1421 depends on !KVM || ARM64_VHE
1422 help
1423 Pointer authentication (part of the ARMv8.3 Extensions) provides
1424 instructions for signing and authenticating pointers against secret
1425 keys, which can be used to mitigate Return Oriented Programming (ROP)
1426 and other attacks.
1428 This option enables these instructions at EL0 (i.e. for userspace).
1430 Choosing this option will cause the kernel to initialise secret keys
1431 for each process at exec() time, with these keys being
1432 context-switched along with the process.
1434 The feature is detected at runtime. If the feature is not present in
1435 hardware it will not be advertised to userspace/KVM guest nor will it
1436 be enabled. However, KVM guest also require VHE mode and hence
1437 CONFIG_ARM64_VHE=y option to use this feature.
1439 endmenu
1441 config ARM64_SVE
1442 bool "ARM Scalable Vector Extension support"
1443 default y
1444 depends on !KVM || ARM64_VHE
1445 help
1446 The Scalable Vector Extension (SVE) is an extension to the AArch64
1447 execution state which complements and extends the SIMD functionality
1448 of the base architecture to support much larger vectors and to enable
1449 additional vectorisation opportunities.
1451 To enable use of this extension on CPUs that implement it, say Y.
1453 On CPUs that support the SVE2 extensions, this option will enable
1454 those too.
1456 Note that for architectural reasons, firmware _must_ implement SVE
1457 support when running on SVE capable hardware. The required support
1458 is present in:
1460 * version 1.5 and later of the ARM Trusted Firmware
1461 * the AArch64 boot wrapper since commit 5e1261e08abf
1462 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1464 For other firmware implementations, consult the firmware documentation
1465 or vendor.
1467 If you need the kernel to boot on SVE-capable hardware with broken
1468 firmware, you may need to say N here until you get your firmware
1469 fixed. Otherwise, you may experience firmware panics or lockups when
1470 booting the kernel. If unsure and you are not observing these
1471 symptoms, you should assume that it is safe to say Y.
1473 CPUs that support SVE are architecturally required to support the
1474 Virtualization Host Extensions (VHE), so the kernel makes no
1475 provision for supporting SVE alongside KVM without VHE enabled.
1476 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1477 KVM in the same kernel image.
1479 config ARM64_MODULE_PLTS
1480 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1481 depends on MODULES
1482 select HAVE_MOD_ARCH_SPECIFIC
1483 help
1484 Allocate PLTs when loading modules so that jumps and calls whose
1485 targets are too far away for their relative offsets to be encoded
1486 in the instructions themselves can be bounced via veneers in the
1487 module's PLT. This allows modules to be allocated in the generic
1488 vmalloc area after the dedicated module memory area has been
1489 exhausted.
1491 When running with address space randomization (KASLR), the module
1492 region itself may be too far away for ordinary relative jumps and
1493 calls, and so in that case, module PLTs are required and cannot be
1494 disabled.
1496 Specific errata workaround(s) might also force module PLTs to be
1497 enabled (ARM64_ERRATUM_843419).
1499 config ARM64_PSEUDO_NMI
1500 bool "Support for NMI-like interrupts"
1501 select CONFIG_ARM_GIC_V3
1502 help
1503 Adds support for mimicking Non-Maskable Interrupts through the use of
1504 GIC interrupt priority. This support requires version 3 or later of
1505 ARM GIC.
1507 This high priority configuration for interrupts needs to be
1508 explicitly enabled by setting the kernel parameter
1509 "irqchip.gicv3_pseudo_nmi" to 1.
1511 If unsure, say N
1513 if ARM64_PSEUDO_NMI
1514 config ARM64_DEBUG_PRIORITY_MASKING
1515 bool "Debug interrupt priority masking"
1516 help
1517 This adds runtime checks to functions enabling/disabling
1518 interrupts when using priority masking. The additional checks verify
1519 the validity of ICC_PMR_EL1 when calling concerned functions.
1521 If unsure, say N
1522 endif
1524 config RELOCATABLE
1525 bool
1526 select ARCH_HAS_RELR
1527 help
1528 This builds the kernel as a Position Independent Executable (PIE),
1529 which retains all relocation metadata required to relocate the
1530 kernel binary at runtime to a different virtual address than the
1531 address it was linked at.
1532 Since AArch64 uses the RELA relocation format, this requires a
1533 relocation pass at runtime even if the kernel is loaded at the
1534 same address it was linked at.
1536 config RANDOMIZE_BASE
1537 bool "Randomize the address of the kernel image"
1538 select ARM64_MODULE_PLTS if MODULES
1539 select RELOCATABLE
1540 help
1541 Randomizes the virtual address at which the kernel image is
1542 loaded, as a security feature that deters exploit attempts
1543 relying on knowledge of the location of kernel internals.
1545 It is the bootloader's job to provide entropy, by passing a
1546 random u64 value in /chosen/kaslr-seed at kernel entry.
1548 When booting via the UEFI stub, it will invoke the firmware's
1549 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1550 to the kernel proper. In addition, it will randomise the physical
1551 location of the kernel Image as well.
1553 If unsure, say N.
1555 config RANDOMIZE_MODULE_REGION_FULL
1556 bool "Randomize the module region over a 4 GB range"
1557 depends on RANDOMIZE_BASE
1558 default y
1559 help
1560 Randomizes the location of the module region inside a 4 GB window
1561 covering the core kernel. This way, it is less likely for modules
1562 to leak information about the location of core kernel data structures
1563 but it does imply that function calls between modules and the core
1564 kernel will need to be resolved via veneers in the module PLT.
1566 When this option is not set, the module region will be randomized over
1567 a limited range that contains the [_stext, _etext] interval of the
1568 core kernel, so branch relocations are always in range.
1570 config CC_HAVE_STACKPROTECTOR_SYSREG
1571 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1573 config STACKPROTECTOR_PER_TASK
1574 def_bool y
1575 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1577 endmenu
1579 menu "Boot options"
1581 config ARM64_ACPI_PARKING_PROTOCOL
1582 bool "Enable support for the ARM64 ACPI parking protocol"
1583 depends on ACPI
1584 help
1585 Enable support for the ARM64 ACPI parking protocol. If disabled
1586 the kernel will not allow booting through the ARM64 ACPI parking
1587 protocol even if the corresponding data is present in the ACPI
1588 MADT table.
1590 config CMDLINE
1591 string "Default kernel command string"
1592 default ""
1593 help
1594 Provide a set of default command-line options at build time by
1595 entering them here. As a minimum, you should specify the the
1596 root device (e.g. root=/dev/nfs).
1598 config CMDLINE_FORCE
1599 bool "Always use the default kernel command string"
1600 help
1601 Always use the default kernel command string, even if the boot
1602 loader passes other arguments to the kernel.
1603 This is useful if you cannot or don't want to change the
1604 command-line options your boot loader passes to the kernel.
1606 config EFI_STUB
1607 bool
1609 config EFI
1610 bool "UEFI runtime support"
1611 depends on OF && !CPU_BIG_ENDIAN
1612 depends on KERNEL_MODE_NEON
1613 select ARCH_SUPPORTS_ACPI
1614 select LIBFDT
1615 select UCS2_STRING
1616 select EFI_PARAMS_FROM_FDT
1617 select EFI_RUNTIME_WRAPPERS
1618 select EFI_STUB
1619 select EFI_ARMSTUB
1620 default y
1621 help
1622 This option provides support for runtime services provided
1623 by UEFI firmware (such as non-volatile variables, realtime
1624 clock, and platform reset). A UEFI stub is also provided to
1625 allow the kernel to be booted as an EFI application. This
1626 is only useful on systems that have UEFI firmware.
1628 config DMI
1629 bool "Enable support for SMBIOS (DMI) tables"
1630 depends on EFI
1631 default y
1632 help
1633 This enables SMBIOS/DMI feature for systems.
1635 This option is only useful on systems that have UEFI firmware.
1636 However, even with this option, the resultant kernel should
1637 continue to boot on existing non-UEFI platforms.
1639 endmenu
1641 config SYSVIPC_COMPAT
1642 def_bool y
1643 depends on COMPAT && SYSVIPC
1645 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1646 def_bool y
1647 depends on HUGETLB_PAGE && MIGRATION
1649 menu "Power management options"
1651 source "kernel/power/Kconfig"
1653 config ARCH_HIBERNATION_POSSIBLE
1654 def_bool y
1655 depends on CPU_PM
1657 config ARCH_HIBERNATION_HEADER
1658 def_bool y
1659 depends on HIBERNATION
1661 config ARCH_SUSPEND_POSSIBLE
1662 def_bool y
1664 endmenu
1666 menu "CPU Power Management"
1668 source "drivers/cpuidle/Kconfig"
1670 source "drivers/cpufreq/Kconfig"
1672 endmenu
1674 source "drivers/firmware/Kconfig"
1676 source "drivers/acpi/Kconfig"
1678 source "arch/arm64/kvm/Kconfig"
1680 if CRYPTO
1681 source "arch/arm64/crypto/Kconfig"
1682 endif