arch/arc/include/asm/perf_event.h

   1 /*
   2  * Linux performance counter support for ARC
   3  *
   4  * Copyright (C) 2011-2013 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #ifndef __ASM_PERF_EVENT_H
  13 #define __ASM_PERF_EVENT_H
  14
  15 /* real maximum varies per CPU, this is the maximum supported by the driver */
  16 #define ARC_PMU_MAX_HWEVENTS    64
  17
  18 #define ARC_REG_CC_BUILD        0xF6
  19 #define ARC_REG_CC_INDEX        0x240
  20 #define ARC_REG_CC_NAME0        0x241
  21 #define ARC_REG_CC_NAME1        0x242
  22
  23 #define ARC_REG_PCT_BUILD       0xF5
  24 #define ARC_REG_PCT_COUNTL      0x250
  25 #define ARC_REG_PCT_COUNTH      0x251
  26 #define ARC_REG_PCT_SNAPL       0x252
  27 #define ARC_REG_PCT_SNAPH       0x253
  28 #define ARC_REG_PCT_CONFIG      0x254
  29 #define ARC_REG_PCT_CONTROL     0x255
  30 #define ARC_REG_PCT_INDEX       0x256
  31
  32 #define ARC_REG_PCT_CONTROL_CC  (1 << 16)       /* clear counts */
  33 #define ARC_REG_PCT_CONTROL_SN  (1 << 17)       /* snapshot */
  34
  35 struct arc_reg_pct_build {
  36 #ifdef CONFIG_CPU_BIG_ENDIAN
  37         unsigned int m:8, c:8, r:6, s:2, v:8;
  38 #else
  39         unsigned int v:8, s:2, r:6, c:8, m:8;
  40 #endif
  41 };
  42
  43 struct arc_reg_cc_build {
  44 #ifdef CONFIG_CPU_BIG_ENDIAN
  45         unsigned int c:16, r:8, v:8;
  46 #else
  47         unsigned int v:8, r:8, c:16;
  48 #endif
  49 };
  50
  51 #define PERF_COUNT_ARC_DCLM     (PERF_COUNT_HW_MAX + 0)
  52 #define PERF_COUNT_ARC_DCSM     (PERF_COUNT_HW_MAX + 1)
  53 #define PERF_COUNT_ARC_ICM      (PERF_COUNT_HW_MAX + 2)
  54 #define PERF_COUNT_ARC_BPOK     (PERF_COUNT_HW_MAX + 3)
  55 #define PERF_COUNT_ARC_EDTLB    (PERF_COUNT_HW_MAX + 4)
  56 #define PERF_COUNT_ARC_EITLB    (PERF_COUNT_HW_MAX + 5)
  57 #define PERF_COUNT_ARC_LDC      (PERF_COUNT_HW_MAX + 6)
  58 #define PERF_COUNT_ARC_STC      (PERF_COUNT_HW_MAX + 7)
  59
  60 #define PERF_COUNT_ARC_HW_MAX   (PERF_COUNT_HW_MAX + 8)
  61
  62 /*
  63  * Some ARC pct quirks:
  64  *
  65  * PERF_COUNT_HW_STALLED_CYCLES_BACKEND
  66  * PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
  67  *      The ARC 700 can either measure stalls per pipeline stage, or all stalls
  68  *      combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
  69  *      and all pipeline flushes (e.g. caused by mispredicts, etc.) to
  70  *      STALLED_CYCLES_FRONTEND.
  71  *
  72  *      We could start multiple performance counters and combine everything
  73  *      afterwards, but that makes it complicated.
  74  *
  75  *      Note that I$ cache misses aren't counted by either of the two!
  76  */
  77
  78 /*
  79  * ARC PCT has hardware conditions with fixed "names" but variable "indexes"
  80  * (based on a specific RTL build)
  81  * Below is the static map between perf generic/arc specific event_id and
  82  * h/w condition names.
  83  * At the time of probe, we loop thru each index and find it's name to
  84  * complete the mapping of perf event_id to h/w index as latter is needed
  85  * to program the counter really
  86  */
  87 static const char * const arc_pmu_ev_hw_map[] = {
  88         /* count cycles */
  89         [PERF_COUNT_HW_CPU_CYCLES] = "crun",
  90         [PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
  91         [PERF_COUNT_HW_BUS_CYCLES] = "crun",
  92
  93         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
  94         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",
  95
  96         /* counts condition */
  97         [PERF_COUNT_HW_INSTRUCTIONS] = "iall",
  98         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp",
  99         [PERF_COUNT_ARC_BPOK]         = "bpok",   /* NP-NT, PT-T, PNT-NT */
 100         [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
 101
 102         [PERF_COUNT_ARC_LDC] = "imemrdc",       /* Instr: mem read cached */
 103         [PERF_COUNT_ARC_STC] = "imemwrc",       /* Instr: mem write cached */
 104
 105         [PERF_COUNT_ARC_DCLM] = "dclm",         /* D-cache Load Miss */
 106         [PERF_COUNT_ARC_DCSM] = "dcsm",         /* D-cache Store Miss */
 107         [PERF_COUNT_ARC_ICM] = "icm",           /* I-cache Miss */
 108         [PERF_COUNT_ARC_EDTLB] = "edtlb",       /* D-TLB Miss */
 109         [PERF_COUNT_ARC_EITLB] = "eitlb",       /* I-TLB Miss */
 110 };
 111
 112 #define C(_x)                   PERF_COUNT_HW_CACHE_##_x
 113 #define CACHE_OP_UNSUPPORTED    0xffff
 114
 115 static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 116         [C(L1D)] = {
 117                 [C(OP_READ)] = {
 118                         [C(RESULT_ACCESS)]      = PERF_COUNT_ARC_LDC,
 119                         [C(RESULT_MISS)]        = PERF_COUNT_ARC_DCLM,
 120                 },
 121                 [C(OP_WRITE)] = {
 122                         [C(RESULT_ACCESS)]      = PERF_COUNT_ARC_STC,
 123                         [C(RESULT_MISS)]        = PERF_COUNT_ARC_DCSM,
 124                 },
 125                 [C(OP_PREFETCH)] = {
 126                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 127                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 128                 },
 129         },
 130         [C(L1I)] = {
 131                 [C(OP_READ)] = {
 132                         [C(RESULT_ACCESS)]      = PERF_COUNT_HW_INSTRUCTIONS,
 133                         [C(RESULT_MISS)]        = PERF_COUNT_ARC_ICM,
 134                 },
 135                 [C(OP_WRITE)] = {
 136                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 137                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 138                 },
 139                 [C(OP_PREFETCH)] = {
 140                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 141                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 142                 },
 143         },
 144         [C(LL)] = {
 145                 [C(OP_READ)] = {
 146                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 147                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 148                 },
 149                 [C(OP_WRITE)] = {
 150                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 151                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 152                 },
 153                 [C(OP_PREFETCH)] = {
 154                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 155                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 156                 },
 157         },
 158         [C(DTLB)] = {
 159                 [C(OP_READ)] = {
 160                         [C(RESULT_ACCESS)]      = PERF_COUNT_ARC_LDC,
 161                         [C(RESULT_MISS)]        = PERF_COUNT_ARC_EDTLB,
 162                 },
 163                         /* DTLB LD/ST Miss not segregated by h/w*/
 164                 [C(OP_WRITE)] = {
 165                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 166                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 167                 },
 168                 [C(OP_PREFETCH)] = {
 169                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 170                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 171                 },
 172         },
 173         [C(ITLB)] = {
 174                 [C(OP_READ)] = {
 175                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 176                         [C(RESULT_MISS)]        = PERF_COUNT_ARC_EITLB,
 177                 },
 178                 [C(OP_WRITE)] = {
 179                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 180                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 181                 },
 182                 [C(OP_PREFETCH)] = {
 183                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 184                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 185                 },
 186         },
 187         [C(BPU)] = {
 188                 [C(OP_READ)] = {
 189                         [C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
 190                         [C(RESULT_MISS)]        = PERF_COUNT_HW_BRANCH_MISSES,
 191                 },
 192                 [C(OP_WRITE)] = {
 193                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 194                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 195                 },
 196                 [C(OP_PREFETCH)] = {
 197                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 198                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 199                 },
 200         },
 201         [C(NODE)] = {
 202                 [C(OP_READ)] = {
 203                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 204                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 205                 },
 206                 [C(OP_WRITE)] = {
 207                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 208                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 209                 },
 210                 [C(OP_PREFETCH)] = {
 211                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 212                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 213                 },
 214         },
 215 };
 216
 217 #endif /* __ASM_PERF_EVENT_H */