arch/arm/boot/dts/am335x-evm.dts

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "am33xx.dtsi"
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12
  13 / {
  14         model = "TI AM335x EVM";
  15         compatible = "ti,am335x-evm", "ti,am33xx";
  16
  17         cpus {
  18                 cpu@0 {
  19                         cpu0-supply = <&vdd1_reg>;
  20                 };
  21         };
  22
  23         memory {
  24                 device_type = "memory";
  25                 reg = <0x80000000 0x10000000>; /* 256 MB */
  26         };
  27
  28         vbat: fixedregulator@0 {
  29                 compatible = "regulator-fixed";
  30                 regulator-name = "vbat";
  31                 regulator-min-microvolt = <5000000>;
  32                 regulator-max-microvolt = <5000000>;
  33                 regulator-boot-on;
  34         };
  35
  36         lis3_reg: fixedregulator@1 {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "lis3_reg";
  39                 regulator-boot-on;
  40         };
  41
  42         wlan_en_reg: fixedregulator@2 {
  43                 compatible = "regulator-fixed";
  44                 regulator-name = "wlan-en-regulator";
  45                 regulator-min-microvolt = <1800000>;
  46                 regulator-max-microvolt = <1800000>;
  47
  48                 /* WLAN_EN GPIO for this board - Bank1, pin16 */
  49                 gpio = <&gpio1 16 0>;
  50
  51                 /* WLAN card specific delay */
  52                 startup-delay-us = <70000>;
  53                 enable-active-high;
  54         };
  55
  56         matrix_keypad: matrix_keypad@0 {
  57                 compatible = "gpio-matrix-keypad";
  58                 debounce-delay-ms = <5>;
  59                 col-scan-delay-us = <2>;
  60
  61                 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH         /* Bank1, pin25 */
  62                              &gpio1 26 GPIO_ACTIVE_HIGH         /* Bank1, pin26 */
  63                              &gpio1 27 GPIO_ACTIVE_HIGH>;       /* Bank1, pin27 */
  64
  65                 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH         /* Bank1, pin21 */
  66                              &gpio1 22 GPIO_ACTIVE_HIGH>;       /* Bank1, pin22 */
  67
  68                 linux,keymap = <0x0000008b      /* MENU */
  69                                 0x0100009e      /* BACK */
  70                                 0x02000069      /* LEFT */
  71                                 0x0001006a      /* RIGHT */
  72                                 0x0101001c      /* ENTER */
  73                                 0x0201006c>;    /* DOWN */
  74         };
  75
  76         gpio_keys: volume_keys@0 {
  77                 compatible = "gpio-keys";
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80                 autorepeat;
  81
  82                 switch@9 {
  83                         label = "volume-up";
  84                         linux,code = <115>;
  85                         gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  86                         gpio-key,wakeup;
  87                 };
  88
  89                 switch@10 {
  90                         label = "volume-down";
  91                         linux,code = <114>;
  92                         gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
  93                         gpio-key,wakeup;
  94                 };
  95         };
  96
  97         backlight {
  98                 compatible = "pwm-backlight";
  99                 pwms = <&ecap0 0 50000 0>;
 100                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
 101                 default-brightness-level = <8>;
 102         };
 103
 104         panel {
 105                 compatible = "ti,tilcdc,panel";
 106                 status = "okay";
 107                 pinctrl-names = "default";
 108                 pinctrl-0 = <&lcd_pins_s0>;
 109                 panel-info {
 110                         ac-bias           = <255>;
 111                         ac-bias-intrpt    = <0>;
 112                         dma-burst-sz      = <16>;
 113                         bpp               = <32>;
 114                         fdd               = <0x80>;
 115                         sync-edge         = <0>;
 116                         sync-ctrl         = <1>;
 117                         raster-order      = <0>;
 118                         fifo-th           = <0>;
 119                 };
 120
 121                 display-timings {
 122                         800x480p62 {
 123                                 clock-frequency = <30000000>;
 124                                 hactive = <800>;
 125                                 vactive = <480>;
 126                                 hfront-porch = <39>;
 127                                 hback-porch = <39>;
 128                                 hsync-len = <47>;
 129                                 vback-porch = <29>;
 130                                 vfront-porch = <13>;
 131                                 vsync-len = <2>;
 132                                 hsync-active = <1>;
 133                                 vsync-active = <1>;
 134                         };
 135                 };
 136         };
 137
 138         sound {
 139                 compatible = "ti,da830-evm-audio";
 140                 ti,model = "AM335x-EVM";
 141                 ti,audio-codec = <&tlv320aic3106>;
 142                 ti,mcasp-controller = <&mcasp1>;
 143                 ti,codec-clock-rate = <12000000>;
 144                 ti,audio-routing =
 145                         "Headphone Jack",       "HPLOUT",
 146                         "Headphone Jack",       "HPROUT",
 147                         "LINE1L",               "Line In",
 148                         "LINE1R",               "Line In";
 149         };
 150 };
 151
 152 &am33xx_pinmux {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
 155
 156         matrix_keypad_s0: matrix_keypad_s0 {
 157                 pinctrl-single,pins = <
 158                         0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
 159                         0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a6.gpio1_22 */
 160                         0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a9.gpio1_25 */
 161                         0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a10.gpio1_26 */
 162                         0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a11.gpio1_27 */
 163                 >;
 164         };
 165
 166         volume_keys_s0: volume_keys_s0 {
 167                 pinctrl-single,pins = <
 168                         0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_sclk.gpio0_2 */
 169                         0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_d0.gpio0_3 */
 170                 >;
 171         };
 172
 173         i2c0_pins: pinmux_i2c0_pins {
 174                 pinctrl-single,pins = <
 175                         0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
 176                         0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
 177                 >;
 178         };
 179
 180         i2c1_pins: pinmux_i2c1_pins {
 181                 pinctrl-single,pins = <
 182                         0x158 (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_d1.i2c1_sda */
 183                         0x15c (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_cs0.i2c1_scl */
 184                 >;
 185         };
 186
 187         uart0_pins: pinmux_uart0_pins {
 188                 pinctrl-single,pins = <
 189                         0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
 190                         0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
 191                 >;
 192         };
 193
 194         uart1_pins: pinmux_uart1_pins {
 195                 pinctrl-single,pins = <
 196                         0x178 (PIN_INPUT | MUX_MODE0)           /* uart1_ctsn.uart1_ctsn */
 197                         0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
 198                         0x180 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart1_rxd.uart1_rxd */
 199                         0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
 200                 >;
 201         };
 202
 203         clkout2_pin: pinmux_clkout2_pin {
 204                 pinctrl-single,pins = <
 205                         0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
 206                 >;
 207         };
 208
 209         nandflash_pins_s0: nandflash_pins_s0 {
 210                 pinctrl-single,pins = <
 211                         0x0 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad0.gpmc_ad0 */
 212                         0x4 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad1.gpmc_ad1 */
 213                         0x8 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad2.gpmc_ad2 */
 214                         0xc (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad3.gpmc_ad3 */
 215                         0x10 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
 216                         0x14 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
 217                         0x18 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
 218                         0x1c (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
 219                         0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
 220                         0x74 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_wpn.gpio0_30 */
 221                         0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
 222                         0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
 223                         0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 224                         0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 225                         0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 226                 >;
 227         };
 228
 229         ecap0_pins: backlight_pins {
 230                 pinctrl-single,pins = <
 231                         0x164 0x0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 232                 >;
 233         };
 234
 235         cpsw_default: cpsw_default {
 236                 pinctrl-single,pins = <
 237                         /* Slave 1 */
 238                         0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
 239                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
 240                         0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
 241                         0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
 242                         0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
 243                         0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
 244                         0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
 245                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
 246                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
 247                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
 248                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
 249                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
 250                 >;
 251         };
 252
 253         cpsw_sleep: cpsw_sleep {
 254                 pinctrl-single,pins = <
 255                         /* Slave 1 reset value */
 256                         0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 257                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 258                         0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 259                         0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 260                         0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 261                         0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 262                         0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 263                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 264                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 265                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 266                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 267                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 268                 >;
 269         };
 270
 271         davinci_mdio_default: davinci_mdio_default {
 272                 pinctrl-single,pins = <
 273                         /* MDIO */
 274                         0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
 275                         0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
 276                 >;
 277         };
 278
 279         davinci_mdio_sleep: davinci_mdio_sleep {
 280                 pinctrl-single,pins = <
 281                         /* MDIO reset value */
 282                         0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 283                         0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 284                 >;
 285         };
 286
 287         mmc1_pins: pinmux_mmc1_pins {
 288                 pinctrl-single,pins = <
 289                         0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 290                 >;
 291         };
 292
 293         mmc3_pins: pinmux_mmc3_pins {
 294                 pinctrl-single,pins = <
 295                         0x44 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
 296                         0x48 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
 297                         0x4C (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
 298                         0x78 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
 299                         0x88 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
 300                         0x8C (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
 301                 >;
 302         };
 303
 304         wlan_pins: pinmux_wlan_pins {
 305                 pinctrl-single,pins = <
 306                         0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a0.gpio1_16 */
 307                         0x19C (PIN_INPUT | MUX_MODE7)           /* mcasp0_ahclkr.gpio3_17 */
 308                         0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
 309                 >;
 310         };
 311
 312         lcd_pins_s0: lcd_pins_s0 {
 313                 pinctrl-single,pins = <
 314                         0x20 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad8.lcd_data23 */
 315                         0x24 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad9.lcd_data22 */
 316                         0x28 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad10.lcd_data21 */
 317                         0x2c (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad11.lcd_data20 */
 318                         0x30 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad12.lcd_data19 */
 319                         0x34 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad13.lcd_data18 */
 320                         0x38 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad14.lcd_data17 */
 321                         0x3c (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad15.lcd_data16 */
 322                         0xa0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data0.lcd_data0 */
 323                         0xa4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data1.lcd_data1 */
 324                         0xa8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data2.lcd_data2 */
 325                         0xac (PIN_OUTPUT | MUX_MODE0)           /* lcd_data3.lcd_data3 */
 326                         0xb0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data4.lcd_data4 */
 327                         0xb4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data5.lcd_data5 */
 328                         0xb8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data6.lcd_data6 */
 329                         0xbc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data7.lcd_data7 */
 330                         0xc0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data8.lcd_data8 */
 331                         0xc4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data9.lcd_data9 */
 332                         0xc8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data10.lcd_data10 */
 333                         0xcc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data11.lcd_data11 */
 334                         0xd0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data12.lcd_data12 */
 335                         0xd4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data13.lcd_data13 */
 336                         0xd8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data14.lcd_data14 */
 337                         0xdc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data15.lcd_data15 */
 338                         0xe0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_vsync.lcd_vsync */
 339                         0xe4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_hsync.lcd_hsync */
 340                         0xe8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_pclk.lcd_pclk */
 341                         0xec (PIN_OUTPUT | MUX_MODE0)           /* lcd_ac_bias_en.lcd_ac_bias_en */
 342                 >;
 343         };
 344
 345         am335x_evm_audio_pins: am335x_evm_audio_pins {
 346                 pinctrl-single,pins = <
 347                         0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
 348                         0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
 349                         0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
 350                         0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
 351                 >;
 352         };
 353
 354         dcan1_pins_default: dcan1_pins_default {
 355                 pinctrl-single,pins = <
 356                         0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
 357                         0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
 358                 >;
 359         };
 360 };
 361
 362 &uart0 {
 363         pinctrl-names = "default";
 364         pinctrl-0 = <&uart0_pins>;
 365
 366         status = "okay";
 367 };
 368
 369 &uart1 {
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&uart1_pins>;
 372
 373         status = "okay";
 374 };
 375
 376 &i2c0 {
 377         pinctrl-names = "default";
 378         pinctrl-0 = <&i2c0_pins>;
 379
 380         status = "okay";
 381         clock-frequency = <400000>;
 382
 383         tps: tps@2d {
 384                 reg = <0x2d>;
 385         };
 386 };
 387
 388 &usb {
 389         status = "okay";
 390 };
 391
 392 &usb_ctrl_mod {
 393         status = "okay";
 394 };
 395
 396 &usb0_phy {
 397         status = "okay";
 398 };
 399
 400 &usb1_phy {
 401         status = "okay";
 402 };
 403
 404 &usb0 {
 405         status = "okay";
 406 };
 407
 408 &usb1 {
 409         status = "okay";
 410         dr_mode = "host";
 411 };
 412
 413 &cppi41dma  {
 414         status = "okay";
 415 };
 416
 417 &i2c1 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&i2c1_pins>;
 420
 421         status = "okay";
 422         clock-frequency = <100000>;
 423
 424         lis331dlh: lis331dlh@18 {
 425                 compatible = "st,lis331dlh", "st,lis3lv02d";
 426                 reg = <0x18>;
 427                 Vdd-supply = <&lis3_reg>;
 428                 Vdd_IO-supply = <&lis3_reg>;
 429
 430                 st,click-single-x;
 431                 st,click-single-y;
 432                 st,click-single-z;
 433                 st,click-thresh-x = <10>;
 434                 st,click-thresh-y = <10>;
 435                 st,click-thresh-z = <10>;
 436                 st,irq1-click;
 437                 st,irq2-click;
 438                 st,wakeup-x-lo;
 439                 st,wakeup-x-hi;
 440                 st,wakeup-y-lo;
 441                 st,wakeup-y-hi;
 442                 st,wakeup-z-lo;
 443                 st,wakeup-z-hi;
 444                 st,min-limit-x = <120>;
 445                 st,min-limit-y = <120>;
 446                 st,min-limit-z = <140>;
 447                 st,max-limit-x = <550>;
 448                 st,max-limit-y = <550>;
 449                 st,max-limit-z = <750>;
 450         };
 451
 452         tsl2550: tsl2550@39 {
 453                 compatible = "taos,tsl2550";
 454                 reg = <0x39>;
 455         };
 456
 457         tmp275: tmp275@48 {
 458                 compatible = "ti,tmp275";
 459                 reg = <0x48>;
 460         };
 461
 462         tlv320aic3106: tlv320aic3106@1b {
 463                 compatible = "ti,tlv320aic3106";
 464                 reg = <0x1b>;
 465                 status = "okay";
 466
 467                 /* Regulators */
 468                 AVDD-supply = <&vaux2_reg>;
 469                 IOVDD-supply = <&vaux2_reg>;
 470                 DRVDD-supply = <&vaux2_reg>;
 471                 DVDD-supply = <&vbat>;
 472         };
 473 };
 474
 475 &lcdc {
 476         status = "okay";
 477 };
 478
 479 &elm {
 480         status = "okay";
 481 };
 482
 483 &epwmss0 {
 484         status = "okay";
 485
 486         ecap0: ecap@48300100 {
 487                 status = "okay";
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&ecap0_pins>;
 490         };
 491 };
 492
 493 &gpmc {
 494         status = "okay";
 495         pinctrl-names = "default";
 496         pinctrl-0 = <&nandflash_pins_s0>;
 497         ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
 498         nand@0,0 {
 499                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 500                 ti,nand-ecc-opt = "bch8";
 501                 ti,elm-id = <&elm>;
 502                 nand-bus-width = <8>;
 503                 gpmc,device-width = <1>;
 504                 gpmc,sync-clk-ps = <0>;
 505                 gpmc,cs-on-ns = <0>;
 506                 gpmc,cs-rd-off-ns = <44>;
 507                 gpmc,cs-wr-off-ns = <44>;
 508                 gpmc,adv-on-ns = <6>;
 509                 gpmc,adv-rd-off-ns = <34>;
 510                 gpmc,adv-wr-off-ns = <44>;
 511                 gpmc,we-on-ns = <0>;
 512                 gpmc,we-off-ns = <40>;
 513                 gpmc,oe-on-ns = <0>;
 514                 gpmc,oe-off-ns = <54>;
 515                 gpmc,access-ns = <64>;
 516                 gpmc,rd-cycle-ns = <82>;
 517                 gpmc,wr-cycle-ns = <82>;
 518                 gpmc,wait-on-read = "true";
 519                 gpmc,wait-on-write = "true";
 520                 gpmc,bus-turnaround-ns = <0>;
 521                 gpmc,cycle2cycle-delay-ns = <0>;
 522                 gpmc,clk-activation-ns = <0>;
 523                 gpmc,wait-monitoring-ns = <0>;
 524                 gpmc,wr-access-ns = <40>;
 525                 gpmc,wr-data-mux-bus-ns = <0>;
 526                 /* MTD partition table */
 527                 /* All SPL-* partitions are sized to minimal length
 528                  * which can be independently programmable. For
 529                  * NAND flash this is equal to size of erase-block */
 530                 #address-cells = <1>;
 531                 #size-cells = <1>;
 532                 partition@0 {
 533                         label = "NAND.SPL";
 534                         reg = <0x00000000 0x000020000>;
 535                 };
 536                 partition@1 {
 537                         label = "NAND.SPL.backup1";
 538                         reg = <0x00020000 0x00020000>;
 539                 };
 540                 partition@2 {
 541                         label = "NAND.SPL.backup2";
 542                         reg = <0x00040000 0x00020000>;
 543                 };
 544                 partition@3 {
 545                         label = "NAND.SPL.backup3";
 546                         reg = <0x00060000 0x00020000>;
 547                 };
 548                 partition@4 {
 549                         label = "NAND.u-boot-spl-os";
 550                         reg = <0x00080000 0x00040000>;
 551                 };
 552                 partition@5 {
 553                         label = "NAND.u-boot";
 554                         reg = <0x000C0000 0x00100000>;
 555                 };
 556                 partition@6 {
 557                         label = "NAND.u-boot-env";
 558                         reg = <0x001C0000 0x00020000>;
 559                 };
 560                 partition@7 {
 561                         label = "NAND.u-boot-env.backup1";
 562                         reg = <0x001E0000 0x00020000>;
 563                 };
 564                 partition@8 {
 565                         label = "NAND.kernel";
 566                         reg = <0x00200000 0x00800000>;
 567                 };
 568                 partition@9 {
 569                         label = "NAND.file-system";
 570                         reg = <0x00A00000 0x0F600000>;
 571                 };
 572         };
 573 };
 574
 575 #include "tps65910.dtsi"
 576
 577 &mcasp1 {
 578                 pinctrl-names = "default";
 579                 pinctrl-0 = <&am335x_evm_audio_pins>;
 580
 581                 status = "okay";
 582
 583                 op-mode = <0>;          /* MCASP_IIS_MODE */
 584                 tdm-slots = <2>;
 585                 /* 4 serializers */
 586                 serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 587                         0 0 1 2
 588                 >;
 589                 tx-num-evt = <32>;
 590                 rx-num-evt = <32>;
 591 };
 592
 593 &tps {
 594         vcc1-supply = <&vbat>;
 595         vcc2-supply = <&vbat>;
 596         vcc3-supply = <&vbat>;
 597         vcc4-supply = <&vbat>;
 598         vcc5-supply = <&vbat>;
 599         vcc6-supply = <&vbat>;
 600         vcc7-supply = <&vbat>;
 601         vccio-supply = <&vbat>;
 602
 603         regulators {
 604                 vrtc_reg: regulator@0 {
 605                         regulator-always-on;
 606                 };
 607
 608                 vio_reg: regulator@1 {
 609                         regulator-always-on;
 610                 };
 611
 612                 vdd1_reg: regulator@2 {
 613                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 614                         regulator-name = "vdd_mpu";
 615                         regulator-min-microvolt = <912500>;
 616                         regulator-max-microvolt = <1312500>;
 617                         regulator-boot-on;
 618                         regulator-always-on;
 619                 };
 620
 621                 vdd2_reg: regulator@3 {
 622                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 623                         regulator-name = "vdd_core";
 624                         regulator-min-microvolt = <912500>;
 625                         regulator-max-microvolt = <1150000>;
 626                         regulator-boot-on;
 627                         regulator-always-on;
 628                 };
 629
 630                 vdd3_reg: regulator@4 {
 631                         regulator-always-on;
 632                 };
 633
 634                 vdig1_reg: regulator@5 {
 635                         regulator-always-on;
 636                 };
 637
 638                 vdig2_reg: regulator@6 {
 639                         regulator-always-on;
 640                 };
 641
 642                 vpll_reg: regulator@7 {
 643                         regulator-always-on;
 644                 };
 645
 646                 vdac_reg: regulator@8 {
 647                         regulator-always-on;
 648                 };
 649
 650                 vaux1_reg: regulator@9 {
 651                         regulator-always-on;
 652                 };
 653
 654                 vaux2_reg: regulator@10 {
 655                         regulator-always-on;
 656                 };
 657
 658                 vaux33_reg: regulator@11 {
 659                         regulator-always-on;
 660                 };
 661
 662                 vmmc_reg: regulator@12 {
 663                         regulator-min-microvolt = <1800000>;
 664                         regulator-max-microvolt = <3300000>;
 665                         regulator-always-on;
 666                 };
 667         };
 668 };
 669
 670 &mac {
 671         pinctrl-names = "default", "sleep";
 672         pinctrl-0 = <&cpsw_default>;
 673         pinctrl-1 = <&cpsw_sleep>;
 674         status = "okay";
 675 };
 676
 677 &davinci_mdio {
 678         pinctrl-names = "default", "sleep";
 679         pinctrl-0 = <&davinci_mdio_default>;
 680         pinctrl-1 = <&davinci_mdio_sleep>;
 681         status = "okay";
 682 };
 683
 684 &cpsw_emac0 {
 685         phy_id = <&davinci_mdio>, <0>;
 686         phy-mode = "rgmii-txid";
 687 };
 688
 689 &cpsw_emac1 {
 690         phy_id = <&davinci_mdio>, <1>;
 691         phy-mode = "rgmii-txid";
 692 };
 693
 694 &tscadc {
 695         status = "okay";
 696         tsc {
 697                 ti,wires = <4>;
 698                 ti,x-plate-resistance = <200>;
 699                 ti,coordinate-readouts = <5>;
 700                 ti,wire-config = <0x00 0x11 0x22 0x33>;
 701                 ti,charge-delay = <0x400>;
 702         };
 703
 704         adc {
 705                 ti,adc-channels = <4 5 6 7>;
 706         };
 707 };
 708
 709 &mmc1 {
 710         status = "okay";
 711         vmmc-supply = <&vmmc_reg>;
 712         bus-width = <4>;
 713         pinctrl-names = "default";
 714         pinctrl-0 = <&mmc1_pins>;
 715         cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 716 };
 717
 718 &mmc3 {
 719         /* these are on the crossbar and are outlined in the
 720            xbar-event-map element */
 721         dmas = <&edma 12
 722                 &edma 13>;
 723         dma-names = "tx", "rx";
 724         status = "okay";
 725         vmmc-supply = <&wlan_en_reg>;
 726         bus-width = <4>;
 727         pinctrl-names = "default";
 728         pinctrl-0 = <&mmc3_pins &wlan_pins>;
 729         ti,non-removable;
 730         ti,needs-special-hs-handling;
 731         cap-power-off-card;
 732         keep-power-in-suspend;
 733
 734         #address-cells = <1>;
 735         #size-cells = <0>;
 736         wlcore: wlcore@0 {
 737                 compatible = "ti,wl1835";
 738                 reg = <2>;
 739                 interrupt-parent = <&gpio3>;
 740                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
 741         };
 742 };
 743
 744 &edma {
 745         ti,edma-xbar-event-map = /bits/ 16 <1 12
 746                                             2 13>;
 747 };
 748
 749 &sham {
 750         status = "okay";
 751 };
 752
 753 &aes {
 754         status = "okay";
 755 };
 756
 757 &dcan1 {
 758         status = "disabled";    /* Enable only if Profile 1 is selected */
 759         pinctrl-names = "default";
 760         pinctrl-0 = <&dcan1_pins_default>;
 761 };