arch/arm/boot/dts/am43x-epos-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM43x EPOS EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pwm/pwm.h>
  17
  18 / {
  19         model = "TI AM43x EPOS EVM";
  20         compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
  21
  22         aliases {
  23                 display0 = &lcd0;
  24         };
  25
  26         vmmcsd_fixed: fixedregulator-sd {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "vmmcsd_fixed";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31                 enable-active-high;
  32         };
  33
  34         lcd0: display {
  35                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  36                 label = "lcd";
  37
  38                 pinctrl-names = "default";
  39                 pinctrl-0 = <&lcd_pins>;
  40
  41                 /*
  42                  * SelLCDorHDMI, LOW to select HDMI. This is not really the
  43                  * panel's enable GPIO, but we don't have HDMI driver support nor
  44                  * support to switch between two displays, so using this gpio as
  45                  * panel's enable should be safe.
  46                  */
  47                 enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
  48
  49                 panel-timing {
  50                         clock-frequency = <33000000>;
  51                         hactive = <800>;
  52                         vactive = <480>;
  53                         hfront-porch = <210>;
  54                         hback-porch = <16>;
  55                         hsync-len = <30>;
  56                         vback-porch = <10>;
  57                         vfront-porch = <22>;
  58                         vsync-len = <13>;
  59                         hsync-active = <0>;
  60                         vsync-active = <0>;
  61                         de-active = <1>;
  62                         pixelclk-active = <1>;
  63                 };
  64
  65                 port {
  66                         lcd_in: endpoint {
  67                                 remote-endpoint = <&dpi_out>;
  68                         };
  69                 };
  70         };
  71
  72         matrix_keypad: matrix_keypad@0 {
  73                 compatible = "gpio-matrix-keypad";
  74                 debounce-delay-ms = <5>;
  75                 col-scan-delay-us = <2>;
  76
  77                 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
  78                              &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
  79                              &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
  80                              &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
  81
  82                 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
  83                              &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
  84                              &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
  85                              &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
  86
  87                 linux,keymap = <0x00000201      /* P1 */
  88                         0x01000204      /* P4 */
  89                         0x02000207      /* P7 */
  90                         0x0300020a      /* NUMERIC_STAR */
  91                         0x00010202      /* P2 */
  92                         0x01010205      /* P5 */
  93                         0x02010208      /* P8 */
  94                         0x03010200      /* P0 */
  95                         0x00020203      /* P3 */
  96                         0x01020206      /* P6 */
  97                         0x02020209      /* P9 */
  98                         0x0302020b      /* NUMERIC_POUND */
  99                         0x00030067      /* UP */
 100                         0x0103006a      /* RIGHT */
 101                         0x0203006c      /* DOWN */
 102                         0x03030069>;    /* LEFT */
 103         };
 104
 105         backlight {
 106                 compatible = "pwm-backlight";
 107                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
 108                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
 109                 default-brightness-level = <8>;
 110         };
 111 };
 112
 113 &am43xx_pinmux {
 114                 cpsw_default: cpsw_default {
 115                         pinctrl-single,pins = <
 116                                 /* Slave 1 */
 117                                 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
 118                                 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxerr.rmii1_rxerr */
 119                                 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
 120                                 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxdv.rmii1_rxdv */
 121                                 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
 122                                 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
 123                                 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd1.rmii1_rxd1 */
 124                                 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd0.rmii1_rxd0 */
 125                                 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_refclk.rmii1_refclk */
 126                         >;
 127                 };
 128
 129                 cpsw_sleep: cpsw_sleep {
 130                         pinctrl-single,pins = <
 131                                 /* Slave 1 reset value */
 132                                 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 133                                 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 134                                 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 135                                 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 136                                 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 137                                 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 138                                 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 139                                 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 140                                 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 141                         >;
 142                 };
 143
 144                 davinci_mdio_default: davinci_mdio_default {
 145                         pinctrl-single,pins = <
 146                                 /* MDIO */
 147                                 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
 148                                 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
 149                         >;
 150                 };
 151
 152                 davinci_mdio_sleep: davinci_mdio_sleep {
 153                         pinctrl-single,pins = <
 154                                 /* MDIO reset value */
 155                                 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 156                                 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 157                         >;
 158                 };
 159
 160                 i2c0_pins: pinmux_i2c0_pins {
 161                         pinctrl-single,pins = <
 162                                 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
 163                                 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
 164                         >;
 165                 };
 166
 167                 nand_flash_x8: nand_flash_x8 {
 168                         pinctrl-single,pins = <
 169                                 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a0.SELQSPIorNAND/GPIO */
 170                                 0x0  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
 171                                 0x4  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
 172                                 0x8  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
 173                                 0xc  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
 174                                 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
 175                                 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
 176                                 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
 177                                 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
 178                                 0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
 179                                 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
 180                                 0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
 181                                 0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
 182                                 0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 183                                 0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 184                                 0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 185                         >;
 186                 };
 187
 188                 ecap0_pins: backlight_pins {
 189                         pinctrl-single,pins = <
 190                                 0x164 MUX_MODE0         /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 191                         >;
 192                 };
 193
 194                 i2c2_pins: pinmux_i2c2_pins {
 195                         pinctrl-single,pins = <
 196                                 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_sda.i2c2_sda */
 197                                 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_scl.i2c2_scl */
 198                         >;
 199                 };
 200
 201                 spi0_pins: pinmux_spi0_pins {
 202                         pinctrl-single,pins = <
 203                                 0x150 (PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
 204                                 0x154 (PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
 205                                 0x158 (PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
 206                                 0x15c (PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
 207                         >;
 208                 };
 209
 210                 spi1_pins: pinmux_spi1_pins {
 211                         pinctrl-single,pins = <
 212                                 0x190 (PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
 213                                 0x194 (PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
 214                                 0x198 (PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
 215                                 0x19c (PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
 216                         >;
 217                 };
 218
 219                 mmc1_pins: pinmux_mmc1_pins {
 220                         pinctrl-single,pins = <
 221                                 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 222                         >;
 223                 };
 224
 225                 qspi1_default: qspi1_default {
 226                         pinctrl-single,pins = <
 227                                 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
 228                                 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
 229                                 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
 230                                 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
 231                                 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
 232                                 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
 233                         >;
 234                 };
 235
 236                 pixcir_ts_pins: pixcir_ts_pins {
 237                         pinctrl-single,pins = <
 238                                 0x44 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_a1.gpio1_17 */
 239                         >;
 240                 };
 241
 242                 hdq_pins: pinmux_hdq_pins {
 243                         pinctrl-single,pins = <
 244                                 0x234 (PIN_INPUT_PULLUP | MUX_MODE1)    /* cam1_wen.hdq_gpio */
 245                         >;
 246                 };
 247
 248                 dss_pins: dss_pins {
 249                         pinctrl-single,pins = <
 250                                 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 251                                 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 252                                 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 253                                 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
 254                                 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 255                                 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 256                                 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 257                                 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 258                                 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 259                                 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 260                                 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 261                                 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
 262                                 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 263                                 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 264                                 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 265                                 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
 266                                 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 267                                 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 268                                 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 269                                 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
 270                                 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 271                                 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 272                                 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 273                                 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 274                                 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 275                                 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 276                                 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 277                                 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 278                         >;
 279                 };
 280
 281                 lcd_pins: lcd_pins {
 282                         pinctrl-single,pins = <
 283                                 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
 284                                 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
 285                         >;
 286                 };
 287
 288                 vpfe1_pins_default: vpfe1_pins_default {
 289                         pinctrl-single,pins = <
 290                                 0x1cc (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0 */
 291                                 0x1d0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0 */
 292                                 0x1d4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0 */
 293                                 0x1d8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0 */
 294                                 0x1dc (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0 */
 295                                 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0 */
 296                                 0x1ec (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0 */
 297                                 0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0 */
 298                                 0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0 */
 299                                 0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0 */
 300                                 0x1fc (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0 */
 301                                 0x200 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0 */
 302                                 0x204 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0 */
 303                         >;
 304                 };
 305
 306                 vpfe1_pins_sleep: vpfe1_pins_sleep {
 307                         pinctrl-single,pins = <
 308                                 0x1cc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 309                                 0x1d0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 310                                 0x1d4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 311                                 0x1d8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 312                                 0x1dc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 313                                 0x1e8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 314                                 0x1ec (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 315                                 0x1f0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 316                                 0x1f4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 317                                 0x1f8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 318                                 0x1fc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 319                                 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 320                                 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 321                         >;
 322                 };
 323 };
 324
 325 &mmc1 {
 326         status = "okay";
 327         vmmc-supply = <&vmmcsd_fixed>;
 328         bus-width = <4>;
 329         pinctrl-names = "default";
 330         pinctrl-0 = <&mmc1_pins>;
 331         cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 332 };
 333
 334 &mac {
 335         pinctrl-names = "default", "sleep";
 336         pinctrl-0 = <&cpsw_default>;
 337         pinctrl-1 = <&cpsw_sleep>;
 338         status = "okay";
 339 };
 340
 341 &davinci_mdio {
 342         pinctrl-names = "default", "sleep";
 343         pinctrl-0 = <&davinci_mdio_default>;
 344         pinctrl-1 = <&davinci_mdio_sleep>;
 345         status = "okay";
 346 };
 347
 348 &cpsw_emac0 {
 349         phy_id = <&davinci_mdio>, <16>;
 350         phy-mode = "rmii";
 351 };
 352
 353 &cpsw_emac1 {
 354         phy_id = <&davinci_mdio>, <1>;
 355         phy-mode = "rmii";
 356 };
 357
 358 &phy_sel {
 359         rmii-clock-ext;
 360 };
 361
 362 &i2c0 {
 363         status = "okay";
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&i2c0_pins>;
 366         clock-frequency = <400000>;
 367
 368         tps65218: tps65218@24 {
 369                 reg = <0x24>;
 370                 compatible = "ti,tps65218";
 371                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
 372                 interrupt-controller;
 373                 #interrupt-cells = <2>;
 374
 375                 dcdc1: regulator-dcdc1 {
 376                         compatible = "ti,tps65218-dcdc1";
 377                         regulator-name = "vdd_core";
 378                         regulator-min-microvolt = <912000>;
 379                         regulator-max-microvolt = <1144000>;
 380                         regulator-boot-on;
 381                         regulator-always-on;
 382                 };
 383
 384                 dcdc2: regulator-dcdc2 {
 385                         compatible = "ti,tps65218-dcdc2";
 386                         regulator-name = "vdd_mpu";
 387                         regulator-min-microvolt = <912000>;
 388                         regulator-max-microvolt = <1378000>;
 389                         regulator-boot-on;
 390                         regulator-always-on;
 391                 };
 392
 393                 dcdc3: regulator-dcdc3 {
 394                         compatible = "ti,tps65218-dcdc3";
 395                         regulator-name = "vdcdc3";
 396                         regulator-min-microvolt = <1500000>;
 397                         regulator-max-microvolt = <1500000>;
 398                         regulator-boot-on;
 399                         regulator-always-on;
 400                 };
 401
 402                 dcdc5: regulator-dcdc5 {
 403                         compatible = "ti,tps65218-dcdc5";
 404                         regulator-name = "v1_0bat";
 405                         regulator-min-microvolt = <1000000>;
 406                         regulator-max-microvolt = <1000000>;
 407                 };
 408
 409                 dcdc6: regulator-dcdc6 {
 410                         compatible = "ti,tps65218-dcdc6";
 411                         regulator-name = "v1_8bat";
 412                         regulator-min-microvolt = <1800000>;
 413                         regulator-max-microvolt = <1800000>;
 414                 };
 415
 416                 ldo1: regulator-ldo1 {
 417                         compatible = "ti,tps65218-ldo1";
 418                         regulator-min-microvolt = <1800000>;
 419                         regulator-max-microvolt = <1800000>;
 420                         regulator-boot-on;
 421                         regulator-always-on;
 422                 };
 423         };
 424
 425         at24@50 {
 426                 compatible = "at24,24c256";
 427                 pagesize = <64>;
 428                 reg = <0x50>;
 429         };
 430
 431         pixcir_ts@5c {
 432                 compatible = "pixcir,pixcir_tangoc";
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&pixcir_ts_pins>;
 435                 reg = <0x5c>;
 436                 interrupt-parent = <&gpio1>;
 437                 interrupts = <17 0>;
 438
 439                 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
 440
 441                 touchscreen-size-x = <1024>;
 442                 touchscreen-size-y = <600>;
 443         };
 444 };
 445
 446 &i2c2 {
 447         pinctrl-names = "default";
 448         pinctrl-0 = <&i2c2_pins>;
 449         status = "okay";
 450 };
 451
 452 &gpio0 {
 453         status = "okay";
 454 };
 455
 456 &gpio1 {
 457         status = "okay";
 458 };
 459
 460 &gpio2 {
 461         status = "okay";
 462 };
 463
 464 &gpio3 {
 465         status = "okay";
 466 };
 467
 468 &elm {
 469         status = "okay";
 470 };
 471
 472 &gpmc {
 473         status = "okay";        /* Disable QSPI when enabling GPMC (NAND) */
 474         pinctrl-names = "default";
 475         pinctrl-0 = <&nand_flash_x8>;
 476         ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
 477         nand@0,0 {
 478                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 479                 ti,nand-ecc-opt = "bch16";
 480                 ti,elm-id = <&elm>;
 481                 nand-bus-width = <8>;
 482                 gpmc,device-width = <1>;
 483                 gpmc,sync-clk-ps = <0>;
 484                 gpmc,cs-on-ns = <0>;
 485                 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
 486                 gpmc,cs-wr-off-ns = <40>;
 487                 gpmc,adv-on-ns = <0>;  /* cs-on-ns */
 488                 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
 489                 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
 490                 gpmc,we-on-ns = <0>;   /* cs-on-ns */
 491                 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
 492                 gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
 493                 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
 494                 gpmc,access-ns = <30>; /* tCEA + 4*/
 495                 gpmc,rd-cycle-ns = <40>;
 496                 gpmc,wr-cycle-ns = <40>;
 497                 gpmc,wait-pin = <0>;
 498                 gpmc,bus-turnaround-ns = <0>;
 499                 gpmc,cycle2cycle-delay-ns = <0>;
 500                 gpmc,clk-activation-ns = <0>;
 501                 gpmc,wait-monitoring-ns = <0>;
 502                 gpmc,wr-access-ns = <40>;
 503                 gpmc,wr-data-mux-bus-ns = <0>;
 504                 /* MTD partition table */
 505                 /* All SPL-* partitions are sized to minimal length
 506                  * which can be independently programmable. For
 507                  * NAND flash this is equal to size of erase-block */
 508                 #address-cells = <1>;
 509                 #size-cells = <1>;
 510                 partition@0 {
 511                         label = "NAND.SPL";
 512                         reg = <0x00000000 0x00040000>;
 513                 };
 514                 partition@1 {
 515                         label = "NAND.SPL.backup1";
 516                         reg = <0x00040000 0x00040000>;
 517                 };
 518                 partition@2 {
 519                         label = "NAND.SPL.backup2";
 520                         reg = <0x00080000 0x00040000>;
 521                 };
 522                 partition@3 {
 523                         label = "NAND.SPL.backup3";
 524                         reg = <0x000C0000 0x00040000>;
 525                 };
 526                 partition@4 {
 527                         label = "NAND.u-boot-spl-os";
 528                         reg = <0x00100000 0x00080000>;
 529                 };
 530                 partition@5 {
 531                         label = "NAND.u-boot";
 532                         reg = <0x00180000 0x00100000>;
 533                 };
 534                 partition@6 {
 535                         label = "NAND.u-boot-env";
 536                         reg = <0x00280000 0x00040000>;
 537                 };
 538                 partition@7 {
 539                         label = "NAND.u-boot-env.backup1";
 540                         reg = <0x002C0000 0x00040000>;
 541                 };
 542                 partition@8 {
 543                         label = "NAND.kernel";
 544                         reg = <0x00300000 0x00700000>;
 545                 };
 546                 partition@9 {
 547                         label = "NAND.file-system";
 548                         reg = <0x00a00000 0x1f600000>;
 549                 };
 550         };
 551 };
 552
 553 &epwmss0 {
 554         status = "okay";
 555 };
 556
 557 &tscadc {
 558         status = "okay";
 559
 560         adc {
 561                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 562         };
 563 };
 564
 565 &ecap0 {
 566                 status = "okay";
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&ecap0_pins>;
 569 };
 570
 571 &spi0 {
 572         pinctrl-names = "default";
 573         pinctrl-0 = <&spi0_pins>;
 574         status = "okay";
 575 };
 576
 577 &spi1 {
 578         pinctrl-names = "default";
 579         pinctrl-0 = <&spi1_pins>;
 580         status = "okay";
 581 };
 582
 583 &usb2_phy1 {
 584         status = "okay";
 585 };
 586
 587 &usb1 {
 588         dr_mode = "peripheral";
 589         status = "okay";
 590 };
 591
 592 &usb2_phy2 {
 593         status = "okay";
 594 };
 595
 596 &usb2 {
 597         dr_mode = "host";
 598         status = "okay";
 599 };
 600
 601 &qspi {
 602         status = "disabled";    /* Disable GPMC (NAND) when enabling QSPI */
 603         pinctrl-names = "default";
 604         pinctrl-0 = <&qspi1_default>;
 605
 606         spi-max-frequency = <48000000>;
 607         m25p80@0 {
 608                 compatible = "mx66l51235l";
 609                 spi-max-frequency = <48000000>;
 610                 reg = <0>;
 611                 spi-cpol;
 612                 spi-cpha;
 613                 spi-tx-bus-width = <1>;
 614                 spi-rx-bus-width = <4>;
 615                 #address-cells = <1>;
 616                 #size-cells = <1>;
 617
 618                 /* MTD partition table.
 619                  * The ROM checks the first 512KiB
 620                  * for a valid file to boot(XIP).
 621                  */
 622                 partition@0 {
 623                         label = "QSPI.U_BOOT";
 624                         reg = <0x00000000 0x000080000>;
 625                 };
 626                 partition@1 {
 627                         label = "QSPI.U_BOOT.backup";
 628                         reg = <0x00080000 0x00080000>;
 629                 };
 630                 partition@2 {
 631                         label = "QSPI.U-BOOT-SPL_OS";
 632                         reg = <0x00100000 0x00010000>;
 633                 };
 634                 partition@3 {
 635                         label = "QSPI.U_BOOT_ENV";
 636                         reg = <0x00110000 0x00010000>;
 637                 };
 638                 partition@4 {
 639                         label = "QSPI.U-BOOT-ENV.backup";
 640                         reg = <0x00120000 0x00010000>;
 641                 };
 642                 partition@5 {
 643                         label = "QSPI.KERNEL";
 644                         reg = <0x00130000 0x0800000>;
 645                 };
 646                 partition@6 {
 647                         label = "QSPI.FILESYSTEM";
 648                         reg = <0x00930000 0x36D0000>;
 649                 };
 650         };
 651 };
 652
 653 &hdq {
 654         status = "okay";
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&hdq_pins>;
 657 };
 658
 659 &dss {
 660         status = "ok";
 661
 662         pinctrl-names = "default";
 663         pinctrl-0 = <&dss_pins>;
 664
 665         port {
 666                 dpi_out: endpoint@0 {
 667                         remote-endpoint = <&lcd_in>;
 668                         data-lines = <24>;
 669                 };
 670         };
 671 };
 672
 673 &vpfe1 {
 674         status = "okay";
 675         pinctrl-names = "default", "sleep";
 676         pinctrl-0 = <&vpfe1_pins_default>;
 677         pinctrl-1 = <&vpfe1_pins_sleep>;
 678
 679         port {
 680                 vpfe1_ep: endpoint {
 681                         /* remote-endpoint = <&sensor>; add once we have it */
 682                         ti,am437x-vpfe-interface = <0>;
 683                         bus-width = <8>;
 684                         hsync-active = <0>;
 685                         vsync-active = <0>;
 686                 };
 687         };
 688 };