| blob | b6c8df8d380ea41c9ed9807fb15dd4708d23a913 |
1 /*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
12 #include "skeleton.dtsi"
13 #include <dt-bindings/dma/at91.h>
14 #include <dt-bindings/pinctrl/at91.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/at91.h>
19 / {
20 model = "Atmel AT91SAM9x5 family SoC";
21 compatible = "atmel,at91sam9x5";
22 interrupt-parent = <&aic>;
24 aliases {
25 serial0 = &dbgu;
26 serial1 = &usart0;
27 serial2 = &usart1;
28 serial3 = &usart2;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 tcb0 = &tcb0;
34 tcb1 = &tcb1;
35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 pwm0 = &pwm0;
40 };
41 cpus {
42 #address-cells = <0>;
43 #size-cells = <0>;
45 cpu {
46 compatible = "arm,arm926ej-s";
47 device_type = "cpu";
48 };
49 };
51 memory {
52 reg = <0x20000000 0x10000000>;
53 };
55 clocks {
56 slow_xtal: slow_xtal {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <0>;
60 };
62 main_xtal: main_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
68 adc_op_clk: adc_op_clk{
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <5000000>;
72 };
73 };
75 sram: sram@00300000 {
76 compatible = "mmio-sram";
77 reg = <0x00300000 0x8000>;
78 };
80 ahb {
81 compatible = "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
86 apb {
87 compatible = "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
92 aic: interrupt-controller@fffff000 {
93 #interrupt-cells = <3>;
94 compatible = "atmel,at91rm9200-aic";
95 interrupt-controller;
96 reg = <0xfffff000 0x200>;
97 atmel,external-irqs = <31>;
98 };
100 ramc0: ramc@ffffe800 {
101 compatible = "atmel,at91sam9g45-ddramc";
102 reg = <0xffffe800 0x200>;
103 clocks = <&ddrck>;
104 clock-names = "ddrck";
105 };
107 pmc: pmc@fffffc00 {
108 compatible = "atmel,at91sam9x5-pmc";
109 reg = <0xfffffc00 0x100>;
110 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
111 interrupt-controller;
112 #address-cells = <1>;
113 #size-cells = <0>;
114 #interrupt-cells = <1>;
116 main_rc_osc: main_rc_osc {
117 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
118 #clock-cells = <0>;
119 interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
120 clock-frequency = <12000000>;
121 clock-accuracy = <50000000>;
122 };
124 main_osc: main_osc {
125 compatible = "atmel,at91rm9200-clk-main-osc";
126 #clock-cells = <0>;
127 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
128 clocks = <&main_xtal>;
129 };
131 main: mainck {
132 compatible = "atmel,at91sam9x5-clk-main";
133 #clock-cells = <0>;
134 interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
135 clocks = <&main_rc_osc>, <&main_osc>;
136 };
138 plla: pllack {
139 compatible = "atmel,at91rm9200-clk-pll";
140 #clock-cells = <0>;
141 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
142 clocks = <&main>;
143 reg = <0>;
144 atmel,clk-input-range = <2000000 32000000>;
145 #atmel,pll-clk-output-range-cells = <4>;
146 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
147 695000000 750000000 1 0
148 645000000 700000000 2 0
149 595000000 650000000 3 0
150 545000000 600000000 0 1
151 495000000 555000000 1 1
152 445000000 500000000 2 1
153 400000000 450000000 3 1>;
154 };
156 plladiv: plladivck {
157 compatible = "atmel,at91sam9x5-clk-plldiv";
158 #clock-cells = <0>;
159 clocks = <&plla>;
160 };
162 utmi: utmick {
163 compatible = "atmel,at91sam9x5-clk-utmi";
164 #clock-cells = <0>;
165 interrupts-extended = <&pmc AT91_PMC_LOCKU>;
166 clocks = <&main>;
167 };
169 mck: masterck {
170 compatible = "atmel,at91sam9x5-clk-master";
171 #clock-cells = <0>;
172 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
173 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
174 atmel,clk-output-range = <0 133333333>;
175 atmel,clk-divisors = <1 2 4 3>;
176 atmel,master-clk-have-div3-pres;
177 };
179 usb: usbck {
180 compatible = "atmel,at91sam9x5-clk-usb";
181 #clock-cells = <0>;
182 clocks = <&plladiv>, <&utmi>;
183 };
185 prog: progck {
186 compatible = "atmel,at91sam9x5-clk-programmable";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 interrupt-parent = <&pmc>;
190 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
192 prog0: prog0 {
193 #clock-cells = <0>;
194 reg = <0>;
195 interrupts = <AT91_PMC_PCKRDY(0)>;
196 };
198 prog1: prog1 {
199 #clock-cells = <0>;
200 reg = <1>;
201 interrupts = <AT91_PMC_PCKRDY(1)>;
202 };
203 };
205 smd: smdclk {
206 compatible = "atmel,at91sam9x5-clk-smd";
207 #clock-cells = <0>;
208 clocks = <&plladiv>, <&utmi>;
209 };
211 systemck {
212 compatible = "atmel,at91rm9200-clk-system";
213 #address-cells = <1>;
214 #size-cells = <0>;
216 ddrck: ddrck {
217 #clock-cells = <0>;
218 reg = <2>;
219 clocks = <&mck>;
220 };
222 smdck: smdck {
223 #clock-cells = <0>;
224 reg = <4>;
225 clocks = <&smd>;
226 };
228 uhpck: uhpck {
229 #clock-cells = <0>;
230 reg = <6>;
231 clocks = <&usb>;
232 };
234 udpck: udpck {
235 #clock-cells = <0>;
236 reg = <7>;
237 clocks = <&usb>;
238 };
240 pck0: pck0 {
241 #clock-cells = <0>;
242 reg = <8>;
243 clocks = <&prog0>;
244 };
246 pck1: pck1 {
247 #clock-cells = <0>;
248 reg = <9>;
249 clocks = <&prog1>;
250 };
251 };
253 periphck {
254 compatible = "atmel,at91sam9x5-clk-peripheral";
255 #address-cells = <1>;
256 #size-cells = <0>;
257 clocks = <&mck>;
259 pioAB_clk: pioAB_clk {
260 #clock-cells = <0>;
261 reg = <2>;
262 };
264 pioCD_clk: pioCD_clk {
265 #clock-cells = <0>;
266 reg = <3>;
267 };
269 smd_clk: smd_clk {
270 #clock-cells = <0>;
271 reg = <4>;
272 };
274 usart0_clk: usart0_clk {
275 #clock-cells = <0>;
276 reg = <5>;
277 };
279 usart1_clk: usart1_clk {
280 #clock-cells = <0>;
281 reg = <6>;
282 };
284 usart2_clk: usart2_clk {
285 #clock-cells = <0>;
286 reg = <7>;
287 };
289 twi0_clk: twi0_clk {
290 reg = <9>;
291 #clock-cells = <0>;
292 };
294 twi1_clk: twi1_clk {
295 #clock-cells = <0>;
296 reg = <10>;
297 };
299 twi2_clk: twi2_clk {
300 #clock-cells = <0>;
301 reg = <11>;
302 };
304 mci0_clk: mci0_clk {
305 #clock-cells = <0>;
306 reg = <12>;
307 };
309 spi0_clk: spi0_clk {
310 #clock-cells = <0>;
311 reg = <13>;
312 };
314 spi1_clk: spi1_clk {
315 #clock-cells = <0>;
316 reg = <14>;
317 };
319 uart0_clk: uart0_clk {
320 #clock-cells = <0>;
321 reg = <15>;
322 };
324 uart1_clk: uart1_clk {
325 #clock-cells = <0>;
326 reg = <16>;
327 };
329 tcb0_clk: tcb0_clk {
330 #clock-cells = <0>;
331 reg = <17>;
332 };
334 pwm_clk: pwm_clk {
335 #clock-cells = <0>;
336 reg = <18>;
337 };
339 adc_clk: adc_clk {
340 #clock-cells = <0>;
341 reg = <19>;
342 };
344 dma0_clk: dma0_clk {
345 #clock-cells = <0>;
346 reg = <20>;
347 };
349 dma1_clk: dma1_clk {
350 #clock-cells = <0>;
351 reg = <21>;
352 };
354 uhphs_clk: uhphs_clk {
355 #clock-cells = <0>;
356 reg = <22>;
357 };
359 udphs_clk: udphs_clk {
360 #clock-cells = <0>;
361 reg = <23>;
362 };
364 mci1_clk: mci1_clk {
365 #clock-cells = <0>;
366 reg = <26>;
367 };
369 ssc0_clk: ssc0_clk {
370 #clock-cells = <0>;
371 reg = <28>;
372 };
373 };
374 };
376 rstc@fffffe00 {
377 compatible = "atmel,at91sam9g45-rstc";
378 reg = <0xfffffe00 0x10>;
379 };
381 shdwc@fffffe10 {
382 compatible = "atmel,at91sam9x5-shdwc";
383 reg = <0xfffffe10 0x10>;
384 };
386 pit: timer@fffffe30 {
387 compatible = "atmel,at91sam9260-pit";
388 reg = <0xfffffe30 0xf>;
389 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
390 clocks = <&mck>;
391 };
393 sckc@fffffe50 {
394 compatible = "atmel,at91sam9x5-sckc";
395 reg = <0xfffffe50 0x4>;
397 slow_osc: slow_osc {
398 compatible = "atmel,at91sam9x5-clk-slow-osc";
399 #clock-cells = <0>;
400 clocks = <&slow_xtal>;
401 };
403 slow_rc_osc: slow_rc_osc {
404 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
405 #clock-cells = <0>;
406 clock-frequency = <32768>;
407 clock-accuracy = <50000000>;
408 };
410 clk32k: slck {
411 compatible = "atmel,at91sam9x5-clk-slow";
412 #clock-cells = <0>;
413 clocks = <&slow_rc_osc>, <&slow_osc>;
414 };
415 };
417 tcb0: timer@f8008000 {
418 compatible = "atmel,at91sam9x5-tcb";
419 reg = <0xf8008000 0x100>;
420 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
421 clocks = <&tcb0_clk>;
422 clock-names = "t0_clk";
423 };
425 tcb1: timer@f800c000 {
426 compatible = "atmel,at91sam9x5-tcb";
427 reg = <0xf800c000 0x100>;
428 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
429 clocks = <&tcb0_clk>;
430 clock-names = "t0_clk";
431 };
433 dma0: dma-controller@ffffec00 {
434 compatible = "atmel,at91sam9g45-dma";
435 reg = <0xffffec00 0x200>;
436 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
437 #dma-cells = <2>;
438 clocks = <&dma0_clk>;
439 clock-names = "dma_clk";
440 };
442 dma1: dma-controller@ffffee00 {
443 compatible = "atmel,at91sam9g45-dma";
444 reg = <0xffffee00 0x200>;
445 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
446 #dma-cells = <2>;
447 clocks = <&dma1_clk>;
448 clock-names = "dma_clk";
449 };
451 pinctrl@fffff400 {
452 #address-cells = <1>;
453 #size-cells = <1>;
454 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
455 ranges = <0xfffff400 0xfffff400 0x800>;
457 /* shared pinctrl settings */
458 dbgu {
459 pinctrl_dbgu: dbgu-0 {
460 atmel,pins =
461 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
462 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */
463 };
464 };
466 usart0 {
467 pinctrl_usart0: usart0-0 {
468 atmel,pins =
469 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
470 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */
471 };
473 pinctrl_usart0_rts: usart0_rts-0 {
474 atmel,pins =
475 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
476 };
478 pinctrl_usart0_cts: usart0_cts-0 {
479 atmel,pins =
480 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
481 };
483 pinctrl_usart0_sck: usart0_sck-0 {
484 atmel,pins =
485 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
486 };
487 };
489 usart1 {
490 pinctrl_usart1: usart1-0 {
491 atmel,pins =
492 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */
493 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
494 };
496 pinctrl_usart1_rts: usart1_rts-0 {
497 atmel,pins =
498 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */
499 };
501 pinctrl_usart1_cts: usart1_cts-0 {
502 atmel,pins =
503 <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */
504 };
506 pinctrl_usart1_sck: usart1_sck-0 {
507 atmel,pins =
508 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */
509 };
510 };
512 usart2 {
513 pinctrl_usart2: usart2-0 {
514 atmel,pins =
515 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
516 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
517 };
519 pinctrl_usart2_rts: usart2_rts-0 {
520 atmel,pins =
521 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
522 };
524 pinctrl_usart2_cts: usart2_cts-0 {
525 atmel,pins =
526 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
527 };
529 pinctrl_usart2_sck: usart2_sck-0 {
530 atmel,pins =
531 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
532 };
533 };
535 uart0 {
536 pinctrl_uart0: uart0-0 {
537 atmel,pins =
538 <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */
539 AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */
540 };
541 };
543 uart1 {
544 pinctrl_uart1: uart1-0 {
545 atmel,pins =
546 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */
547 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */
548 };
549 };
551 nand {
552 pinctrl_nand: nand-0 {
553 atmel,pins =
554 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
555 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */
556 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */
557 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */
558 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */
559 AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */
560 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */
561 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */
562 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */
563 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */
564 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */
565 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */
566 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */
567 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */
568 };
570 pinctrl_nand_16bits: nand_16bits-0 {
571 atmel,pins =
572 <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */
573 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */
574 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */
575 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */
576 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */
577 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */
578 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */
579 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */
580 };
581 };
583 mmc0 {
584 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
585 atmel,pins =
586 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
587 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
588 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
589 };
591 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
592 atmel,pins =
593 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
594 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
595 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
596 };
597 };
599 mmc1 {
600 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
601 atmel,pins =
602 <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */
603 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
604 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */
605 };
607 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
608 atmel,pins =
609 <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */
610 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */
611 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */
612 };
613 };
615 ssc0 {
616 pinctrl_ssc0_tx: ssc0_tx-0 {
617 atmel,pins =
618 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
619 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
620 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
621 };
623 pinctrl_ssc0_rx: ssc0_rx-0 {
624 atmel,pins =
625 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
626 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
627 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
628 };
629 };
631 spi0 {
632 pinctrl_spi0: spi0-0 {
633 atmel,pins =
634 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
635 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
636 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
637 };
638 };
640 spi1 {
641 pinctrl_spi1: spi1-0 {
642 atmel,pins =
643 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
644 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
645 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
646 };
647 };
649 i2c0 {
650 pinctrl_i2c0: i2c0-0 {
651 atmel,pins =
652 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */
653 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */
654 };
655 };
657 i2c1 {
658 pinctrl_i2c1: i2c1-0 {
659 atmel,pins =
660 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */
661 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */
662 };
663 };
665 i2c2 {
666 pinctrl_i2c2: i2c2-0 {
667 atmel,pins =
668 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */
669 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */
670 };
671 };
673 i2c_gpio0 {
674 pinctrl_i2c_gpio0: i2c_gpio0-0 {
675 atmel,pins =
676 <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */
677 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */
678 };
679 };
681 i2c_gpio1 {
682 pinctrl_i2c_gpio1: i2c_gpio1-0 {
683 atmel,pins =
684 <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */
685 AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */
686 };
687 };
689 i2c_gpio2 {
690 pinctrl_i2c_gpio2: i2c_gpio2-0 {
691 atmel,pins =
692 <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */
693 AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */
694 };
695 };
697 pwm0 {
698 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
699 atmel,pins =
700 <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
701 };
702 pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
703 atmel,pins =
704 <AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE>;
705 };
706 pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
707 atmel,pins =
708 <AT91_PIOC 18 AT91_PERIPH_C AT91_PINCTRL_NONE>;
709 };
711 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
712 atmel,pins =
713 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
714 };
715 pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
716 atmel,pins =
717 <AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE>;
718 };
719 pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
720 atmel,pins =
721 <AT91_PIOC 19 AT91_PERIPH_C AT91_PINCTRL_NONE>;
722 };
724 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
725 atmel,pins =
726 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
727 };
728 pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
729 atmel,pins =
730 <AT91_PIOC 20 AT91_PERIPH_C AT91_PINCTRL_NONE>;
731 };
733 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
734 atmel,pins =
735 <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
736 };
737 pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
738 atmel,pins =
739 <AT91_PIOC 21 AT91_PERIPH_C AT91_PINCTRL_NONE>;
740 };
741 };
743 tcb0 {
744 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
745 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
746 };
748 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
749 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
750 };
752 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
753 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
754 };
756 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
757 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
758 };
760 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
761 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
762 };
764 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
765 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
766 };
768 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
769 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
770 };
772 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
773 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
774 };
776 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
777 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
778 };
779 };
781 tcb1 {
782 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
783 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
784 };
786 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
787 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
788 };
790 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
791 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
792 };
794 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
795 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
796 };
798 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
799 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
800 };
802 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
803 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
804 };
806 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
807 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
808 };
810 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
811 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
812 };
814 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
815 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
816 };
817 };
819 pioA: gpio@fffff400 {
820 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
821 reg = <0xfffff400 0x200>;
822 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
823 #gpio-cells = <2>;
824 gpio-controller;
825 interrupt-controller;
826 #interrupt-cells = <2>;
827 clocks = <&pioAB_clk>;
828 };
830 pioB: gpio@fffff600 {
831 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
832 reg = <0xfffff600 0x200>;
833 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
834 #gpio-cells = <2>;
835 gpio-controller;
836 #gpio-lines = <19>;
837 interrupt-controller;
838 #interrupt-cells = <2>;
839 clocks = <&pioAB_clk>;
840 };
842 pioC: gpio@fffff800 {
843 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
844 reg = <0xfffff800 0x200>;
845 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
846 #gpio-cells = <2>;
847 gpio-controller;
848 interrupt-controller;
849 #interrupt-cells = <2>;
850 clocks = <&pioCD_clk>;
851 };
853 pioD: gpio@fffffa00 {
854 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
855 reg = <0xfffffa00 0x200>;
856 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
857 #gpio-cells = <2>;
858 gpio-controller;
859 #gpio-lines = <22>;
860 interrupt-controller;
861 #interrupt-cells = <2>;
862 clocks = <&pioCD_clk>;
863 };
864 };
866 ssc0: ssc@f0010000 {
867 compatible = "atmel,at91sam9g45-ssc";
868 reg = <0xf0010000 0x4000>;
869 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
870 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>,
871 <&dma0 1 AT91_DMA_CFG_PER_ID(14)>;
872 dma-names = "tx", "rx";
873 pinctrl-names = "default";
874 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
875 clocks = <&ssc0_clk>;
876 clock-names = "pclk";
877 status = "disabled";
878 };
880 mmc0: mmc@f0008000 {
881 compatible = "atmel,hsmci";
882 reg = <0xf0008000 0x600>;
883 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
884 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
885 dma-names = "rxtx";
886 pinctrl-names = "default";
887 clocks = <&mci0_clk>;
888 clock-names = "mci_clk";
889 #address-cells = <1>;
890 #size-cells = <0>;
891 status = "disabled";
892 };
894 mmc1: mmc@f000c000 {
895 compatible = "atmel,hsmci";
896 reg = <0xf000c000 0x600>;
897 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
898 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
899 dma-names = "rxtx";
900 pinctrl-names = "default";
901 clocks = <&mci1_clk>;
902 clock-names = "mci_clk";
903 #address-cells = <1>;
904 #size-cells = <0>;
905 status = "disabled";
906 };
908 dbgu: serial@fffff200 {
909 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
910 reg = <0xfffff200 0x200>;
911 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
912 pinctrl-names = "default";
913 pinctrl-0 = <&pinctrl_dbgu>;
914 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
915 <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
916 dma-names = "tx", "rx";
917 clocks = <&mck>;
918 clock-names = "usart";
919 status = "disabled";
920 };
922 usart0: serial@f801c000 {
923 compatible = "atmel,at91sam9260-usart";
924 reg = <0xf801c000 0x200>;
925 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
926 pinctrl-names = "default";
927 pinctrl-0 = <&pinctrl_usart0>;
928 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
929 <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
930 dma-names = "tx", "rx";
931 clocks = <&usart0_clk>;
932 clock-names = "usart";
933 status = "disabled";
934 };
936 usart1: serial@f8020000 {
937 compatible = "atmel,at91sam9260-usart";
938 reg = <0xf8020000 0x200>;
939 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
940 pinctrl-names = "default";
941 pinctrl-0 = <&pinctrl_usart1>;
942 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
943 <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
944 dma-names = "tx", "rx";
945 clocks = <&usart1_clk>;
946 clock-names = "usart";
947 status = "disabled";
948 };
950 usart2: serial@f8024000 {
951 compatible = "atmel,at91sam9260-usart";
952 reg = <0xf8024000 0x200>;
953 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
954 pinctrl-names = "default";
955 pinctrl-0 = <&pinctrl_usart2>;
956 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
957 <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
958 dma-names = "tx", "rx";
959 clocks = <&usart2_clk>;
960 clock-names = "usart";
961 status = "disabled";
962 };
964 i2c0: i2c@f8010000 {
965 compatible = "atmel,at91sam9x5-i2c";
966 reg = <0xf8010000 0x100>;
967 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
968 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
969 <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
970 dma-names = "tx", "rx";
971 #address-cells = <1>;
972 #size-cells = <0>;
973 pinctrl-names = "default";
974 pinctrl-0 = <&pinctrl_i2c0>;
975 clocks = <&twi0_clk>;
976 status = "disabled";
977 };
979 i2c1: i2c@f8014000 {
980 compatible = "atmel,at91sam9x5-i2c";
981 reg = <0xf8014000 0x100>;
982 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
983 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
984 <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
985 dma-names = "tx", "rx";
986 #address-cells = <1>;
987 #size-cells = <0>;
988 pinctrl-names = "default";
989 pinctrl-0 = <&pinctrl_i2c1>;
990 clocks = <&twi1_clk>;
991 status = "disabled";
992 };
994 i2c2: i2c@f8018000 {
995 compatible = "atmel,at91sam9x5-i2c";
996 reg = <0xf8018000 0x100>;
997 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
998 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
999 <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
1000 dma-names = "tx", "rx";
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&pinctrl_i2c2>;
1005 clocks = <&twi2_clk>;
1006 status = "disabled";
1007 };
1009 uart0: serial@f8040000 {
1010 compatible = "atmel,at91sam9260-usart";
1011 reg = <0xf8040000 0x200>;
1012 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&pinctrl_uart0>;
1015 clocks = <&uart0_clk>;
1016 clock-names = "usart";
1017 status = "disabled";
1018 };
1020 uart1: serial@f8044000 {
1021 compatible = "atmel,at91sam9260-usart";
1022 reg = <0xf8044000 0x200>;
1023 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
1024 pinctrl-names = "default";
1025 pinctrl-0 = <&pinctrl_uart1>;
1026 clocks = <&uart1_clk>;
1027 clock-names = "usart";
1028 status = "disabled";
1029 };
1031 adc0: adc@f804c000 {
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1034 compatible = "atmel,at91sam9x5-adc";
1035 reg = <0xf804c000 0x100>;
1036 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
1037 clocks = <&adc_clk>,
1038 <&adc_op_clk>;
1039 clock-names = "adc_clk", "adc_op_clk";
1040 atmel,adc-use-external-triggers;
1041 atmel,adc-channels-used = <0xffff>;
1042 atmel,adc-vref = <3300>;
1043 atmel,adc-startup-time = <40>;
1044 atmel,adc-res = <8 10>;
1045 atmel,adc-res-names = "lowres", "highres";
1046 atmel,adc-use-res = "highres";
1048 trigger@0 {
1049 reg = <0>;
1050 trigger-name = "external-rising";
1051 trigger-value = <0x1>;
1052 trigger-external;
1053 };
1055 trigger@1 {
1056 reg = <1>;
1057 trigger-name = "external-falling";
1058 trigger-value = <0x2>;
1059 trigger-external;
1060 };
1062 trigger@2 {
1063 reg = <2>;
1064 trigger-name = "external-any";
1065 trigger-value = <0x3>;
1066 trigger-external;
1067 };
1069 trigger@3 {
1070 reg = <3>;
1071 trigger-name = "continuous";
1072 trigger-value = <0x6>;
1073 };
1074 };
1076 spi0: spi@f0000000 {
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079 compatible = "atmel,at91rm9200-spi";
1080 reg = <0xf0000000 0x100>;
1081 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
1082 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
1083 <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
1084 dma-names = "tx", "rx";
1085 pinctrl-names = "default";
1086 pinctrl-0 = <&pinctrl_spi0>;
1087 clocks = <&spi0_clk>;
1088 clock-names = "spi_clk";
1089 status = "disabled";
1090 };
1092 spi1: spi@f0004000 {
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1095 compatible = "atmel,at91rm9200-spi";
1096 reg = <0xf0004000 0x100>;
1097 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
1098 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
1099 <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
1100 dma-names = "tx", "rx";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&pinctrl_spi1>;
1103 clocks = <&spi1_clk>;
1104 clock-names = "spi_clk";
1105 status = "disabled";
1106 };
1108 usb2: gadget@f803c000 {
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 compatible = "atmel,at91sam9g45-udc";
1112 reg = <0x00500000 0x80000
1113 0xf803c000 0x400>;
1114 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
1115 clocks = <&utmi>, <&udphs_clk>;
1116 clock-names = "hclk", "pclk";
1117 status = "disabled";
1119 ep0 {
1120 reg = <0>;
1121 atmel,fifo-size = <64>;
1122 atmel,nb-banks = <1>;
1123 };
1125 ep1 {
1126 reg = <1>;
1127 atmel,fifo-size = <1024>;
1128 atmel,nb-banks = <2>;
1129 atmel,can-dma;
1130 atmel,can-isoc;
1131 };
1133 ep2 {
1134 reg = <2>;
1135 atmel,fifo-size = <1024>;
1136 atmel,nb-banks = <2>;
1137 atmel,can-dma;
1138 atmel,can-isoc;
1139 };
1141 ep3 {
1142 reg = <3>;
1143 atmel,fifo-size = <1024>;
1144 atmel,nb-banks = <3>;
1145 atmel,can-dma;
1146 };
1148 ep4 {
1149 reg = <4>;
1150 atmel,fifo-size = <1024>;
1151 atmel,nb-banks = <3>;
1152 atmel,can-dma;
1153 };
1155 ep5 {
1156 reg = <5>;
1157 atmel,fifo-size = <1024>;
1158 atmel,nb-banks = <3>;
1159 atmel,can-dma;
1160 atmel,can-isoc;
1161 };
1163 ep6 {
1164 reg = <6>;
1165 atmel,fifo-size = <1024>;
1166 atmel,nb-banks = <3>;
1167 atmel,can-dma;
1168 atmel,can-isoc;
1169 };
1170 };
1172 watchdog@fffffe40 {
1173 compatible = "atmel,at91sam9260-wdt";
1174 reg = <0xfffffe40 0x10>;
1175 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1176 atmel,watchdog-type = "hardware";
1177 atmel,reset-type = "all";
1178 atmel,dbg-halt;
1179 status = "disabled";
1180 };
1182 rtc@fffffeb0 {
1183 compatible = "atmel,at91sam9x5-rtc";
1184 reg = <0xfffffeb0 0x40>;
1185 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1186 status = "disabled";
1187 };
1189 pwm0: pwm@f8034000 {
1190 compatible = "atmel,at91sam9rl-pwm";
1191 reg = <0xf8034000 0x300>;
1192 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
1193 clocks = <&pwm_clk>;
1194 #pwm-cells = <3>;
1195 status = "disabled";
1196 };
1197 };
1199 nand0: nand@40000000 {
1200 compatible = "atmel,at91rm9200-nand";
1201 #address-cells = <1>;
1202 #size-cells = <1>;
1203 reg = <0x40000000 0x10000000
1204 0xffffe000 0x600 /* PMECC Registers */
1205 0xffffe600 0x200 /* PMECC Error Location Registers */
1206 0x00108000 0x18000 /* PMECC looup table in ROM code */
1207 >;
1208 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1209 atmel,nand-addr-offset = <21>;
1210 atmel,nand-cmd-offset = <22>;
1211 atmel,nand-has-dma;
1212 pinctrl-names = "default";
1213 pinctrl-0 = <&pinctrl_nand>;
1214 gpios = <&pioD 5 GPIO_ACTIVE_HIGH
1215 &pioD 4 GPIO_ACTIVE_HIGH
1216 0
1217 >;
1218 status = "disabled";
1219 };
1221 usb0: ohci@00600000 {
1222 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1223 reg = <0x00600000 0x100000>;
1224 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1225 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1226 clock-names = "ohci_clk", "hclk", "uhpck";
1227 status = "disabled";
1228 };
1230 usb1: ehci@00700000 {
1231 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1232 reg = <0x00700000 0x100000>;
1233 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1234 clocks = <&utmi>, <&uhphs_clk>;
1235 clock-names = "usb_clk", "ehci_clk";
1236 status = "disabled";
1237 };
1238 };
1240 i2c@0 {
1241 compatible = "i2c-gpio";
1242 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
1243 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
1244 >;
1245 i2c-gpio,sda-open-drain;
1246 i2c-gpio,scl-open-drain;
1247 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1248 #address-cells = <1>;
1249 #size-cells = <0>;
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&pinctrl_i2c_gpio0>;
1252 status = "disabled";
1253 };
1255 i2c@1 {
1256 compatible = "i2c-gpio";
1257 gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
1258 &pioC 1 GPIO_ACTIVE_HIGH /* scl */
1259 >;
1260 i2c-gpio,sda-open-drain;
1261 i2c-gpio,scl-open-drain;
1262 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&pinctrl_i2c_gpio1>;
1267 status = "disabled";
1268 };
1270 i2c@2 {
1271 compatible = "i2c-gpio";
1272 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
1273 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
1274 >;
1275 i2c-gpio,sda-open-drain;
1276 i2c-gpio,scl-open-drain;
1277 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1278 #address-cells = <1>;
1279 #size-cells = <0>;
1280 pinctrl-names = "default";
1281 pinctrl-0 = <&pinctrl_i2c_gpio2>;
1282 status = "disabled";
1283 };
1284 };