arch/arm/boot/dts/rk3188.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46 #include <dt-bindings/clock/rk3188-cru.h>
  47 #include "rk3xxx.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3188";
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a9";
  60                         next-level-cache = <&L2>;
  61                         reg = <0x0>;
  62                         operating-points = <
  63                                 /* kHz    uV */
  64                                 1608000 1350000
  65                                 1416000 1250000
  66                                 1200000 1150000
  67                                 1008000 1075000
  68                                  816000  975000
  69                                  600000  950000
  70                                  504000  925000
  71                                  312000  875000
  72                         >;
  73                         clock-latency = <40000>;
  74                         clocks = <&cru ARMCLK>;
  75                 };
  76                 cpu@1 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a9";
  79                         next-level-cache = <&L2>;
  80                         reg = <0x1>;
  81                 };
  82                 cpu@2 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a9";
  85                         next-level-cache = <&L2>;
  86                         reg = <0x2>;
  87                 };
  88                 cpu@3 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a9";
  91                         next-level-cache = <&L2>;
  92                         reg = <0x3>;
  93                 };
  94         };
  95
  96         sram: sram@10080000 {
  97                 compatible = "mmio-sram";
  98                 reg = <0x10080000 0x8000>;
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges = <0 0x10080000 0x8000>;
 102
 103                 smp-sram@0 {
 104                         compatible = "rockchip,rk3066-smp-sram";
 105                         reg = <0x0 0x50>;
 106                 };
 107         };
 108
 109         i2s0: i2s@1011a000 {
 110                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
 111                 reg = <0x1011a000 0x2000>;
 112                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115                 pinctrl-names = "default";
 116                 pinctrl-0 = <&i2s0_bus>;
 117                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 118                 dma-names = "tx", "rx";
 119                 clock-names = "i2s_hclk", "i2s_clk";
 120                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 121                 status = "disabled";
 122         };
 123
 124         cru: clock-controller@20000000 {
 125                 compatible = "rockchip,rk3188-cru";
 126                 reg = <0x20000000 0x1000>;
 127                 rockchip,grf = <&grf>;
 128
 129                 #clock-cells = <1>;
 130                 #reset-cells = <1>;
 131         };
 132
 133         pinctrl: pinctrl {
 134                 compatible = "rockchip,rk3188-pinctrl";
 135                 rockchip,grf = <&grf>;
 136                 rockchip,pmu = <&pmu>;
 137
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 gpio0: gpio0@2000a000 {
 143                         compatible = "rockchip,rk3188-gpio-bank0";
 144                         reg = <0x2000a000 0x100>;
 145                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 146                         clocks = <&cru PCLK_GPIO0>;
 147
 148                         gpio-controller;
 149                         #gpio-cells = <2>;
 150
 151                         interrupt-controller;
 152                         #interrupt-cells = <2>;
 153                 };
 154
 155                 gpio1: gpio1@2003c000 {
 156                         compatible = "rockchip,gpio-bank";
 157                         reg = <0x2003c000 0x100>;
 158                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&cru PCLK_GPIO1>;
 160
 161                         gpio-controller;
 162                         #gpio-cells = <2>;
 163
 164                         interrupt-controller;
 165                         #interrupt-cells = <2>;
 166                 };
 167
 168                 gpio2: gpio2@2003e000 {
 169                         compatible = "rockchip,gpio-bank";
 170                         reg = <0x2003e000 0x100>;
 171                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 172                         clocks = <&cru PCLK_GPIO2>;
 173
 174                         gpio-controller;
 175                         #gpio-cells = <2>;
 176
 177                         interrupt-controller;
 178                         #interrupt-cells = <2>;
 179                 };
 180
 181                 gpio3: gpio3@20080000 {
 182                         compatible = "rockchip,gpio-bank";
 183                         reg = <0x20080000 0x100>;
 184                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 185                         clocks = <&cru PCLK_GPIO3>;
 186
 187                         gpio-controller;
 188                         #gpio-cells = <2>;
 189
 190                         interrupt-controller;
 191                         #interrupt-cells = <2>;
 192                 };
 193
 194                 pcfg_pull_up: pcfg_pull_up {
 195                         bias-pull-up;
 196                 };
 197
 198                 pcfg_pull_down: pcfg_pull_down {
 199                         bias-pull-down;
 200                 };
 201
 202                 pcfg_pull_none: pcfg_pull_none {
 203                         bias-disable;
 204                 };
 205
 206                 emmc {
 207                         emmc_clk: emmc-clk {
 208                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
 209                         };
 210
 211                         emmc_cmd: emmc-cmd {
 212                                 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
 213                         };
 214
 215                         emmc_rst: emmc-rst {
 216                                 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
 217                         };
 218
 219                         /*
 220                          * The data pins are shared between nandc and emmc and
 221                          * not accessible through pinctrl. Also they should've
 222                          * been already set correctly by firmware, as
 223                          * flash/emmc is the boot-device.
 224                          */
 225                 };
 226
 227                 emac {
 228                         emac_xfer: emac-xfer {
 229                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 230                                                 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 231                                                 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 232                                                 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
 233                                                 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 234                                                 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 235                                                 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 236                                                 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
 237                         };
 238
 239                         emac_mdio: emac-mdio {
 240                                 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
 241                                                 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
 242                         };
 243                 };
 244
 245                 i2c0 {
 246                         i2c0_xfer: i2c0-xfer {
 247                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
 248                                                 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
 249                         };
 250                 };
 251
 252                 i2c1 {
 253                         i2c1_xfer: i2c1-xfer {
 254                                 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
 255                                                 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
 256                         };
 257                 };
 258
 259                 i2c2 {
 260                         i2c2_xfer: i2c2-xfer {
 261                                 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
 262                                                 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
 263                         };
 264                 };
 265
 266                 i2c3 {
 267                         i2c3_xfer: i2c3-xfer {
 268                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
 269                                                 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
 270                         };
 271                 };
 272
 273                 i2c4 {
 274                         i2c4_xfer: i2c4-xfer {
 275                                 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
 276                                                 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
 277                         };
 278                 };
 279
 280                 pwm0 {
 281                         pwm0_out: pwm0-out {
 282                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
 283                         };
 284                 };
 285
 286                 pwm1 {
 287                         pwm1_out: pwm1-out {
 288                                 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
 289                         };
 290                 };
 291
 292                 pwm2 {
 293                         pwm2_out: pwm2-out {
 294                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
 295                         };
 296                 };
 297
 298                 pwm3 {
 299                         pwm3_out: pwm3-out {
 300                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
 301                         };
 302                 };
 303
 304                 spi0 {
 305                         spi0_clk: spi0-clk {
 306                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
 307                         };
 308                         spi0_cs0: spi0-cs0 {
 309                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
 310                         };
 311                         spi0_tx: spi0-tx {
 312                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
 313                         };
 314                         spi0_rx: spi0-rx {
 315                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
 316                         };
 317                         spi0_cs1: spi0-cs1 {
 318                                 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
 319                         };
 320                 };
 321
 322                 spi1 {
 323                         spi1_clk: spi1-clk {
 324                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
 325                         };
 326                         spi1_cs0: spi1-cs0 {
 327                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
 328                         };
 329                         spi1_rx: spi1-rx {
 330                                 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
 331                         };
 332                         spi1_tx: spi1-tx {
 333                                 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
 334                         };
 335                         spi1_cs1: spi1-cs1 {
 336                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
 337                         };
 338                 };
 339
 340                 uart0 {
 341                         uart0_xfer: uart0-xfer {
 342                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 343                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 344                         };
 345
 346                         uart0_cts: uart0-cts {
 347                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 348                         };
 349
 350                         uart0_rts: uart0-rts {
 351                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 352                         };
 353                 };
 354
 355                 uart1 {
 356                         uart1_xfer: uart1-xfer {
 357                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 358                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 359                         };
 360
 361                         uart1_cts: uart1-cts {
 362                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 363                         };
 364
 365                         uart1_rts: uart1-rts {
 366                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 367                         };
 368                 };
 369
 370                 uart2 {
 371                         uart2_xfer: uart2-xfer {
 372                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 373                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 374                         };
 375                         /* no rts / cts for uart2 */
 376                 };
 377
 378                 uart3 {
 379                         uart3_xfer: uart3-xfer {
 380                                 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 381                                                 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 382                         };
 383
 384                         uart3_cts: uart3-cts {
 385                                 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 386                         };
 387
 388                         uart3_rts: uart3-rts {
 389                                 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 390                         };
 391                 };
 392
 393                 sd0 {
 394                         sd0_clk: sd0-clk {
 395                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 396                         };
 397
 398                         sd0_cmd: sd0-cmd {
 399                                 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 400                         };
 401
 402                         sd0_cd: sd0-cd {
 403                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 404                         };
 405
 406                         sd0_wp: sd0-wp {
 407                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 408                         };
 409
 410                         sd0_pwr: sd0-pwr {
 411                                 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 412                         };
 413
 414                         sd0_bus1: sd0-bus-width1 {
 415                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 416                         };
 417
 418                         sd0_bus4: sd0-bus-width4 {
 419                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 420                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 421                                                 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 422                                                 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 423                         };
 424                 };
 425
 426                 sd1 {
 427                         sd1_clk: sd1-clk {
 428                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 429                         };
 430
 431                         sd1_cmd: sd1-cmd {
 432                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 433                         };
 434
 435                         sd1_cd: sd1-cd {
 436                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 437                         };
 438
 439                         sd1_wp: sd1-wp {
 440                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 441                         };
 442
 443                         sd1_bus1: sd1-bus-width1 {
 444                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 445                         };
 446
 447                         sd1_bus4: sd1-bus-width4 {
 448                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 449                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 450                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 451                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 452                         };
 453                 };
 454
 455                 i2s0 {
 456                         i2s0_bus: i2s0-bus {
 457                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
 458                                                 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
 459                                                 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
 460                                                 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
 461                                                 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
 462                                                 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
 463                         };
 464                 };
 465         };
 466 };
 467
 468 &emac {
 469         compatible = "rockchip,rk3188-emac";
 470 };
 471
 472 &global_timer {
 473         interrupts = <GIC_PPI 11 0xf04>;
 474 };
 475
 476 &local_timer {
 477         interrupts = <GIC_PPI 13 0xf04>;
 478 };
 479
 480 &i2c0 {
 481         compatible = "rockchip,rk3188-i2c";
 482         pinctrl-names = "default";
 483         pinctrl-0 = <&i2c0_xfer>;
 484 };
 485
 486 &i2c1 {
 487         compatible = "rockchip,rk3188-i2c";
 488         pinctrl-names = "default";
 489         pinctrl-0 = <&i2c1_xfer>;
 490 };
 491
 492 &i2c2 {
 493         compatible = "rockchip,rk3188-i2c";
 494         pinctrl-names = "default";
 495         pinctrl-0 = <&i2c2_xfer>;
 496 };
 497
 498 &i2c3 {
 499         compatible = "rockchip,rk3188-i2c";
 500         pinctrl-names = "default";
 501         pinctrl-0 = <&i2c3_xfer>;
 502 };
 503
 504 &i2c4 {
 505         compatible = "rockchip,rk3188-i2c";
 506         pinctrl-names = "default";
 507         pinctrl-0 = <&i2c4_xfer>;
 508 };
 509
 510 &pwm0 {
 511         pinctrl-names = "default";
 512         pinctrl-0 = <&pwm0_out>;
 513 };
 514
 515 &pwm1 {
 516         pinctrl-names = "default";
 517         pinctrl-0 = <&pwm1_out>;
 518 };
 519
 520 &pwm2 {
 521         pinctrl-names = "default";
 522         pinctrl-0 = <&pwm2_out>;
 523 };
 524
 525 &pwm3 {
 526         pinctrl-names = "default";
 527         pinctrl-0 = <&pwm3_out>;
 528 };
 529
 530 &spi0 {
 531         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 532         pinctrl-names = "default";
 533         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 534 };
 535
 536 &spi1 {
 537         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 538         pinctrl-names = "default";
 539         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 540 };
 541
 542 &uart0 {
 543         pinctrl-names = "default";
 544         pinctrl-0 = <&uart0_xfer>;
 545 };
 546
 547 &uart1 {
 548         pinctrl-names = "default";
 549         pinctrl-0 = <&uart1_xfer>;
 550 };
 551
 552 &uart2 {
 553         pinctrl-names = "default";
 554         pinctrl-0 = <&uart2_xfer>;
 555 };
 556
 557 &uart3 {
 558         pinctrl-names = "default";
 559         pinctrl-0 = <&uart3_xfer>;
 560 };
 561
 562 &wdt {
 563         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 564 };