| blob | 61c03d1fe5303301a7ee44f1069c3865da958313 |
1 /*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
44 #include "skeleton.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
51 / {
52 interrupt-parent = <&intc>;
54 aliases {
55 ethernet0 = &emac;
56 };
58 chosen {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
63 framebuffer@0 {
64 compatible = "allwinner,simple-framebuffer",
65 "simple-framebuffer";
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
68 <&ahb_gates 44>;
69 status = "disabled";
70 };
72 framebuffer@1 {
73 compatible = "allwinner,simple-framebuffer",
74 "simple-framebuffer";
75 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
76 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
77 <&ahb_gates 44>, <&ahb_gates 46>;
78 status = "disabled";
79 };
81 framebuffer@2 {
82 compatible = "allwinner,simple-framebuffer",
83 "simple-framebuffer";
84 allwinner,pipeline = "de_fe0-de_be0-lcd0";
85 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
86 <&ahb_gates 46>;
87 status = "disabled";
88 };
90 framebuffer@3 {
91 compatible = "allwinner,simple-framebuffer",
92 "simple-framebuffer";
93 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
94 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
95 <&ahb_gates 44>, <&ahb_gates 46>;
96 status = "disabled";
97 };
98 };
100 cpus {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 cpu0: cpu@0 {
104 device_type = "cpu";
105 compatible = "arm,cortex-a8";
106 reg = <0x0>;
107 clocks = <&cpu>;
108 clock-latency = <244144>; /* 8 32k periods */
109 operating-points = <
110 /* kHz uV */
111 1008000 1400000
112 912000 1350000
113 864000 1300000
114 624000 1250000
115 >;
116 #cooling-cells = <2>;
117 cooling-min-level = <0>;
118 cooling-max-level = <3>;
119 };
120 };
122 thermal-zones {
123 cpu_thermal {
124 /* milliseconds */
125 polling-delay-passive = <250>;
126 polling-delay = <1000>;
127 thermal-sensors = <&rtp>;
129 cooling-maps {
130 map0 {
131 trip = <&cpu_alert0>;
132 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
133 };
134 };
136 trips {
137 cpu_alert0: cpu_alert0 {
138 /* milliCelsius */
139 temperature = <850000>;
140 hysteresis = <2000>;
141 type = "passive";
142 };
144 cpu_crit: cpu_crit {
145 /* milliCelsius */
146 temperature = <100000>;
147 hysteresis = <2000>;
148 type = "critical";
149 };
150 };
151 };
152 };
154 memory {
155 reg = <0x40000000 0x80000000>;
156 };
158 clocks {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 ranges;
163 /*
164 * This is a dummy clock, to be used as placeholder on
165 * other mux clocks when a specific parent clock is not
166 * yet implemented. It should be dropped when the driver
167 * is complete.
168 */
169 dummy: dummy {
170 #clock-cells = <0>;
171 compatible = "fixed-clock";
172 clock-frequency = <0>;
173 };
175 osc24M: clk@01c20050 {
176 #clock-cells = <0>;
177 compatible = "allwinner,sun4i-a10-osc-clk";
178 reg = <0x01c20050 0x4>;
179 clock-frequency = <24000000>;
180 clock-output-names = "osc24M";
181 };
183 osc32k: clk@0 {
184 #clock-cells = <0>;
185 compatible = "fixed-clock";
186 clock-frequency = <32768>;
187 clock-output-names = "osc32k";
188 };
190 pll1: clk@01c20000 {
191 #clock-cells = <0>;
192 compatible = "allwinner,sun4i-a10-pll1-clk";
193 reg = <0x01c20000 0x4>;
194 clocks = <&osc24M>;
195 clock-output-names = "pll1";
196 };
198 pll4: clk@01c20018 {
199 #clock-cells = <0>;
200 compatible = "allwinner,sun4i-a10-pll1-clk";
201 reg = <0x01c20018 0x4>;
202 clocks = <&osc24M>;
203 clock-output-names = "pll4";
204 };
206 pll5: clk@01c20020 {
207 #clock-cells = <1>;
208 compatible = "allwinner,sun4i-a10-pll5-clk";
209 reg = <0x01c20020 0x4>;
210 clocks = <&osc24M>;
211 clock-output-names = "pll5_ddr", "pll5_other";
212 };
214 pll6: clk@01c20028 {
215 #clock-cells = <1>;
216 compatible = "allwinner,sun4i-a10-pll6-clk";
217 reg = <0x01c20028 0x4>;
218 clocks = <&osc24M>;
219 clock-output-names = "pll6_sata", "pll6_other", "pll6";
220 };
222 /* dummy is 200M */
223 cpu: cpu@01c20054 {
224 #clock-cells = <0>;
225 compatible = "allwinner,sun4i-a10-cpu-clk";
226 reg = <0x01c20054 0x4>;
227 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
228 clock-output-names = "cpu";
229 };
231 axi: axi@01c20054 {
232 #clock-cells = <0>;
233 compatible = "allwinner,sun4i-a10-axi-clk";
234 reg = <0x01c20054 0x4>;
235 clocks = <&cpu>;
236 clock-output-names = "axi";
237 };
239 axi_gates: clk@01c2005c {
240 #clock-cells = <1>;
241 compatible = "allwinner,sun4i-a10-axi-gates-clk";
242 reg = <0x01c2005c 0x4>;
243 clocks = <&axi>;
244 clock-output-names = "axi_dram";
245 };
247 ahb: ahb@01c20054 {
248 #clock-cells = <0>;
249 compatible = "allwinner,sun4i-a10-ahb-clk";
250 reg = <0x01c20054 0x4>;
251 clocks = <&axi>;
252 clock-output-names = "ahb";
253 };
255 ahb_gates: clk@01c20060 {
256 #clock-cells = <1>;
257 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
258 reg = <0x01c20060 0x8>;
259 clocks = <&ahb>;
260 clock-output-names = "ahb_usb0", "ahb_ehci0",
261 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
262 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
263 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
264 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
265 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
266 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
267 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
268 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
269 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
270 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
271 };
273 apb0: apb0@01c20054 {
274 #clock-cells = <0>;
275 compatible = "allwinner,sun4i-a10-apb0-clk";
276 reg = <0x01c20054 0x4>;
277 clocks = <&ahb>;
278 clock-output-names = "apb0";
279 };
281 apb0_gates: clk@01c20068 {
282 #clock-cells = <1>;
283 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
284 reg = <0x01c20068 0x4>;
285 clocks = <&apb0>;
286 clock-output-names = "apb0_codec", "apb0_spdif",
287 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
288 "apb0_ir1", "apb0_keypad";
289 };
291 apb1: clk@01c20058 {
292 #clock-cells = <0>;
293 compatible = "allwinner,sun4i-a10-apb1-clk";
294 reg = <0x01c20058 0x4>;
295 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
296 clock-output-names = "apb1";
297 };
299 apb1_gates: clk@01c2006c {
300 #clock-cells = <1>;
301 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
302 reg = <0x01c2006c 0x4>;
303 clocks = <&apb1>;
304 clock-output-names = "apb1_i2c0", "apb1_i2c1",
305 "apb1_i2c2", "apb1_can", "apb1_scr",
306 "apb1_ps20", "apb1_ps21", "apb1_uart0",
307 "apb1_uart1", "apb1_uart2", "apb1_uart3",
308 "apb1_uart4", "apb1_uart5", "apb1_uart6",
309 "apb1_uart7";
310 };
312 nand_clk: clk@01c20080 {
313 #clock-cells = <0>;
314 compatible = "allwinner,sun4i-a10-mod0-clk";
315 reg = <0x01c20080 0x4>;
316 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
317 clock-output-names = "nand";
318 };
320 ms_clk: clk@01c20084 {
321 #clock-cells = <0>;
322 compatible = "allwinner,sun4i-a10-mod0-clk";
323 reg = <0x01c20084 0x4>;
324 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
325 clock-output-names = "ms";
326 };
328 mmc0_clk: clk@01c20088 {
329 #clock-cells = <1>;
330 compatible = "allwinner,sun4i-a10-mmc-clk";
331 reg = <0x01c20088 0x4>;
332 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
333 clock-output-names = "mmc0",
334 "mmc0_output",
335 "mmc0_sample";
336 };
338 mmc1_clk: clk@01c2008c {
339 #clock-cells = <1>;
340 compatible = "allwinner,sun4i-a10-mmc-clk";
341 reg = <0x01c2008c 0x4>;
342 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
343 clock-output-names = "mmc1",
344 "mmc1_output",
345 "mmc1_sample";
346 };
348 mmc2_clk: clk@01c20090 {
349 #clock-cells = <1>;
350 compatible = "allwinner,sun4i-a10-mmc-clk";
351 reg = <0x01c20090 0x4>;
352 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
353 clock-output-names = "mmc2",
354 "mmc2_output",
355 "mmc2_sample";
356 };
358 mmc3_clk: clk@01c20094 {
359 #clock-cells = <1>;
360 compatible = "allwinner,sun4i-a10-mmc-clk";
361 reg = <0x01c20094 0x4>;
362 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
363 clock-output-names = "mmc3",
364 "mmc3_output",
365 "mmc3_sample";
366 };
368 ts_clk: clk@01c20098 {
369 #clock-cells = <0>;
370 compatible = "allwinner,sun4i-a10-mod0-clk";
371 reg = <0x01c20098 0x4>;
372 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
373 clock-output-names = "ts";
374 };
376 ss_clk: clk@01c2009c {
377 #clock-cells = <0>;
378 compatible = "allwinner,sun4i-a10-mod0-clk";
379 reg = <0x01c2009c 0x4>;
380 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
381 clock-output-names = "ss";
382 };
384 spi0_clk: clk@01c200a0 {
385 #clock-cells = <0>;
386 compatible = "allwinner,sun4i-a10-mod0-clk";
387 reg = <0x01c200a0 0x4>;
388 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
389 clock-output-names = "spi0";
390 };
392 spi1_clk: clk@01c200a4 {
393 #clock-cells = <0>;
394 compatible = "allwinner,sun4i-a10-mod0-clk";
395 reg = <0x01c200a4 0x4>;
396 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
397 clock-output-names = "spi1";
398 };
400 spi2_clk: clk@01c200a8 {
401 #clock-cells = <0>;
402 compatible = "allwinner,sun4i-a10-mod0-clk";
403 reg = <0x01c200a8 0x4>;
404 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
405 clock-output-names = "spi2";
406 };
408 pata_clk: clk@01c200ac {
409 #clock-cells = <0>;
410 compatible = "allwinner,sun4i-a10-mod0-clk";
411 reg = <0x01c200ac 0x4>;
412 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
413 clock-output-names = "pata";
414 };
416 ir0_clk: clk@01c200b0 {
417 #clock-cells = <0>;
418 compatible = "allwinner,sun4i-a10-mod0-clk";
419 reg = <0x01c200b0 0x4>;
420 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
421 clock-output-names = "ir0";
422 };
424 ir1_clk: clk@01c200b4 {
425 #clock-cells = <0>;
426 compatible = "allwinner,sun4i-a10-mod0-clk";
427 reg = <0x01c200b4 0x4>;
428 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
429 clock-output-names = "ir1";
430 };
432 usb_clk: clk@01c200cc {
433 #clock-cells = <1>;
434 #reset-cells = <1>;
435 compatible = "allwinner,sun4i-a10-usb-clk";
436 reg = <0x01c200cc 0x4>;
437 clocks = <&pll6 1>;
438 clock-output-names = "usb_ohci0", "usb_ohci1",
439 "usb_phy";
440 };
442 spi3_clk: clk@01c200d4 {
443 #clock-cells = <0>;
444 compatible = "allwinner,sun4i-a10-mod0-clk";
445 reg = <0x01c200d4 0x4>;
446 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
447 clock-output-names = "spi3";
448 };
449 };
451 soc@01c00000 {
452 compatible = "simple-bus";
453 #address-cells = <1>;
454 #size-cells = <1>;
455 ranges;
457 sram-controller@01c00000 {
458 compatible = "allwinner,sun4i-a10-sram-controller";
459 reg = <0x01c00000 0x30>;
460 #address-cells = <1>;
461 #size-cells = <1>;
462 ranges;
464 sram_a: sram@00000000 {
465 compatible = "mmio-sram";
466 reg = <0x00000000 0xc000>;
467 #address-cells = <1>;
468 #size-cells = <1>;
469 ranges = <0 0x00000000 0xc000>;
471 emac_sram: sram-section@8000 {
472 compatible = "allwinner,sun4i-a10-sram-a3-a4";
473 reg = <0x8000 0x4000>;
474 status = "disabled";
475 };
476 };
478 sram_d: sram@00010000 {
479 compatible = "mmio-sram";
480 reg = <0x00010000 0x1000>;
481 #address-cells = <1>;
482 #size-cells = <1>;
483 ranges = <0 0x00010000 0x1000>;
485 otg_sram: sram-section@0000 {
486 compatible = "allwinner,sun4i-a10-sram-d";
487 reg = <0x0000 0x1000>;
488 status = "disabled";
489 };
490 };
491 };
493 dma: dma-controller@01c02000 {
494 compatible = "allwinner,sun4i-a10-dma";
495 reg = <0x01c02000 0x1000>;
496 interrupts = <27>;
497 clocks = <&ahb_gates 6>;
498 #dma-cells = <2>;
499 };
501 spi0: spi@01c05000 {
502 compatible = "allwinner,sun4i-a10-spi";
503 reg = <0x01c05000 0x1000>;
504 interrupts = <10>;
505 clocks = <&ahb_gates 20>, <&spi0_clk>;
506 clock-names = "ahb", "mod";
507 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
508 <&dma SUN4I_DMA_DEDICATED 26>;
509 dma-names = "rx", "tx";
510 status = "disabled";
511 #address-cells = <1>;
512 #size-cells = <0>;
513 };
515 spi1: spi@01c06000 {
516 compatible = "allwinner,sun4i-a10-spi";
517 reg = <0x01c06000 0x1000>;
518 interrupts = <11>;
519 clocks = <&ahb_gates 21>, <&spi1_clk>;
520 clock-names = "ahb", "mod";
521 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
522 <&dma SUN4I_DMA_DEDICATED 8>;
523 dma-names = "rx", "tx";
524 status = "disabled";
525 #address-cells = <1>;
526 #size-cells = <0>;
527 };
529 emac: ethernet@01c0b000 {
530 compatible = "allwinner,sun4i-a10-emac";
531 reg = <0x01c0b000 0x1000>;
532 interrupts = <55>;
533 clocks = <&ahb_gates 17>;
534 allwinner,sram = <&emac_sram 1>;
535 status = "disabled";
536 };
538 mdio: mdio@01c0b080 {
539 compatible = "allwinner,sun4i-a10-mdio";
540 reg = <0x01c0b080 0x14>;
541 status = "disabled";
542 #address-cells = <1>;
543 #size-cells = <0>;
544 };
546 mmc0: mmc@01c0f000 {
547 compatible = "allwinner,sun4i-a10-mmc";
548 reg = <0x01c0f000 0x1000>;
549 clocks = <&ahb_gates 8>,
550 <&mmc0_clk 0>,
551 <&mmc0_clk 1>,
552 <&mmc0_clk 2>;
553 clock-names = "ahb",
554 "mmc",
555 "output",
556 "sample";
557 interrupts = <32>;
558 status = "disabled";
559 #address-cells = <1>;
560 #size-cells = <0>;
561 };
563 mmc1: mmc@01c10000 {
564 compatible = "allwinner,sun4i-a10-mmc";
565 reg = <0x01c10000 0x1000>;
566 clocks = <&ahb_gates 9>,
567 <&mmc1_clk 0>,
568 <&mmc1_clk 1>,
569 <&mmc1_clk 2>;
570 clock-names = "ahb",
571 "mmc",
572 "output",
573 "sample";
574 interrupts = <33>;
575 status = "disabled";
576 #address-cells = <1>;
577 #size-cells = <0>;
578 };
580 mmc2: mmc@01c11000 {
581 compatible = "allwinner,sun4i-a10-mmc";
582 reg = <0x01c11000 0x1000>;
583 clocks = <&ahb_gates 10>,
584 <&mmc2_clk 0>,
585 <&mmc2_clk 1>,
586 <&mmc2_clk 2>;
587 clock-names = "ahb",
588 "mmc",
589 "output",
590 "sample";
591 interrupts = <34>;
592 status = "disabled";
593 #address-cells = <1>;
594 #size-cells = <0>;
595 };
597 mmc3: mmc@01c12000 {
598 compatible = "allwinner,sun4i-a10-mmc";
599 reg = <0x01c12000 0x1000>;
600 clocks = <&ahb_gates 11>,
601 <&mmc3_clk 0>,
602 <&mmc3_clk 1>,
603 <&mmc3_clk 2>;
604 clock-names = "ahb",
605 "mmc",
606 "output",
607 "sample";
608 interrupts = <35>;
609 status = "disabled";
610 #address-cells = <1>;
611 #size-cells = <0>;
612 };
614 usbphy: phy@01c13400 {
615 #phy-cells = <1>;
616 compatible = "allwinner,sun4i-a10-usb-phy";
617 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
618 reg-names = "phy_ctrl", "pmu1", "pmu2";
619 clocks = <&usb_clk 8>;
620 clock-names = "usb_phy";
621 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
622 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
623 status = "disabled";
624 };
626 ehci0: usb@01c14000 {
627 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
628 reg = <0x01c14000 0x100>;
629 interrupts = <39>;
630 clocks = <&ahb_gates 1>;
631 phys = <&usbphy 1>;
632 phy-names = "usb";
633 status = "disabled";
634 };
636 ohci0: usb@01c14400 {
637 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
638 reg = <0x01c14400 0x100>;
639 interrupts = <64>;
640 clocks = <&usb_clk 6>, <&ahb_gates 2>;
641 phys = <&usbphy 1>;
642 phy-names = "usb";
643 status = "disabled";
644 };
646 spi2: spi@01c17000 {
647 compatible = "allwinner,sun4i-a10-spi";
648 reg = <0x01c17000 0x1000>;
649 interrupts = <12>;
650 clocks = <&ahb_gates 22>, <&spi2_clk>;
651 clock-names = "ahb", "mod";
652 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
653 <&dma SUN4I_DMA_DEDICATED 28>;
654 dma-names = "rx", "tx";
655 status = "disabled";
656 #address-cells = <1>;
657 #size-cells = <0>;
658 };
660 ahci: sata@01c18000 {
661 compatible = "allwinner,sun4i-a10-ahci";
662 reg = <0x01c18000 0x1000>;
663 interrupts = <56>;
664 clocks = <&pll6 0>, <&ahb_gates 25>;
665 status = "disabled";
666 };
668 ehci1: usb@01c1c000 {
669 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
670 reg = <0x01c1c000 0x100>;
671 interrupts = <40>;
672 clocks = <&ahb_gates 3>;
673 phys = <&usbphy 2>;
674 phy-names = "usb";
675 status = "disabled";
676 };
678 ohci1: usb@01c1c400 {
679 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
680 reg = <0x01c1c400 0x100>;
681 interrupts = <65>;
682 clocks = <&usb_clk 7>, <&ahb_gates 4>;
683 phys = <&usbphy 2>;
684 phy-names = "usb";
685 status = "disabled";
686 };
688 spi3: spi@01c1f000 {
689 compatible = "allwinner,sun4i-a10-spi";
690 reg = <0x01c1f000 0x1000>;
691 interrupts = <50>;
692 clocks = <&ahb_gates 23>, <&spi3_clk>;
693 clock-names = "ahb", "mod";
694 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
695 <&dma SUN4I_DMA_DEDICATED 30>;
696 dma-names = "rx", "tx";
697 status = "disabled";
698 #address-cells = <1>;
699 #size-cells = <0>;
700 };
702 intc: interrupt-controller@01c20400 {
703 compatible = "allwinner,sun4i-a10-ic";
704 reg = <0x01c20400 0x400>;
705 interrupt-controller;
706 #interrupt-cells = <1>;
707 };
709 pio: pinctrl@01c20800 {
710 compatible = "allwinner,sun4i-a10-pinctrl";
711 reg = <0x01c20800 0x400>;
712 interrupts = <28>;
713 clocks = <&apb0_gates 5>;
714 gpio-controller;
715 interrupt-controller;
716 #interrupt-cells = <2>;
717 #size-cells = <0>;
718 #gpio-cells = <3>;
720 pwm0_pins_a: pwm0@0 {
721 allwinner,pins = "PB2";
722 allwinner,function = "pwm";
723 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
724 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
725 };
727 pwm1_pins_a: pwm1@0 {
728 allwinner,pins = "PI3";
729 allwinner,function = "pwm";
730 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
731 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
732 };
734 uart0_pins_a: uart0@0 {
735 allwinner,pins = "PB22", "PB23";
736 allwinner,function = "uart0";
737 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
738 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
739 };
741 uart0_pins_b: uart0@1 {
742 allwinner,pins = "PF2", "PF4";
743 allwinner,function = "uart0";
744 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
745 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
746 };
748 uart1_pins_a: uart1@0 {
749 allwinner,pins = "PA10", "PA11";
750 allwinner,function = "uart1";
751 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
752 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
753 };
755 i2c0_pins_a: i2c0@0 {
756 allwinner,pins = "PB0", "PB1";
757 allwinner,function = "i2c0";
758 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
759 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
760 };
762 i2c1_pins_a: i2c1@0 {
763 allwinner,pins = "PB18", "PB19";
764 allwinner,function = "i2c1";
765 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
766 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
767 };
769 i2c2_pins_a: i2c2@0 {
770 allwinner,pins = "PB20", "PB21";
771 allwinner,function = "i2c2";
772 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
773 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
774 };
776 emac_pins_a: emac0@0 {
777 allwinner,pins = "PA0", "PA1", "PA2",
778 "PA3", "PA4", "PA5", "PA6",
779 "PA7", "PA8", "PA9", "PA10",
780 "PA11", "PA12", "PA13", "PA14",
781 "PA15", "PA16";
782 allwinner,function = "emac";
783 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
784 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
785 };
787 mmc0_pins_a: mmc0@0 {
788 allwinner,pins = "PF0", "PF1", "PF2",
789 "PF3", "PF4", "PF5";
790 allwinner,function = "mmc0";
791 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
792 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
793 };
795 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
796 allwinner,pins = "PH1";
797 allwinner,function = "gpio_in";
798 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
799 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
800 };
802 ir0_rx_pins_a: ir0@0 {
803 allwinner,pins = "PB4";
804 allwinner,function = "ir0";
805 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
806 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
807 };
809 ir0_tx_pins_a: ir0@1 {
810 allwinner,pins = "PB3";
811 allwinner,function = "ir0";
812 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
813 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
814 };
816 ir1_rx_pins_a: ir1@0 {
817 allwinner,pins = "PB23";
818 allwinner,function = "ir1";
819 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
820 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
821 };
823 ir1_tx_pins_a: ir1@1 {
824 allwinner,pins = "PB22";
825 allwinner,function = "ir1";
826 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
827 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
828 };
830 spi0_pins_a: spi0@0 {
831 allwinner,pins = "PI11", "PI12", "PI13";
832 allwinner,function = "spi0";
833 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
834 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
835 };
837 spi0_cs0_pins_a: spi0_cs0@0 {
838 allwinner,pins = "PI10";
839 allwinner,function = "spi0";
840 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
841 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
842 };
844 spi1_pins_a: spi1@0 {
845 allwinner,pins = "PI17", "PI18", "PI19";
846 allwinner,function = "spi1";
847 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
848 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
849 };
851 spi1_cs0_pins_a: spi1_cs0@0 {
852 allwinner,pins = "PI16";
853 allwinner,function = "spi1";
854 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
855 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
856 };
858 spi2_pins_a: spi2@0 {
859 allwinner,pins = "PC20", "PC21", "PC22";
860 allwinner,function = "spi2";
861 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
862 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
863 };
865 spi2_pins_b: spi2@1 {
866 allwinner,pins = "PB15", "PB16", "PB17";
867 allwinner,function = "spi2";
868 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
869 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
870 };
872 spi2_cs0_pins_a: spi2_cs0@0 {
873 allwinner,pins = "PC19";
874 allwinner,function = "spi2";
875 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
876 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
877 };
879 spi2_cs0_pins_b: spi2_cs0@1 {
880 allwinner,pins = "PB14";
881 allwinner,function = "spi2";
882 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
883 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
884 };
886 ps20_pins_a: ps20@0 {
887 allwinner,pins = "PI20", "PI21";
888 allwinner,function = "ps2";
889 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
890 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
891 };
893 ps21_pins_a: ps21@0 {
894 allwinner,pins = "PH12", "PH13";
895 allwinner,function = "ps2";
896 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
897 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
898 };
899 };
901 timer@01c20c00 {
902 compatible = "allwinner,sun4i-a10-timer";
903 reg = <0x01c20c00 0x90>;
904 interrupts = <22>;
905 clocks = <&osc24M>;
906 };
908 wdt: watchdog@01c20c90 {
909 compatible = "allwinner,sun4i-a10-wdt";
910 reg = <0x01c20c90 0x10>;
911 };
913 rtc: rtc@01c20d00 {
914 compatible = "allwinner,sun4i-a10-rtc";
915 reg = <0x01c20d00 0x20>;
916 interrupts = <24>;
917 };
919 pwm: pwm@01c20e00 {
920 compatible = "allwinner,sun4i-a10-pwm";
921 reg = <0x01c20e00 0xc>;
922 clocks = <&osc24M>;
923 #pwm-cells = <3>;
924 status = "disabled";
925 };
927 ir0: ir@01c21800 {
928 compatible = "allwinner,sun4i-a10-ir";
929 clocks = <&apb0_gates 6>, <&ir0_clk>;
930 clock-names = "apb", "ir";
931 interrupts = <5>;
932 reg = <0x01c21800 0x40>;
933 status = "disabled";
934 };
936 ir1: ir@01c21c00 {
937 compatible = "allwinner,sun4i-a10-ir";
938 clocks = <&apb0_gates 7>, <&ir1_clk>;
939 clock-names = "apb", "ir";
940 interrupts = <6>;
941 reg = <0x01c21c00 0x40>;
942 status = "disabled";
943 };
945 lradc: lradc@01c22800 {
946 compatible = "allwinner,sun4i-a10-lradc-keys";
947 reg = <0x01c22800 0x100>;
948 interrupts = <31>;
949 status = "disabled";
950 };
952 sid: eeprom@01c23800 {
953 compatible = "allwinner,sun4i-a10-sid";
954 reg = <0x01c23800 0x10>;
955 };
957 rtp: rtp@01c25000 {
958 compatible = "allwinner,sun4i-a10-ts";
959 reg = <0x01c25000 0x100>;
960 interrupts = <29>;
961 #thermal-sensor-cells = <0>;
962 };
964 uart0: serial@01c28000 {
965 compatible = "snps,dw-apb-uart";
966 reg = <0x01c28000 0x400>;
967 interrupts = <1>;
968 reg-shift = <2>;
969 reg-io-width = <4>;
970 clocks = <&apb1_gates 16>;
971 status = "disabled";
972 };
974 uart1: serial@01c28400 {
975 compatible = "snps,dw-apb-uart";
976 reg = <0x01c28400 0x400>;
977 interrupts = <2>;
978 reg-shift = <2>;
979 reg-io-width = <4>;
980 clocks = <&apb1_gates 17>;
981 status = "disabled";
982 };
984 uart2: serial@01c28800 {
985 compatible = "snps,dw-apb-uart";
986 reg = <0x01c28800 0x400>;
987 interrupts = <3>;
988 reg-shift = <2>;
989 reg-io-width = <4>;
990 clocks = <&apb1_gates 18>;
991 status = "disabled";
992 };
994 uart3: serial@01c28c00 {
995 compatible = "snps,dw-apb-uart";
996 reg = <0x01c28c00 0x400>;
997 interrupts = <4>;
998 reg-shift = <2>;
999 reg-io-width = <4>;
1000 clocks = <&apb1_gates 19>;
1001 status = "disabled";
1002 };
1004 uart4: serial@01c29000 {
1005 compatible = "snps,dw-apb-uart";
1006 reg = <0x01c29000 0x400>;
1007 interrupts = <17>;
1008 reg-shift = <2>;
1009 reg-io-width = <4>;
1010 clocks = <&apb1_gates 20>;
1011 status = "disabled";
1012 };
1014 uart5: serial@01c29400 {
1015 compatible = "snps,dw-apb-uart";
1016 reg = <0x01c29400 0x400>;
1017 interrupts = <18>;
1018 reg-shift = <2>;
1019 reg-io-width = <4>;
1020 clocks = <&apb1_gates 21>;
1021 status = "disabled";
1022 };
1024 uart6: serial@01c29800 {
1025 compatible = "snps,dw-apb-uart";
1026 reg = <0x01c29800 0x400>;
1027 interrupts = <19>;
1028 reg-shift = <2>;
1029 reg-io-width = <4>;
1030 clocks = <&apb1_gates 22>;
1031 status = "disabled";
1032 };
1034 uart7: serial@01c29c00 {
1035 compatible = "snps,dw-apb-uart";
1036 reg = <0x01c29c00 0x400>;
1037 interrupts = <20>;
1038 reg-shift = <2>;
1039 reg-io-width = <4>;
1040 clocks = <&apb1_gates 23>;
1041 status = "disabled";
1042 };
1044 i2c0: i2c@01c2ac00 {
1045 compatible = "allwinner,sun4i-a10-i2c";
1046 reg = <0x01c2ac00 0x400>;
1047 interrupts = <7>;
1048 clocks = <&apb1_gates 0>;
1049 status = "disabled";
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1052 };
1054 i2c1: i2c@01c2b000 {
1055 compatible = "allwinner,sun4i-a10-i2c";
1056 reg = <0x01c2b000 0x400>;
1057 interrupts = <8>;
1058 clocks = <&apb1_gates 1>;
1059 status = "disabled";
1060 #address-cells = <1>;
1061 #size-cells = <0>;
1062 };
1064 i2c2: i2c@01c2b400 {
1065 compatible = "allwinner,sun4i-a10-i2c";
1066 reg = <0x01c2b400 0x400>;
1067 interrupts = <9>;
1068 clocks = <&apb1_gates 2>;
1069 status = "disabled";
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1072 };
1074 ps20: ps2@01c2a000 {
1075 compatible = "allwinner,sun4i-a10-ps2";
1076 reg = <0x01c2a000 0x400>;
1077 interrupts = <62>;
1078 clocks = <&apb1_gates 6>;
1079 status = "disabled";
1080 };
1082 ps21: ps2@01c2a400 {
1083 compatible = "allwinner,sun4i-a10-ps2";
1084 reg = <0x01c2a400 0x400>;
1085 interrupts = <63>;
1086 clocks = <&apb1_gates 7>;
1087 status = "disabled";
1088 };
1089 };
1090 };