| blob | 6a63f30c9a699d0e4620aac31f64247ad9c1f95b |
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/dma/sun4i-a10.h>
51 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 / {
54 interrupt-parent = <&gic>;
56 aliases {
57 ethernet0 = &gmac;
58 };
60 chosen {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
65 framebuffer@0 {
66 compatible = "allwinner,simple-framebuffer",
67 "simple-framebuffer";
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
70 <&ahb_gates 44>;
71 status = "disabled";
72 };
74 framebuffer@1 {
75 compatible = "allwinner,simple-framebuffer",
76 "simple-framebuffer";
77 allwinner,pipeline = "de_be0-lcd0";
78 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
79 status = "disabled";
80 };
82 framebuffer@2 {
83 compatible = "allwinner,simple-framebuffer",
84 "simple-framebuffer";
85 allwinner,pipeline = "de_be0-lcd0-tve0";
86 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
87 <&ahb_gates 44>;
88 status = "disabled";
89 };
90 };
92 cpus {
93 #address-cells = <1>;
94 #size-cells = <0>;
96 cpu0: cpu@0 {
97 compatible = "arm,cortex-a7";
98 device_type = "cpu";
99 reg = <0>;
100 clocks = <&cpu>;
101 clock-latency = <244144>; /* 8 32k periods */
102 operating-points = <
103 /* kHz uV */
104 960000 1400000
105 912000 1400000
106 864000 1300000
107 720000 1200000
108 528000 1100000
109 312000 1000000
110 144000 900000
111 >;
112 #cooling-cells = <2>;
113 cooling-min-level = <0>;
114 cooling-max-level = <6>;
115 };
117 cpu@1 {
118 compatible = "arm,cortex-a7";
119 device_type = "cpu";
120 reg = <1>;
121 };
122 };
124 thermal-zones {
125 cpu_thermal {
126 /* milliseconds */
127 polling-delay-passive = <250>;
128 polling-delay = <1000>;
129 thermal-sensors = <&rtp>;
131 cooling-maps {
132 map0 {
133 trip = <&cpu_alert0>;
134 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
135 };
136 };
138 trips {
139 cpu_alert0: cpu_alert0 {
140 /* milliCelsius */
141 temperature = <75000>;
142 hysteresis = <2000>;
143 type = "passive";
144 };
146 cpu_crit: cpu_crit {
147 /* milliCelsius */
148 temperature = <100000>;
149 hysteresis = <2000>;
150 type = "critical";
151 };
152 };
153 };
154 };
156 memory {
157 reg = <0x40000000 0x80000000>;
158 };
160 timer {
161 compatible = "arm,armv7-timer";
162 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
163 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
164 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
165 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
166 };
168 pmu {
169 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
170 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
172 };
174 clocks {
175 #address-cells = <1>;
176 #size-cells = <1>;
177 ranges;
179 osc24M: clk@01c20050 {
180 #clock-cells = <0>;
181 compatible = "allwinner,sun4i-a10-osc-clk";
182 reg = <0x01c20050 0x4>;
183 clock-frequency = <24000000>;
184 clock-output-names = "osc24M";
185 };
187 osc32k: clk@0 {
188 #clock-cells = <0>;
189 compatible = "fixed-clock";
190 clock-frequency = <32768>;
191 clock-output-names = "osc32k";
192 };
194 pll1: clk@01c20000 {
195 #clock-cells = <0>;
196 compatible = "allwinner,sun4i-a10-pll1-clk";
197 reg = <0x01c20000 0x4>;
198 clocks = <&osc24M>;
199 clock-output-names = "pll1";
200 };
202 pll4: clk@01c20018 {
203 #clock-cells = <0>;
204 compatible = "allwinner,sun7i-a20-pll4-clk";
205 reg = <0x01c20018 0x4>;
206 clocks = <&osc24M>;
207 clock-output-names = "pll4";
208 };
210 pll5: clk@01c20020 {
211 #clock-cells = <1>;
212 compatible = "allwinner,sun4i-a10-pll5-clk";
213 reg = <0x01c20020 0x4>;
214 clocks = <&osc24M>;
215 clock-output-names = "pll5_ddr", "pll5_other";
216 };
218 pll6: clk@01c20028 {
219 #clock-cells = <1>;
220 compatible = "allwinner,sun4i-a10-pll6-clk";
221 reg = <0x01c20028 0x4>;
222 clocks = <&osc24M>;
223 clock-output-names = "pll6_sata", "pll6_other", "pll6",
224 "pll6_div_4";
225 };
227 pll8: clk@01c20040 {
228 #clock-cells = <0>;
229 compatible = "allwinner,sun7i-a20-pll4-clk";
230 reg = <0x01c20040 0x4>;
231 clocks = <&osc24M>;
232 clock-output-names = "pll8";
233 };
235 cpu: cpu@01c20054 {
236 #clock-cells = <0>;
237 compatible = "allwinner,sun4i-a10-cpu-clk";
238 reg = <0x01c20054 0x4>;
239 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
240 clock-output-names = "cpu";
241 };
243 axi: axi@01c20054 {
244 #clock-cells = <0>;
245 compatible = "allwinner,sun4i-a10-axi-clk";
246 reg = <0x01c20054 0x4>;
247 clocks = <&cpu>;
248 clock-output-names = "axi";
249 };
251 ahb: ahb@01c20054 {
252 #clock-cells = <0>;
253 compatible = "allwinner,sun5i-a13-ahb-clk";
254 reg = <0x01c20054 0x4>;
255 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
256 clock-output-names = "ahb";
257 /*
258 * Use PLL6 as parent, instead of CPU/AXI
259 * which has rate changes due to cpufreq
260 */
261 assigned-clocks = <&ahb>;
262 assigned-clock-parents = <&pll6 3>;
263 };
265 ahb_gates: clk@01c20060 {
266 #clock-cells = <1>;
267 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
268 reg = <0x01c20060 0x8>;
269 clocks = <&ahb>;
270 clock-output-names = "ahb_usb0", "ahb_ehci0",
271 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
272 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
273 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
274 "ahb_nand", "ahb_sdram", "ahb_ace",
275 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
276 "ahb_spi2", "ahb_spi3", "ahb_sata",
277 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
278 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
279 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
280 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
281 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
282 "ahb_mali";
283 };
285 apb0: apb0@01c20054 {
286 #clock-cells = <0>;
287 compatible = "allwinner,sun4i-a10-apb0-clk";
288 reg = <0x01c20054 0x4>;
289 clocks = <&ahb>;
290 clock-output-names = "apb0";
291 };
293 apb0_gates: clk@01c20068 {
294 #clock-cells = <1>;
295 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
296 reg = <0x01c20068 0x4>;
297 clocks = <&apb0>;
298 clock-output-names = "apb0_codec", "apb0_spdif",
299 "apb0_ac97", "apb0_iis0", "apb0_iis1",
300 "apb0_pio", "apb0_ir0", "apb0_ir1",
301 "apb0_iis2", "apb0_keypad";
302 };
304 apb1: clk@01c20058 {
305 #clock-cells = <0>;
306 compatible = "allwinner,sun4i-a10-apb1-clk";
307 reg = <0x01c20058 0x4>;
308 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
309 clock-output-names = "apb1";
310 };
312 apb1_gates: clk@01c2006c {
313 #clock-cells = <1>;
314 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
315 reg = <0x01c2006c 0x4>;
316 clocks = <&apb1>;
317 clock-output-names = "apb1_i2c0", "apb1_i2c1",
318 "apb1_i2c2", "apb1_i2c3", "apb1_can",
319 "apb1_scr", "apb1_ps20", "apb1_ps21",
320 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
321 "apb1_uart2", "apb1_uart3", "apb1_uart4",
322 "apb1_uart5", "apb1_uart6", "apb1_uart7";
323 };
325 nand_clk: clk@01c20080 {
326 #clock-cells = <0>;
327 compatible = "allwinner,sun4i-a10-mod0-clk";
328 reg = <0x01c20080 0x4>;
329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
330 clock-output-names = "nand";
331 };
333 ms_clk: clk@01c20084 {
334 #clock-cells = <0>;
335 compatible = "allwinner,sun4i-a10-mod0-clk";
336 reg = <0x01c20084 0x4>;
337 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
338 clock-output-names = "ms";
339 };
341 mmc0_clk: clk@01c20088 {
342 #clock-cells = <1>;
343 compatible = "allwinner,sun4i-a10-mmc-clk";
344 reg = <0x01c20088 0x4>;
345 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
346 clock-output-names = "mmc0",
347 "mmc0_output",
348 "mmc0_sample";
349 };
351 mmc1_clk: clk@01c2008c {
352 #clock-cells = <1>;
353 compatible = "allwinner,sun4i-a10-mmc-clk";
354 reg = <0x01c2008c 0x4>;
355 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
356 clock-output-names = "mmc1",
357 "mmc1_output",
358 "mmc1_sample";
359 };
361 mmc2_clk: clk@01c20090 {
362 #clock-cells = <1>;
363 compatible = "allwinner,sun4i-a10-mmc-clk";
364 reg = <0x01c20090 0x4>;
365 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
366 clock-output-names = "mmc2",
367 "mmc2_output",
368 "mmc2_sample";
369 };
371 mmc3_clk: clk@01c20094 {
372 #clock-cells = <1>;
373 compatible = "allwinner,sun4i-a10-mmc-clk";
374 reg = <0x01c20094 0x4>;
375 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
376 clock-output-names = "mmc3",
377 "mmc3_output",
378 "mmc3_sample";
379 };
381 ts_clk: clk@01c20098 {
382 #clock-cells = <0>;
383 compatible = "allwinner,sun4i-a10-mod0-clk";
384 reg = <0x01c20098 0x4>;
385 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
386 clock-output-names = "ts";
387 };
389 ss_clk: clk@01c2009c {
390 #clock-cells = <0>;
391 compatible = "allwinner,sun4i-a10-mod0-clk";
392 reg = <0x01c2009c 0x4>;
393 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
394 clock-output-names = "ss";
395 };
397 spi0_clk: clk@01c200a0 {
398 #clock-cells = <0>;
399 compatible = "allwinner,sun4i-a10-mod0-clk";
400 reg = <0x01c200a0 0x4>;
401 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
402 clock-output-names = "spi0";
403 };
405 spi1_clk: clk@01c200a4 {
406 #clock-cells = <0>;
407 compatible = "allwinner,sun4i-a10-mod0-clk";
408 reg = <0x01c200a4 0x4>;
409 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
410 clock-output-names = "spi1";
411 };
413 spi2_clk: clk@01c200a8 {
414 #clock-cells = <0>;
415 compatible = "allwinner,sun4i-a10-mod0-clk";
416 reg = <0x01c200a8 0x4>;
417 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
418 clock-output-names = "spi2";
419 };
421 pata_clk: clk@01c200ac {
422 #clock-cells = <0>;
423 compatible = "allwinner,sun4i-a10-mod0-clk";
424 reg = <0x01c200ac 0x4>;
425 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
426 clock-output-names = "pata";
427 };
429 ir0_clk: clk@01c200b0 {
430 #clock-cells = <0>;
431 compatible = "allwinner,sun4i-a10-mod0-clk";
432 reg = <0x01c200b0 0x4>;
433 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
434 clock-output-names = "ir0";
435 };
437 ir1_clk: clk@01c200b4 {
438 #clock-cells = <0>;
439 compatible = "allwinner,sun4i-a10-mod0-clk";
440 reg = <0x01c200b4 0x4>;
441 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
442 clock-output-names = "ir1";
443 };
445 usb_clk: clk@01c200cc {
446 #clock-cells = <1>;
447 #reset-cells = <1>;
448 compatible = "allwinner,sun4i-a10-usb-clk";
449 reg = <0x01c200cc 0x4>;
450 clocks = <&pll6 1>;
451 clock-output-names = "usb_ohci0", "usb_ohci1",
452 "usb_phy";
453 };
455 spi3_clk: clk@01c200d4 {
456 #clock-cells = <0>;
457 compatible = "allwinner,sun4i-a10-mod0-clk";
458 reg = <0x01c200d4 0x4>;
459 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
460 clock-output-names = "spi3";
461 };
463 mbus_clk: clk@01c2015c {
464 #clock-cells = <0>;
465 compatible = "allwinner,sun5i-a13-mbus-clk";
466 reg = <0x01c2015c 0x4>;
467 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
468 clock-output-names = "mbus";
469 };
471 /*
472 * The following two are dummy clocks, placeholders
473 * used in the gmac_tx clock. The gmac driver will
474 * choose one parent depending on the PHY interface
475 * mode, using clk_set_rate auto-reparenting.
476 *
477 * The actual TX clock rate is not controlled by the
478 * gmac_tx clock.
479 */
480 mii_phy_tx_clk: clk@2 {
481 #clock-cells = <0>;
482 compatible = "fixed-clock";
483 clock-frequency = <25000000>;
484 clock-output-names = "mii_phy_tx";
485 };
487 gmac_int_tx_clk: clk@3 {
488 #clock-cells = <0>;
489 compatible = "fixed-clock";
490 clock-frequency = <125000000>;
491 clock-output-names = "gmac_int_tx";
492 };
494 gmac_tx_clk: clk@01c20164 {
495 #clock-cells = <0>;
496 compatible = "allwinner,sun7i-a20-gmac-clk";
497 reg = <0x01c20164 0x4>;
498 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
499 clock-output-names = "gmac_tx";
500 };
502 /*
503 * Dummy clock used by output clocks
504 */
505 osc24M_32k: clk@1 {
506 #clock-cells = <0>;
507 compatible = "fixed-factor-clock";
508 clock-div = <750>;
509 clock-mult = <1>;
510 clocks = <&osc24M>;
511 clock-output-names = "osc24M_32k";
512 };
514 clk_out_a: clk@01c201f0 {
515 #clock-cells = <0>;
516 compatible = "allwinner,sun7i-a20-out-clk";
517 reg = <0x01c201f0 0x4>;
518 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
519 clock-output-names = "clk_out_a";
520 };
522 clk_out_b: clk@01c201f4 {
523 #clock-cells = <0>;
524 compatible = "allwinner,sun7i-a20-out-clk";
525 reg = <0x01c201f4 0x4>;
526 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
527 clock-output-names = "clk_out_b";
528 };
529 };
531 soc@01c00000 {
532 compatible = "simple-bus";
533 #address-cells = <1>;
534 #size-cells = <1>;
535 ranges;
537 sram-controller@01c00000 {
538 compatible = "allwinner,sun4i-a10-sram-controller";
539 reg = <0x01c00000 0x30>;
540 #address-cells = <1>;
541 #size-cells = <1>;
542 ranges;
544 sram_a: sram@00000000 {
545 compatible = "mmio-sram";
546 reg = <0x00000000 0xc000>;
547 #address-cells = <1>;
548 #size-cells = <1>;
549 ranges = <0 0x00000000 0xc000>;
551 emac_sram: sram-section@8000 {
552 compatible = "allwinner,sun4i-a10-sram-a3-a4";
553 reg = <0x8000 0x4000>;
554 status = "disabled";
555 };
556 };
558 sram_d: sram@00010000 {
559 compatible = "mmio-sram";
560 reg = <0x00010000 0x1000>;
561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges = <0 0x00010000 0x1000>;
565 otg_sram: sram-section@0000 {
566 compatible = "allwinner,sun4i-a10-sram-d";
567 reg = <0x0000 0x1000>;
568 status = "disabled";
569 };
570 };
571 };
573 nmi_intc: interrupt-controller@01c00030 {
574 compatible = "allwinner,sun7i-a20-sc-nmi";
575 interrupt-controller;
576 #interrupt-cells = <2>;
577 reg = <0x01c00030 0x0c>;
578 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
579 };
581 dma: dma-controller@01c02000 {
582 compatible = "allwinner,sun4i-a10-dma";
583 reg = <0x01c02000 0x1000>;
584 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&ahb_gates 6>;
586 #dma-cells = <2>;
587 };
589 spi0: spi@01c05000 {
590 compatible = "allwinner,sun4i-a10-spi";
591 reg = <0x01c05000 0x1000>;
592 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&ahb_gates 20>, <&spi0_clk>;
594 clock-names = "ahb", "mod";
595 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
596 <&dma SUN4I_DMA_DEDICATED 26>;
597 dma-names = "rx", "tx";
598 status = "disabled";
599 #address-cells = <1>;
600 #size-cells = <0>;
601 };
603 spi1: spi@01c06000 {
604 compatible = "allwinner,sun4i-a10-spi";
605 reg = <0x01c06000 0x1000>;
606 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&ahb_gates 21>, <&spi1_clk>;
608 clock-names = "ahb", "mod";
609 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
610 <&dma SUN4I_DMA_DEDICATED 8>;
611 dma-names = "rx", "tx";
612 status = "disabled";
613 #address-cells = <1>;
614 #size-cells = <0>;
615 };
617 emac: ethernet@01c0b000 {
618 compatible = "allwinner,sun4i-a10-emac";
619 reg = <0x01c0b000 0x1000>;
620 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&ahb_gates 17>;
622 allwinner,sram = <&emac_sram 1>;
623 status = "disabled";
624 };
626 mdio: mdio@01c0b080 {
627 compatible = "allwinner,sun4i-a10-mdio";
628 reg = <0x01c0b080 0x14>;
629 status = "disabled";
630 #address-cells = <1>;
631 #size-cells = <0>;
632 };
634 mmc0: mmc@01c0f000 {
635 compatible = "allwinner,sun5i-a13-mmc";
636 reg = <0x01c0f000 0x1000>;
637 clocks = <&ahb_gates 8>,
638 <&mmc0_clk 0>,
639 <&mmc0_clk 1>,
640 <&mmc0_clk 2>;
641 clock-names = "ahb",
642 "mmc",
643 "output",
644 "sample";
645 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
646 status = "disabled";
647 #address-cells = <1>;
648 #size-cells = <0>;
649 };
651 mmc1: mmc@01c10000 {
652 compatible = "allwinner,sun5i-a13-mmc";
653 reg = <0x01c10000 0x1000>;
654 clocks = <&ahb_gates 9>,
655 <&mmc1_clk 0>,
656 <&mmc1_clk 1>,
657 <&mmc1_clk 2>;
658 clock-names = "ahb",
659 "mmc",
660 "output",
661 "sample";
662 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
663 status = "disabled";
664 #address-cells = <1>;
665 #size-cells = <0>;
666 };
668 mmc2: mmc@01c11000 {
669 compatible = "allwinner,sun5i-a13-mmc";
670 reg = <0x01c11000 0x1000>;
671 clocks = <&ahb_gates 10>,
672 <&mmc2_clk 0>,
673 <&mmc2_clk 1>,
674 <&mmc2_clk 2>;
675 clock-names = "ahb",
676 "mmc",
677 "output",
678 "sample";
679 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
680 status = "disabled";
681 #address-cells = <1>;
682 #size-cells = <0>;
683 };
685 mmc3: mmc@01c12000 {
686 compatible = "allwinner,sun5i-a13-mmc";
687 reg = <0x01c12000 0x1000>;
688 clocks = <&ahb_gates 11>,
689 <&mmc3_clk 0>,
690 <&mmc3_clk 1>,
691 <&mmc3_clk 2>;
692 clock-names = "ahb",
693 "mmc",
694 "output",
695 "sample";
696 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
697 status = "disabled";
698 #address-cells = <1>;
699 #size-cells = <0>;
700 };
702 usbphy: phy@01c13400 {
703 #phy-cells = <1>;
704 compatible = "allwinner,sun7i-a20-usb-phy";
705 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
706 reg-names = "phy_ctrl", "pmu1", "pmu2";
707 clocks = <&usb_clk 8>;
708 clock-names = "usb_phy";
709 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
710 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
711 status = "disabled";
712 };
714 ehci0: usb@01c14000 {
715 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
716 reg = <0x01c14000 0x100>;
717 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&ahb_gates 1>;
719 phys = <&usbphy 1>;
720 phy-names = "usb";
721 status = "disabled";
722 };
724 ohci0: usb@01c14400 {
725 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
726 reg = <0x01c14400 0x100>;
727 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&usb_clk 6>, <&ahb_gates 2>;
729 phys = <&usbphy 1>;
730 phy-names = "usb";
731 status = "disabled";
732 };
734 spi2: spi@01c17000 {
735 compatible = "allwinner,sun4i-a10-spi";
736 reg = <0x01c17000 0x1000>;
737 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&ahb_gates 22>, <&spi2_clk>;
739 clock-names = "ahb", "mod";
740 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
741 <&dma SUN4I_DMA_DEDICATED 28>;
742 dma-names = "rx", "tx";
743 status = "disabled";
744 #address-cells = <1>;
745 #size-cells = <0>;
746 };
748 ahci: sata@01c18000 {
749 compatible = "allwinner,sun4i-a10-ahci";
750 reg = <0x01c18000 0x1000>;
751 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&pll6 0>, <&ahb_gates 25>;
753 status = "disabled";
754 };
756 ehci1: usb@01c1c000 {
757 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
758 reg = <0x01c1c000 0x100>;
759 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&ahb_gates 3>;
761 phys = <&usbphy 2>;
762 phy-names = "usb";
763 status = "disabled";
764 };
766 ohci1: usb@01c1c400 {
767 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
768 reg = <0x01c1c400 0x100>;
769 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&usb_clk 7>, <&ahb_gates 4>;
771 phys = <&usbphy 2>;
772 phy-names = "usb";
773 status = "disabled";
774 };
776 spi3: spi@01c1f000 {
777 compatible = "allwinner,sun4i-a10-spi";
778 reg = <0x01c1f000 0x1000>;
779 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&ahb_gates 23>, <&spi3_clk>;
781 clock-names = "ahb", "mod";
782 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
783 <&dma SUN4I_DMA_DEDICATED 30>;
784 dma-names = "rx", "tx";
785 status = "disabled";
786 #address-cells = <1>;
787 #size-cells = <0>;
788 };
790 pio: pinctrl@01c20800 {
791 compatible = "allwinner,sun7i-a20-pinctrl";
792 reg = <0x01c20800 0x400>;
793 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&apb0_gates 5>;
795 gpio-controller;
796 interrupt-controller;
797 #interrupt-cells = <2>;
798 #size-cells = <0>;
799 #gpio-cells = <3>;
801 pwm0_pins_a: pwm0@0 {
802 allwinner,pins = "PB2";
803 allwinner,function = "pwm";
804 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
805 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
806 };
808 pwm1_pins_a: pwm1@0 {
809 allwinner,pins = "PI3";
810 allwinner,function = "pwm";
811 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
812 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
813 };
815 uart0_pins_a: uart0@0 {
816 allwinner,pins = "PB22", "PB23";
817 allwinner,function = "uart0";
818 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
819 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
820 };
822 uart2_pins_a: uart2@0 {
823 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
824 allwinner,function = "uart2";
825 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
826 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
827 };
829 uart3_pins_a: uart3@0 {
830 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
831 allwinner,function = "uart3";
832 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
833 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
834 };
836 uart3_pins_b: uart3@1 {
837 allwinner,pins = "PH0", "PH1";
838 allwinner,function = "uart3";
839 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
840 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
841 };
843 uart4_pins_a: uart4@0 {
844 allwinner,pins = "PG10", "PG11";
845 allwinner,function = "uart4";
846 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
847 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
848 };
850 uart4_pins_b: uart4@1 {
851 allwinner,pins = "PH4", "PH5";
852 allwinner,function = "uart4";
853 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
854 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
855 };
857 uart5_pins_a: uart5@0 {
858 allwinner,pins = "PI10", "PI11";
859 allwinner,function = "uart5";
860 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
861 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
862 };
864 uart6_pins_a: uart6@0 {
865 allwinner,pins = "PI12", "PI13";
866 allwinner,function = "uart6";
867 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
868 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
869 };
871 uart7_pins_a: uart7@0 {
872 allwinner,pins = "PI20", "PI21";
873 allwinner,function = "uart7";
874 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
875 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
876 };
878 i2c0_pins_a: i2c0@0 {
879 allwinner,pins = "PB0", "PB1";
880 allwinner,function = "i2c0";
881 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
882 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
883 };
885 i2c1_pins_a: i2c1@0 {
886 allwinner,pins = "PB18", "PB19";
887 allwinner,function = "i2c1";
888 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
889 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
890 };
892 i2c2_pins_a: i2c2@0 {
893 allwinner,pins = "PB20", "PB21";
894 allwinner,function = "i2c2";
895 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
896 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
897 };
899 i2c3_pins_a: i2c3@0 {
900 allwinner,pins = "PI0", "PI1";
901 allwinner,function = "i2c3";
902 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
903 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
904 };
906 emac_pins_a: emac0@0 {
907 allwinner,pins = "PA0", "PA1", "PA2",
908 "PA3", "PA4", "PA5", "PA6",
909 "PA7", "PA8", "PA9", "PA10",
910 "PA11", "PA12", "PA13", "PA14",
911 "PA15", "PA16";
912 allwinner,function = "emac";
913 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
914 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
915 };
917 clk_out_a_pins_a: clk_out_a@0 {
918 allwinner,pins = "PI12";
919 allwinner,function = "clk_out_a";
920 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
921 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
922 };
924 clk_out_b_pins_a: clk_out_b@0 {
925 allwinner,pins = "PI13";
926 allwinner,function = "clk_out_b";
927 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
928 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
929 };
931 gmac_pins_mii_a: gmac_mii@0 {
932 allwinner,pins = "PA0", "PA1", "PA2",
933 "PA3", "PA4", "PA5", "PA6",
934 "PA7", "PA8", "PA9", "PA10",
935 "PA11", "PA12", "PA13", "PA14",
936 "PA15", "PA16";
937 allwinner,function = "gmac";
938 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
939 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
940 };
942 gmac_pins_rgmii_a: gmac_rgmii@0 {
943 allwinner,pins = "PA0", "PA1", "PA2",
944 "PA3", "PA4", "PA5", "PA6",
945 "PA7", "PA8", "PA10",
946 "PA11", "PA12", "PA13",
947 "PA15", "PA16";
948 allwinner,function = "gmac";
949 /*
950 * data lines in RGMII mode use DDR mode
951 * and need a higher signal drive strength
952 */
953 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
954 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
955 };
957 spi0_pins_a: spi0@0 {
958 allwinner,pins = "PI11", "PI12", "PI13";
959 allwinner,function = "spi0";
960 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
961 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
962 };
964 spi0_cs0_pins_a: spi0_cs0@0 {
965 allwinner,pins = "PI10";
966 allwinner,function = "spi0";
967 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
968 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
969 };
971 spi0_cs1_pins_a: spi0_cs1@0 {
972 allwinner,pins = "PI14";
973 allwinner,function = "spi0";
974 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
975 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
976 };
978 spi1_pins_a: spi1@0 {
979 allwinner,pins = "PI17", "PI18", "PI19";
980 allwinner,function = "spi1";
981 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
982 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
983 };
985 spi1_cs0_pins_a: spi1_cs0@0 {
986 allwinner,pins = "PI16";
987 allwinner,function = "spi1";
988 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
989 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
990 };
992 spi2_pins_a: spi2@0 {
993 allwinner,pins = "PC20", "PC21", "PC22";
994 allwinner,function = "spi2";
995 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
996 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
997 };
999 spi2_pins_b: spi2@1 {
1000 allwinner,pins = "PB15", "PB16", "PB17";
1001 allwinner,function = "spi2";
1002 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1003 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1004 };
1006 spi2_cs0_pins_a: spi2_cs0@0 {
1007 allwinner,pins = "PC19";
1008 allwinner,function = "spi2";
1009 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1010 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1011 };
1013 spi2_cs0_pins_b: spi2_cs0@1 {
1014 allwinner,pins = "PB14";
1015 allwinner,function = "spi2";
1016 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1017 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1018 };
1020 mmc0_pins_a: mmc0@0 {
1021 allwinner,pins = "PF0", "PF1", "PF2",
1022 "PF3", "PF4", "PF5";
1023 allwinner,function = "mmc0";
1024 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1025 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1026 };
1028 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1029 allwinner,pins = "PH1";
1030 allwinner,function = "gpio_in";
1031 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1032 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1033 };
1035 mmc2_pins_a: mmc2@0 {
1036 allwinner,pins = "PC6", "PC7", "PC8",
1037 "PC9", "PC10", "PC11";
1038 allwinner,function = "mmc2";
1039 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1040 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1041 };
1043 mmc3_pins_a: mmc3@0 {
1044 allwinner,pins = "PI4", "PI5", "PI6",
1045 "PI7", "PI8", "PI9";
1046 allwinner,function = "mmc3";
1047 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1048 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1049 };
1051 ir0_rx_pins_a: ir0@0 {
1052 allwinner,pins = "PB4";
1053 allwinner,function = "ir0";
1054 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1055 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1056 };
1058 ir0_tx_pins_a: ir0@1 {
1059 allwinner,pins = "PB3";
1060 allwinner,function = "ir0";
1061 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1062 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1063 };
1065 ir1_rx_pins_a: ir1@0 {
1066 allwinner,pins = "PB23";
1067 allwinner,function = "ir1";
1068 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1069 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1070 };
1072 ir1_tx_pins_a: ir1@1 {
1073 allwinner,pins = "PB22";
1074 allwinner,function = "ir1";
1075 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1076 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1077 };
1079 ps20_pins_a: ps20@0 {
1080 allwinner,pins = "PI20", "PI21";
1081 allwinner,function = "ps2";
1082 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1083 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1084 };
1086 ps21_pins_a: ps21@0 {
1087 allwinner,pins = "PH12", "PH13";
1088 allwinner,function = "ps2";
1089 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1090 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1091 };
1092 };
1094 timer@01c20c00 {
1095 compatible = "allwinner,sun4i-a10-timer";
1096 reg = <0x01c20c00 0x90>;
1097 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1101 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1102 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&osc24M>;
1104 };
1106 wdt: watchdog@01c20c90 {
1107 compatible = "allwinner,sun4i-a10-wdt";
1108 reg = <0x01c20c90 0x10>;
1109 };
1111 rtc: rtc@01c20d00 {
1112 compatible = "allwinner,sun7i-a20-rtc";
1113 reg = <0x01c20d00 0x20>;
1114 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1115 };
1117 pwm: pwm@01c20e00 {
1118 compatible = "allwinner,sun7i-a20-pwm";
1119 reg = <0x01c20e00 0xc>;
1120 clocks = <&osc24M>;
1121 #pwm-cells = <3>;
1122 status = "disabled";
1123 };
1125 ir0: ir@01c21800 {
1126 compatible = "allwinner,sun4i-a10-ir";
1127 clocks = <&apb0_gates 6>, <&ir0_clk>;
1128 clock-names = "apb", "ir";
1129 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1130 reg = <0x01c21800 0x40>;
1131 status = "disabled";
1132 };
1134 ir1: ir@01c21c00 {
1135 compatible = "allwinner,sun4i-a10-ir";
1136 clocks = <&apb0_gates 7>, <&ir1_clk>;
1137 clock-names = "apb", "ir";
1138 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1139 reg = <0x01c21c00 0x40>;
1140 status = "disabled";
1141 };
1143 lradc: lradc@01c22800 {
1144 compatible = "allwinner,sun4i-a10-lradc-keys";
1145 reg = <0x01c22800 0x100>;
1146 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1147 status = "disabled";
1148 };
1150 sid: eeprom@01c23800 {
1151 compatible = "allwinner,sun7i-a20-sid";
1152 reg = <0x01c23800 0x200>;
1153 };
1155 rtp: rtp@01c25000 {
1156 compatible = "allwinner,sun5i-a13-ts";
1157 reg = <0x01c25000 0x100>;
1158 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1159 #thermal-sensor-cells = <0>;
1160 };
1162 uart0: serial@01c28000 {
1163 compatible = "snps,dw-apb-uart";
1164 reg = <0x01c28000 0x400>;
1165 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1166 reg-shift = <2>;
1167 reg-io-width = <4>;
1168 clocks = <&apb1_gates 16>;
1169 status = "disabled";
1170 };
1172 uart1: serial@01c28400 {
1173 compatible = "snps,dw-apb-uart";
1174 reg = <0x01c28400 0x400>;
1175 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1176 reg-shift = <2>;
1177 reg-io-width = <4>;
1178 clocks = <&apb1_gates 17>;
1179 status = "disabled";
1180 };
1182 uart2: serial@01c28800 {
1183 compatible = "snps,dw-apb-uart";
1184 reg = <0x01c28800 0x400>;
1185 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1186 reg-shift = <2>;
1187 reg-io-width = <4>;
1188 clocks = <&apb1_gates 18>;
1189 status = "disabled";
1190 };
1192 uart3: serial@01c28c00 {
1193 compatible = "snps,dw-apb-uart";
1194 reg = <0x01c28c00 0x400>;
1195 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1196 reg-shift = <2>;
1197 reg-io-width = <4>;
1198 clocks = <&apb1_gates 19>;
1199 status = "disabled";
1200 };
1202 uart4: serial@01c29000 {
1203 compatible = "snps,dw-apb-uart";
1204 reg = <0x01c29000 0x400>;
1205 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1206 reg-shift = <2>;
1207 reg-io-width = <4>;
1208 clocks = <&apb1_gates 20>;
1209 status = "disabled";
1210 };
1212 uart5: serial@01c29400 {
1213 compatible = "snps,dw-apb-uart";
1214 reg = <0x01c29400 0x400>;
1215 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1216 reg-shift = <2>;
1217 reg-io-width = <4>;
1218 clocks = <&apb1_gates 21>;
1219 status = "disabled";
1220 };
1222 uart6: serial@01c29800 {
1223 compatible = "snps,dw-apb-uart";
1224 reg = <0x01c29800 0x400>;
1225 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1226 reg-shift = <2>;
1227 reg-io-width = <4>;
1228 clocks = <&apb1_gates 22>;
1229 status = "disabled";
1230 };
1232 uart7: serial@01c29c00 {
1233 compatible = "snps,dw-apb-uart";
1234 reg = <0x01c29c00 0x400>;
1235 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1236 reg-shift = <2>;
1237 reg-io-width = <4>;
1238 clocks = <&apb1_gates 23>;
1239 status = "disabled";
1240 };
1242 i2c0: i2c@01c2ac00 {
1243 compatible = "allwinner,sun7i-a20-i2c",
1244 "allwinner,sun4i-a10-i2c";
1245 reg = <0x01c2ac00 0x400>;
1246 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1247 clocks = <&apb1_gates 0>;
1248 status = "disabled";
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1251 };
1253 i2c1: i2c@01c2b000 {
1254 compatible = "allwinner,sun7i-a20-i2c",
1255 "allwinner,sun4i-a10-i2c";
1256 reg = <0x01c2b000 0x400>;
1257 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&apb1_gates 1>;
1259 status = "disabled";
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1262 };
1264 i2c2: i2c@01c2b400 {
1265 compatible = "allwinner,sun7i-a20-i2c",
1266 "allwinner,sun4i-a10-i2c";
1267 reg = <0x01c2b400 0x400>;
1268 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&apb1_gates 2>;
1270 status = "disabled";
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1273 };
1275 i2c3: i2c@01c2b800 {
1276 compatible = "allwinner,sun7i-a20-i2c",
1277 "allwinner,sun4i-a10-i2c";
1278 reg = <0x01c2b800 0x400>;
1279 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1280 clocks = <&apb1_gates 3>;
1281 status = "disabled";
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1284 };
1286 i2c4: i2c@01c2c000 {
1287 compatible = "allwinner,sun7i-a20-i2c",
1288 "allwinner,sun4i-a10-i2c";
1289 reg = <0x01c2c000 0x400>;
1290 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1291 clocks = <&apb1_gates 15>;
1292 status = "disabled";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1295 };
1297 gmac: ethernet@01c50000 {
1298 compatible = "allwinner,sun7i-a20-gmac";
1299 reg = <0x01c50000 0x10000>;
1300 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1301 interrupt-names = "macirq";
1302 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1303 clock-names = "stmmaceth", "allwinner_gmac_tx";
1304 snps,pbl = <2>;
1305 snps,fixed-burst;
1306 snps,force_sf_dma_mode;
1307 status = "disabled";
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310 };
1312 hstimer@01c60000 {
1313 compatible = "allwinner,sun7i-a20-hstimer";
1314 reg = <0x01c60000 0x1000>;
1315 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1316 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1319 clocks = <&ahb_gates 28>;
1320 };
1322 gic: interrupt-controller@01c81000 {
1323 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1324 reg = <0x01c81000 0x1000>,
1325 <0x01c82000 0x1000>,
1326 <0x01c84000 0x2000>,
1327 <0x01c86000 0x2000>;
1328 interrupt-controller;
1329 #interrupt-cells = <3>;
1330 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1331 };
1333 ps20: ps2@01c2a000 {
1334 compatible = "allwinner,sun4i-a10-ps2";
1335 reg = <0x01c2a000 0x400>;
1336 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1337 clocks = <&apb1_gates 6>;
1338 status = "disabled";
1339 };
1341 ps21: ps2@01c2a400 {
1342 compatible = "allwinner,sun4i-a10-ps2";
1343 reg = <0x01c2a400 0x400>;
1344 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&apb1_gates 7>;
1346 status = "disabled";
1347 };
1348 };
1349 };