arch/arm/mach-rockchip/platsmp.c

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/smp.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/regmap.h>
  23 #include <linux/mfd/syscon.h>
  24
  25 #include <linux/reset.h>
  26 #include <linux/cpu.h>
  27 #include <asm/cacheflush.h>
  28 #include <asm/cp15.h>
  29 #include <asm/smp_scu.h>
  30 #include <asm/smp_plat.h>
  31 #include <asm/mach/map.h>
  32
  33 #include "core.h"
  34
  35 static void __iomem *scu_base_addr;
  36 static void __iomem *sram_base_addr;
  37 static int ncores;
  38
  39 #define PMU_PWRDN_CON           0x08
  40 #define PMU_PWRDN_ST            0x0c
  41
  42 #define PMU_PWRDN_SCU           4
  43
  44 static struct regmap *pmu;
  45
  46 static int pmu_power_domain_is_on(int pd)
  47 {
  48         u32 val;
  49         int ret;
  50
  51         ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
  52         if (ret < 0)
  53                 return ret;
  54
  55         return !(val & BIT(pd));
  56 }
  57
  58 static struct reset_control *rockchip_get_core_reset(int cpu)
  59 {
  60         struct device *dev = get_cpu_device(cpu);
  61         struct device_node *np;
  62
  63         /* The cpu device is only available after the initial core bringup */
  64         if (dev)
  65                 np = dev->of_node;
  66         else
  67                 np = of_get_cpu_node(cpu, 0);
  68
  69         return of_reset_control_get(np, NULL);
  70 }
  71
  72 static int pmu_set_power_domain(int pd, bool on)
  73 {
  74         u32 val = (on) ? 0 : BIT(pd);
  75         struct reset_control *rstc = rockchip_get_core_reset(pd);
  76         int ret;
  77
  78         if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
  79                 pr_err("%s: could not get reset control for core %d\n",
  80                        __func__, pd);
  81                 return PTR_ERR(rstc);
  82         }
  83
  84         /*
  85          * We need to soft reset the cpu when we turn off the cpu power domain,
  86          * or else the active processors might be stalled when the individual
  87          * processor is powered down.
  88          */
  89         if (!IS_ERR(rstc) && !on)
  90                 reset_control_assert(rstc);
  91
  92         ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
  93         if (ret < 0) {
  94                 pr_err("%s: could not update power domain\n", __func__);
  95                 return ret;
  96         }
  97
  98         ret = -1;
  99         while (ret != on) {
 100                 ret = pmu_power_domain_is_on(pd);
 101                 if (ret < 0) {
 102                         pr_err("%s: could not read power domain state\n",
 103                                  __func__);
 104                         return ret;
 105                 }
 106         }
 107
 108         if (!IS_ERR(rstc)) {
 109                 if (on)
 110                         reset_control_deassert(rstc);
 111                 reset_control_put(rstc);
 112         }
 113
 114         return 0;
 115 }
 116
 117 /*
 118  * Handling of CPU cores
 119  */
 120
 121 static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
 122 {
 123         int ret;
 124
 125         if (!sram_base_addr || !pmu) {
 126                 pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
 127                 return -ENXIO;
 128         }
 129
 130         if (cpu >= ncores) {
 131                 pr_err("%s: cpu %d outside maximum number of cpus %d\n",
 132                                                         __func__, cpu, ncores);
 133                 return -ENXIO;
 134         }
 135
 136         /* start the core */
 137         ret = pmu_set_power_domain(0 + cpu, true);
 138         if (ret < 0)
 139                 return ret;
 140
 141         if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
 142                 /* We communicate with the bootrom to active the cpus other
 143                  * than cpu0, after a blob of initialize code, they will
 144                  * stay at wfe state, once they are actived, they will check
 145                  * the mailbox:
 146                  * sram_base_addr + 4: 0xdeadbeaf
 147                  * sram_base_addr + 8: start address for pc
 148                  * The cpu0 need to wait the other cpus other than cpu0 entering
 149                  * the wfe state.The wait time is affected by many aspects.
 150                  * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
 151                  * */
 152                 mdelay(1); /* ensure the cpus other than cpu0 to startup */
 153
 154                 writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
 155                 writel(0xDEADBEAF, sram_base_addr + 4);
 156                 dsb_sev();
 157         }
 158
 159         return 0;
 160 }
 161
 162 /**
 163  * rockchip_smp_prepare_sram - populate necessary sram block
 164  * Starting cores execute the code residing at the start of the on-chip sram
 165  * after power-on. Therefore make sure, this sram region is reserved and
 166  * big enough. After this check, copy the trampoline code that directs the
 167  * core to the real startup code in ram into the sram-region.
 168  * @node: mmio-sram device node
 169  */
 170 static int __init rockchip_smp_prepare_sram(struct device_node *node)
 171 {
 172         unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
 173                                             &rockchip_secondary_trampoline;
 174         struct resource res;
 175         unsigned int rsize;
 176         int ret;
 177
 178         ret = of_address_to_resource(node, 0, &res);
 179         if (ret < 0) {
 180                 pr_err("%s: could not get address for node %s\n",
 181                        __func__, node->full_name);
 182                 return ret;
 183         }
 184
 185         rsize = resource_size(&res);
 186         if (rsize < trampoline_sz) {
 187                 pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
 188                        __func__, rsize, trampoline_sz);
 189                 return -EINVAL;
 190         }
 191
 192         /* set the boot function for the sram code */
 193         rockchip_boot_fn = virt_to_phys(secondary_startup);
 194
 195         /* copy the trampoline to sram, that runs during startup of the core */
 196         memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
 197         flush_cache_all();
 198         outer_clean_range(0, trampoline_sz);
 199
 200         dsb_sev();
 201
 202         return 0;
 203 }
 204
 205 static const struct regmap_config rockchip_pmu_regmap_config = {
 206         .reg_bits = 32,
 207         .val_bits = 32,
 208         .reg_stride = 4,
 209 };
 210
 211 static int __init rockchip_smp_prepare_pmu(void)
 212 {
 213         struct device_node *node;
 214         void __iomem *pmu_base;
 215
 216         /*
 217          * This function is only called via smp_ops->smp_prepare_cpu().
 218          * That only happens if a "/cpus" device tree node exists
 219          * and has an "enable-method" property that selects the SMP
 220          * operations defined herein.
 221          */
 222         node = of_find_node_by_path("/cpus");
 223
 224         pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
 225         of_node_put(node);
 226         if (!IS_ERR(pmu))
 227                 return 0;
 228
 229         pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
 230         if (!IS_ERR(pmu))
 231                 return 0;
 232
 233         /* fallback, create our own regmap for the pmu area */
 234         pmu = NULL;
 235         node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
 236         if (!node) {
 237                 pr_err("%s: could not find pmu dt node\n", __func__);
 238                 return -ENODEV;
 239         }
 240
 241         pmu_base = of_iomap(node, 0);
 242         if (!pmu_base) {
 243                 pr_err("%s: could not map pmu registers\n", __func__);
 244                 return -ENOMEM;
 245         }
 246
 247         pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
 248         if (IS_ERR(pmu)) {
 249                 int ret = PTR_ERR(pmu);
 250
 251                 iounmap(pmu_base);
 252                 pmu = NULL;
 253                 pr_err("%s: regmap init failed\n", __func__);
 254                 return ret;
 255         }
 256
 257         return 0;
 258 }
 259
 260 static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
 261 {
 262         struct device_node *node;
 263         unsigned int i;
 264
 265         node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
 266         if (!node) {
 267                 pr_err("%s: could not find sram dt node\n", __func__);
 268                 return;
 269         }
 270
 271         sram_base_addr = of_iomap(node, 0);
 272         if (!sram_base_addr) {
 273                 pr_err("%s: could not map sram registers\n", __func__);
 274                 return;
 275         }
 276
 277         if (rockchip_smp_prepare_pmu())
 278                 return;
 279
 280         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
 281                 if (rockchip_smp_prepare_sram(node))
 282                         return;
 283
 284                 /* enable the SCU power domain */
 285                 pmu_set_power_domain(PMU_PWRDN_SCU, true);
 286
 287                 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
 288                 if (!node) {
 289                         pr_err("%s: missing scu\n", __func__);
 290                         return;
 291                 }
 292
 293                 scu_base_addr = of_iomap(node, 0);
 294                 if (!scu_base_addr) {
 295                         pr_err("%s: could not map scu registers\n", __func__);
 296                         return;
 297                 }
 298
 299                 /*
 300                  * While the number of cpus is gathered from dt, also get the
 301                  * number of cores from the scu to verify this value when
 302                  * booting the cores.
 303                  */
 304                 ncores = scu_get_core_count(scu_base_addr);
 305                 pr_err("%s: ncores %d\n", __func__, ncores);
 306
 307                 scu_enable(scu_base_addr);
 308         } else {
 309                 unsigned int l2ctlr;
 310
 311                 asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
 312                 ncores = ((l2ctlr >> 24) & 0x3) + 1;
 313         }
 314
 315         /* Make sure that all cores except the first are really off */
 316         for (i = 1; i < ncores; i++)
 317                 pmu_set_power_domain(0 + i, false);
 318 }
 319
 320 #ifdef CONFIG_HOTPLUG_CPU
 321 static int rockchip_cpu_kill(unsigned int cpu)
 322 {
 323         pmu_set_power_domain(0 + cpu, false);
 324         return 1;
 325 }
 326
 327 static void rockchip_cpu_die(unsigned int cpu)
 328 {
 329         v7_exit_coherency_flush(louis);
 330         while(1)
 331                 cpu_do_idle();
 332 }
 333 #endif
 334
 335 static struct smp_operations rockchip_smp_ops __initdata = {
 336         .smp_prepare_cpus       = rockchip_smp_prepare_cpus,
 337         .smp_boot_secondary     = rockchip_boot_secondary,
 338 #ifdef CONFIG_HOTPLUG_CPU
 339         .cpu_kill               = rockchip_cpu_kill,
 340         .cpu_die                = rockchip_cpu_die,
 341 #endif
 342 };
 343 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);