2 * at91 pinctrl driver based on at91 pinmux core
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
20 #include <linux/gpio.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 /* Since we request GPIOs from ourself */
26 #include <linux/pinctrl/consumer.h>
28 #include "pinctrl-at91.h"
31 #define MAX_GPIO_BANKS 5
32 #define MAX_NB_GPIO_PER_BANK 32
34 struct at91_pinctrl_mux_ops
;
36 struct at91_gpio_chip
{
37 struct gpio_chip chip
;
38 struct pinctrl_gpio_range range
;
39 struct at91_gpio_chip
*next
; /* Bank sharing same clock */
40 int pioc_hwirq
; /* PIO bank interrupt identifier on AIC */
41 int pioc_virq
; /* PIO bank Linux virtual interrupt */
42 int pioc_idx
; /* PIO bank index */
43 void __iomem
*regbase
; /* PIO bank virtual address */
44 struct clk
*clock
; /* associated clock */
45 struct at91_pinctrl_mux_ops
*ops
; /* ops */
48 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
50 static struct at91_gpio_chip
*gpio_chips
[MAX_GPIO_BANKS
];
52 static int gpio_banks
;
54 #define PULL_UP (1 << 0)
55 #define MULTI_DRIVE (1 << 1)
56 #define DEGLITCH (1 << 2)
57 #define PULL_DOWN (1 << 3)
58 #define DIS_SCHMIT (1 << 4)
59 #define DRIVE_STRENGTH_SHIFT 5
60 #define DRIVE_STRENGTH_MASK 0x3
61 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
62 #define DEBOUNCE (1 << 16)
63 #define DEBOUNCE_VAL_SHIFT 17
64 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
67 * These defines will translated the dt binding settings to our internal
68 * settings. They are not necessarily the same value as the register setting.
69 * The actual drive strength current of low, medium and high must be looked up
70 * from the corresponding device datasheet. This value is different for pins
71 * that are even in the same banks. It is also dependent on VCC.
72 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
73 * strength when there is no dt config for it.
75 #define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
76 #define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
77 #define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
78 #define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
81 * struct at91_pmx_func - describes AT91 pinmux functions
82 * @name: the name of this specific function
83 * @groups: corresponding pin groups
84 * @ngroups: the number of groups
86 struct at91_pmx_func
{
94 AT91_MUX_PERIPH_A
= 1,
95 AT91_MUX_PERIPH_B
= 2,
96 AT91_MUX_PERIPH_C
= 3,
97 AT91_MUX_PERIPH_D
= 4,
101 * struct at91_pmx_pin - describes an At91 pin mux
102 * @bank: the bank of the pin
103 * @pin: the pin number in the @bank
104 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
105 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
107 struct at91_pmx_pin
{
115 * struct at91_pin_group - describes an At91 pin group
116 * @name: the name of this specific pin group
117 * @pins_conf: the mux mode for each pin in this group. The size of this
118 * array is the same as pins.
119 * @pins: an array of discrete physical pins used in this group, taken
120 * from the driver-local pin enumeration space
121 * @npins: the number of pins in this group array, i.e. the number of
122 * elements in .pins so we can iterate over that array
124 struct at91_pin_group
{
126 struct at91_pmx_pin
*pins_conf
;
132 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
133 * on new IP with support for periph C and D the way to mux in
134 * periph A and B has changed
135 * So provide the right call back
136 * if not present means the IP does not support it
137 * @get_periph: return the periph mode configured
138 * @mux_A_periph: mux as periph A
139 * @mux_B_periph: mux as periph B
140 * @mux_C_periph: mux as periph C
141 * @mux_D_periph: mux as periph D
142 * @get_deglitch: get deglitch status
143 * @set_deglitch: enable/disable deglitch
144 * @get_debounce: get debounce status
145 * @set_debounce: enable/disable debounce
146 * @get_pulldown: get pulldown status
147 * @set_pulldown: enable/disable pulldown
148 * @get_schmitt_trig: get schmitt trigger status
149 * @disable_schmitt_trig: disable schmitt trigger
150 * @irq_type: return irq type
152 struct at91_pinctrl_mux_ops
{
153 enum at91_mux (*get_periph
)(void __iomem
*pio
, unsigned mask
);
154 void (*mux_A_periph
)(void __iomem
*pio
, unsigned mask
);
155 void (*mux_B_periph
)(void __iomem
*pio
, unsigned mask
);
156 void (*mux_C_periph
)(void __iomem
*pio
, unsigned mask
);
157 void (*mux_D_periph
)(void __iomem
*pio
, unsigned mask
);
158 bool (*get_deglitch
)(void __iomem
*pio
, unsigned pin
);
159 void (*set_deglitch
)(void __iomem
*pio
, unsigned mask
, bool is_on
);
160 bool (*get_debounce
)(void __iomem
*pio
, unsigned pin
, u32
*div
);
161 void (*set_debounce
)(void __iomem
*pio
, unsigned mask
, bool is_on
, u32 div
);
162 bool (*get_pulldown
)(void __iomem
*pio
, unsigned pin
);
163 void (*set_pulldown
)(void __iomem
*pio
, unsigned mask
, bool is_on
);
164 bool (*get_schmitt_trig
)(void __iomem
*pio
, unsigned pin
);
165 void (*disable_schmitt_trig
)(void __iomem
*pio
, unsigned mask
);
166 unsigned (*get_drivestrength
)(void __iomem
*pio
, unsigned pin
);
167 void (*set_drivestrength
)(void __iomem
*pio
, unsigned pin
,
170 int (*irq_type
)(struct irq_data
*d
, unsigned type
);
173 static int gpio_irq_type(struct irq_data
*d
, unsigned type
);
174 static int alt_gpio_irq_type(struct irq_data
*d
, unsigned type
);
176 struct at91_pinctrl
{
178 struct pinctrl_dev
*pctl
;
185 struct at91_pmx_func
*functions
;
188 struct at91_pin_group
*groups
;
191 struct at91_pinctrl_mux_ops
*ops
;
194 static const inline struct at91_pin_group
*at91_pinctrl_find_group_by_name(
195 const struct at91_pinctrl
*info
,
198 const struct at91_pin_group
*grp
= NULL
;
201 for (i
= 0; i
< info
->ngroups
; i
++) {
202 if (strcmp(info
->groups
[i
].name
, name
))
205 grp
= &info
->groups
[i
];
206 dev_dbg(info
->dev
, "%s: %d 0:%d\n", name
, grp
->npins
, grp
->pins
[0]);
213 static int at91_get_groups_count(struct pinctrl_dev
*pctldev
)
215 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
217 return info
->ngroups
;
220 static const char *at91_get_group_name(struct pinctrl_dev
*pctldev
,
223 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
225 return info
->groups
[selector
].name
;
228 static int at91_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
229 const unsigned **pins
,
232 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
234 if (selector
>= info
->ngroups
)
237 *pins
= info
->groups
[selector
].pins
;
238 *npins
= info
->groups
[selector
].npins
;
243 static void at91_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
246 seq_printf(s
, "%s", dev_name(pctldev
->dev
));
249 static int at91_dt_node_to_map(struct pinctrl_dev
*pctldev
,
250 struct device_node
*np
,
251 struct pinctrl_map
**map
, unsigned *num_maps
)
253 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
254 const struct at91_pin_group
*grp
;
255 struct pinctrl_map
*new_map
;
256 struct device_node
*parent
;
261 * first find the group of this node and check if we need to create
262 * config maps for pins
264 grp
= at91_pinctrl_find_group_by_name(info
, np
->name
);
266 dev_err(info
->dev
, "unable to find group for node %s\n",
271 map_num
+= grp
->npins
;
272 new_map
= devm_kzalloc(pctldev
->dev
, sizeof(*new_map
) * map_num
, GFP_KERNEL
);
280 parent
= of_get_parent(np
);
282 devm_kfree(pctldev
->dev
, new_map
);
285 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
286 new_map
[0].data
.mux
.function
= parent
->name
;
287 new_map
[0].data
.mux
.group
= np
->name
;
290 /* create config map */
292 for (i
= 0; i
< grp
->npins
; i
++) {
293 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
294 new_map
[i
].data
.configs
.group_or_pin
=
295 pin_get_name(pctldev
, grp
->pins
[i
]);
296 new_map
[i
].data
.configs
.configs
= &grp
->pins_conf
[i
].conf
;
297 new_map
[i
].data
.configs
.num_configs
= 1;
300 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
301 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
306 static void at91_dt_free_map(struct pinctrl_dev
*pctldev
,
307 struct pinctrl_map
*map
, unsigned num_maps
)
311 static const struct pinctrl_ops at91_pctrl_ops
= {
312 .get_groups_count
= at91_get_groups_count
,
313 .get_group_name
= at91_get_group_name
,
314 .get_group_pins
= at91_get_group_pins
,
315 .pin_dbg_show
= at91_pin_dbg_show
,
316 .dt_node_to_map
= at91_dt_node_to_map
,
317 .dt_free_map
= at91_dt_free_map
,
320 static void __iomem
*pin_to_controller(struct at91_pinctrl
*info
,
323 return gpio_chips
[bank
]->regbase
;
326 static inline int pin_to_bank(unsigned pin
)
328 return pin
/= MAX_NB_GPIO_PER_BANK
;
331 static unsigned pin_to_mask(unsigned int pin
)
336 static unsigned two_bit_pin_value_shift_amount(unsigned int pin
)
338 /* return the shift value for a pin for "two bit" per pin registers,
339 * i.e. drive strength */
340 return 2*((pin
>= MAX_NB_GPIO_PER_BANK
/2)
341 ? pin
- MAX_NB_GPIO_PER_BANK
/2 : pin
);
344 static unsigned sama5d3_get_drive_register(unsigned int pin
)
346 /* drive strength is split between two registers
347 * with two bits per pin */
348 return (pin
>= MAX_NB_GPIO_PER_BANK
/2)
349 ? SAMA5D3_PIO_DRIVER2
: SAMA5D3_PIO_DRIVER1
;
352 static unsigned at91sam9x5_get_drive_register(unsigned int pin
)
354 /* drive strength is split between two registers
355 * with two bits per pin */
356 return (pin
>= MAX_NB_GPIO_PER_BANK
/2)
357 ? AT91SAM9X5_PIO_DRIVER2
: AT91SAM9X5_PIO_DRIVER1
;
360 static void at91_mux_disable_interrupt(void __iomem
*pio
, unsigned mask
)
362 writel_relaxed(mask
, pio
+ PIO_IDR
);
365 static unsigned at91_mux_get_pullup(void __iomem
*pio
, unsigned pin
)
367 return !((readl_relaxed(pio
+ PIO_PUSR
) >> pin
) & 0x1);
370 static void at91_mux_set_pullup(void __iomem
*pio
, unsigned mask
, bool on
)
373 writel_relaxed(mask
, pio
+ PIO_PPDDR
);
375 writel_relaxed(mask
, pio
+ (on
? PIO_PUER
: PIO_PUDR
));
378 static unsigned at91_mux_get_multidrive(void __iomem
*pio
, unsigned pin
)
380 return (readl_relaxed(pio
+ PIO_MDSR
) >> pin
) & 0x1;
383 static void at91_mux_set_multidrive(void __iomem
*pio
, unsigned mask
, bool on
)
385 writel_relaxed(mask
, pio
+ (on
? PIO_MDER
: PIO_MDDR
));
388 static void at91_mux_set_A_periph(void __iomem
*pio
, unsigned mask
)
390 writel_relaxed(mask
, pio
+ PIO_ASR
);
393 static void at91_mux_set_B_periph(void __iomem
*pio
, unsigned mask
)
395 writel_relaxed(mask
, pio
+ PIO_BSR
);
398 static void at91_mux_pio3_set_A_periph(void __iomem
*pio
, unsigned mask
)
401 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) & ~mask
,
403 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) & ~mask
,
407 static void at91_mux_pio3_set_B_periph(void __iomem
*pio
, unsigned mask
)
409 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) | mask
,
411 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) & ~mask
,
415 static void at91_mux_pio3_set_C_periph(void __iomem
*pio
, unsigned mask
)
417 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) & ~mask
, pio
+ PIO_ABCDSR1
);
418 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) | mask
, pio
+ PIO_ABCDSR2
);
421 static void at91_mux_pio3_set_D_periph(void __iomem
*pio
, unsigned mask
)
423 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) | mask
, pio
+ PIO_ABCDSR1
);
424 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) | mask
, pio
+ PIO_ABCDSR2
);
427 static enum at91_mux
at91_mux_pio3_get_periph(void __iomem
*pio
, unsigned mask
)
431 if (readl_relaxed(pio
+ PIO_PSR
) & mask
)
432 return AT91_MUX_GPIO
;
434 select
= !!(readl_relaxed(pio
+ PIO_ABCDSR1
) & mask
);
435 select
|= (!!(readl_relaxed(pio
+ PIO_ABCDSR2
) & mask
) << 1);
440 static enum at91_mux
at91_mux_get_periph(void __iomem
*pio
, unsigned mask
)
444 if (readl_relaxed(pio
+ PIO_PSR
) & mask
)
445 return AT91_MUX_GPIO
;
447 select
= readl_relaxed(pio
+ PIO_ABSR
) & mask
;
452 static bool at91_mux_get_deglitch(void __iomem
*pio
, unsigned pin
)
454 return (readl_relaxed(pio
+ PIO_IFSR
) >> pin
) & 0x1;
457 static void at91_mux_set_deglitch(void __iomem
*pio
, unsigned mask
, bool is_on
)
459 writel_relaxed(mask
, pio
+ (is_on
? PIO_IFER
: PIO_IFDR
));
462 static bool at91_mux_pio3_get_deglitch(void __iomem
*pio
, unsigned pin
)
464 if ((readl_relaxed(pio
+ PIO_IFSR
) >> pin
) & 0x1)
465 return !((readl_relaxed(pio
+ PIO_IFSCSR
) >> pin
) & 0x1);
470 static void at91_mux_pio3_set_deglitch(void __iomem
*pio
, unsigned mask
, bool is_on
)
473 writel_relaxed(mask
, pio
+ PIO_IFSCDR
);
474 at91_mux_set_deglitch(pio
, mask
, is_on
);
477 static bool at91_mux_pio3_get_debounce(void __iomem
*pio
, unsigned pin
, u32
*div
)
479 *div
= readl_relaxed(pio
+ PIO_SCDR
);
481 return ((readl_relaxed(pio
+ PIO_IFSR
) >> pin
) & 0x1) &&
482 ((readl_relaxed(pio
+ PIO_IFSCSR
) >> pin
) & 0x1);
485 static void at91_mux_pio3_set_debounce(void __iomem
*pio
, unsigned mask
,
489 writel_relaxed(mask
, pio
+ PIO_IFSCER
);
490 writel_relaxed(div
& PIO_SCDR_DIV
, pio
+ PIO_SCDR
);
491 writel_relaxed(mask
, pio
+ PIO_IFER
);
493 writel_relaxed(mask
, pio
+ PIO_IFSCDR
);
496 static bool at91_mux_pio3_get_pulldown(void __iomem
*pio
, unsigned pin
)
498 return !((readl_relaxed(pio
+ PIO_PPDSR
) >> pin
) & 0x1);
501 static void at91_mux_pio3_set_pulldown(void __iomem
*pio
, unsigned mask
, bool is_on
)
504 writel_relaxed(mask
, pio
+ PIO_PUDR
);
506 writel_relaxed(mask
, pio
+ (is_on
? PIO_PPDER
: PIO_PPDDR
));
509 static void at91_mux_pio3_disable_schmitt_trig(void __iomem
*pio
, unsigned mask
)
511 writel_relaxed(readl_relaxed(pio
+ PIO_SCHMITT
) | mask
, pio
+ PIO_SCHMITT
);
514 static bool at91_mux_pio3_get_schmitt_trig(void __iomem
*pio
, unsigned pin
)
516 return (readl_relaxed(pio
+ PIO_SCHMITT
) >> pin
) & 0x1;
519 static inline u32
read_drive_strength(void __iomem
*reg
, unsigned pin
)
521 unsigned tmp
= readl_relaxed(reg
);
523 tmp
= tmp
>> two_bit_pin_value_shift_amount(pin
);
525 return tmp
& DRIVE_STRENGTH_MASK
;
528 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem
*pio
,
531 unsigned tmp
= read_drive_strength(pio
+
532 sama5d3_get_drive_register(pin
), pin
);
534 /* SAMA5 strength is 1:1 with our defines,
535 * except 0 is equivalent to low per datasheet */
537 tmp
= DRIVE_STRENGTH_LOW
;
542 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem
*pio
,
545 unsigned tmp
= read_drive_strength(pio
+
546 at91sam9x5_get_drive_register(pin
), pin
);
548 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
549 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
550 tmp
= DRIVE_STRENGTH_HI
- tmp
;
555 static void set_drive_strength(void __iomem
*reg
, unsigned pin
, u32 strength
)
557 unsigned tmp
= readl_relaxed(reg
);
558 unsigned shift
= two_bit_pin_value_shift_amount(pin
);
560 tmp
&= ~(DRIVE_STRENGTH_MASK
<< shift
);
561 tmp
|= strength
<< shift
;
563 writel_relaxed(tmp
, reg
);
566 static void at91_mux_sama5d3_set_drivestrength(void __iomem
*pio
, unsigned pin
,
569 /* do nothing if setting is zero */
573 /* strength is 1 to 1 with setting for SAMA5 */
574 set_drive_strength(pio
+ sama5d3_get_drive_register(pin
), pin
, setting
);
577 static void at91_mux_sam9x5_set_drivestrength(void __iomem
*pio
, unsigned pin
,
580 /* do nothing if setting is zero */
584 /* strength is inverse on SAM9x5s with our defines
585 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
586 setting
= DRIVE_STRENGTH_HI
- setting
;
588 set_drive_strength(pio
+ at91sam9x5_get_drive_register(pin
), pin
,
592 static struct at91_pinctrl_mux_ops at91rm9200_ops
= {
593 .get_periph
= at91_mux_get_periph
,
594 .mux_A_periph
= at91_mux_set_A_periph
,
595 .mux_B_periph
= at91_mux_set_B_periph
,
596 .get_deglitch
= at91_mux_get_deglitch
,
597 .set_deglitch
= at91_mux_set_deglitch
,
598 .irq_type
= gpio_irq_type
,
601 static struct at91_pinctrl_mux_ops at91sam9x5_ops
= {
602 .get_periph
= at91_mux_pio3_get_periph
,
603 .mux_A_periph
= at91_mux_pio3_set_A_periph
,
604 .mux_B_periph
= at91_mux_pio3_set_B_periph
,
605 .mux_C_periph
= at91_mux_pio3_set_C_periph
,
606 .mux_D_periph
= at91_mux_pio3_set_D_periph
,
607 .get_deglitch
= at91_mux_pio3_get_deglitch
,
608 .set_deglitch
= at91_mux_pio3_set_deglitch
,
609 .get_debounce
= at91_mux_pio3_get_debounce
,
610 .set_debounce
= at91_mux_pio3_set_debounce
,
611 .get_pulldown
= at91_mux_pio3_get_pulldown
,
612 .set_pulldown
= at91_mux_pio3_set_pulldown
,
613 .get_schmitt_trig
= at91_mux_pio3_get_schmitt_trig
,
614 .disable_schmitt_trig
= at91_mux_pio3_disable_schmitt_trig
,
615 .get_drivestrength
= at91_mux_sam9x5_get_drivestrength
,
616 .set_drivestrength
= at91_mux_sam9x5_set_drivestrength
,
617 .irq_type
= alt_gpio_irq_type
,
620 static struct at91_pinctrl_mux_ops sama5d3_ops
= {
621 .get_periph
= at91_mux_pio3_get_periph
,
622 .mux_A_periph
= at91_mux_pio3_set_A_periph
,
623 .mux_B_periph
= at91_mux_pio3_set_B_periph
,
624 .mux_C_periph
= at91_mux_pio3_set_C_periph
,
625 .mux_D_periph
= at91_mux_pio3_set_D_periph
,
626 .get_deglitch
= at91_mux_pio3_get_deglitch
,
627 .set_deglitch
= at91_mux_pio3_set_deglitch
,
628 .get_debounce
= at91_mux_pio3_get_debounce
,
629 .set_debounce
= at91_mux_pio3_set_debounce
,
630 .get_pulldown
= at91_mux_pio3_get_pulldown
,
631 .set_pulldown
= at91_mux_pio3_set_pulldown
,
632 .get_schmitt_trig
= at91_mux_pio3_get_schmitt_trig
,
633 .disable_schmitt_trig
= at91_mux_pio3_disable_schmitt_trig
,
634 .get_drivestrength
= at91_mux_sama5d3_get_drivestrength
,
635 .set_drivestrength
= at91_mux_sama5d3_set_drivestrength
,
636 .irq_type
= alt_gpio_irq_type
,
639 static void at91_pin_dbg(const struct device
*dev
, const struct at91_pmx_pin
*pin
)
642 dev_dbg(dev
, "pio%c%d configured as periph%c with conf = 0x%lx\n",
643 pin
->bank
+ 'A', pin
->pin
, pin
->mux
- 1 + 'A', pin
->conf
);
645 dev_dbg(dev
, "pio%c%d configured as gpio with conf = 0x%lx\n",
646 pin
->bank
+ 'A', pin
->pin
, pin
->conf
);
650 static int pin_check_config(struct at91_pinctrl
*info
, const char *name
,
651 int index
, const struct at91_pmx_pin
*pin
)
655 /* check if it's a valid config */
656 if (pin
->bank
>= gpio_banks
) {
657 dev_err(info
->dev
, "%s: pin conf %d bank_id %d >= nbanks %d\n",
658 name
, index
, pin
->bank
, gpio_banks
);
662 if (!gpio_chips
[pin
->bank
]) {
663 dev_err(info
->dev
, "%s: pin conf %d bank_id %d not enabled\n",
664 name
, index
, pin
->bank
);
668 if (pin
->pin
>= MAX_NB_GPIO_PER_BANK
) {
669 dev_err(info
->dev
, "%s: pin conf %d pin_bank_id %d >= %d\n",
670 name
, index
, pin
->pin
, MAX_NB_GPIO_PER_BANK
);
679 if (mux
>= info
->nmux
) {
680 dev_err(info
->dev
, "%s: pin conf %d mux_id %d >= nmux %d\n",
681 name
, index
, mux
, info
->nmux
);
685 if (!(info
->mux_mask
[pin
->bank
* info
->nmux
+ mux
] & 1 << pin
->pin
)) {
686 dev_err(info
->dev
, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
687 name
, index
, mux
, pin
->bank
+ 'A', pin
->pin
);
694 static void at91_mux_gpio_disable(void __iomem
*pio
, unsigned mask
)
696 writel_relaxed(mask
, pio
+ PIO_PDR
);
699 static void at91_mux_gpio_enable(void __iomem
*pio
, unsigned mask
, bool input
)
701 writel_relaxed(mask
, pio
+ PIO_PER
);
702 writel_relaxed(mask
, pio
+ (input
? PIO_ODR
: PIO_OER
));
705 static int at91_pmx_set(struct pinctrl_dev
*pctldev
, unsigned selector
,
708 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
709 const struct at91_pmx_pin
*pins_conf
= info
->groups
[group
].pins_conf
;
710 const struct at91_pmx_pin
*pin
;
711 uint32_t npins
= info
->groups
[group
].npins
;
716 dev_dbg(info
->dev
, "enable function %s group %s\n",
717 info
->functions
[selector
].name
, info
->groups
[group
].name
);
719 /* first check that all the pins of the group are valid with a valid
721 for (i
= 0; i
< npins
; i
++) {
723 ret
= pin_check_config(info
, info
->groups
[group
].name
, i
, pin
);
728 for (i
= 0; i
< npins
; i
++) {
730 at91_pin_dbg(info
->dev
, pin
);
731 pio
= pin_to_controller(info
, pin
->bank
);
732 mask
= pin_to_mask(pin
->pin
);
733 at91_mux_disable_interrupt(pio
, mask
);
736 at91_mux_gpio_enable(pio
, mask
, 1);
738 case AT91_MUX_PERIPH_A
:
739 info
->ops
->mux_A_periph(pio
, mask
);
741 case AT91_MUX_PERIPH_B
:
742 info
->ops
->mux_B_periph(pio
, mask
);
744 case AT91_MUX_PERIPH_C
:
745 if (!info
->ops
->mux_C_periph
)
747 info
->ops
->mux_C_periph(pio
, mask
);
749 case AT91_MUX_PERIPH_D
:
750 if (!info
->ops
->mux_D_periph
)
752 info
->ops
->mux_D_periph(pio
, mask
);
756 at91_mux_gpio_disable(pio
, mask
);
762 static int at91_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
764 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
766 return info
->nfunctions
;
769 static const char *at91_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
772 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
774 return info
->functions
[selector
].name
;
777 static int at91_pmx_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
778 const char * const **groups
,
779 unsigned * const num_groups
)
781 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
783 *groups
= info
->functions
[selector
].groups
;
784 *num_groups
= info
->functions
[selector
].ngroups
;
789 static int at91_gpio_request_enable(struct pinctrl_dev
*pctldev
,
790 struct pinctrl_gpio_range
*range
,
793 struct at91_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
794 struct at91_gpio_chip
*at91_chip
;
795 struct gpio_chip
*chip
;
799 dev_err(npct
->dev
, "invalid range\n");
803 dev_err(npct
->dev
, "missing GPIO chip in range\n");
807 at91_chip
= container_of(chip
, struct at91_gpio_chip
, chip
);
809 dev_dbg(npct
->dev
, "enable pin %u as GPIO\n", offset
);
811 mask
= 1 << (offset
- chip
->base
);
813 dev_dbg(npct
->dev
, "enable pin %u as PIO%c%d 0x%x\n",
814 offset
, 'A' + range
->id
, offset
- chip
->base
, mask
);
816 writel_relaxed(mask
, at91_chip
->regbase
+ PIO_PER
);
821 static void at91_gpio_disable_free(struct pinctrl_dev
*pctldev
,
822 struct pinctrl_gpio_range
*range
,
825 struct at91_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
827 dev_dbg(npct
->dev
, "disable pin %u as GPIO\n", offset
);
828 /* Set the pin to some default state, GPIO is usually default */
831 static const struct pinmux_ops at91_pmx_ops
= {
832 .get_functions_count
= at91_pmx_get_funcs_count
,
833 .get_function_name
= at91_pmx_get_func_name
,
834 .get_function_groups
= at91_pmx_get_groups
,
835 .set_mux
= at91_pmx_set
,
836 .gpio_request_enable
= at91_gpio_request_enable
,
837 .gpio_disable_free
= at91_gpio_disable_free
,
840 static int at91_pinconf_get(struct pinctrl_dev
*pctldev
,
841 unsigned pin_id
, unsigned long *config
)
843 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
849 dev_dbg(info
->dev
, "%s:%d, pin_id=%d", __func__
, __LINE__
, pin_id
);
850 pio
= pin_to_controller(info
, pin_to_bank(pin_id
));
851 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
853 if (at91_mux_get_multidrive(pio
, pin
))
854 *config
|= MULTI_DRIVE
;
856 if (at91_mux_get_pullup(pio
, pin
))
859 if (info
->ops
->get_deglitch
&& info
->ops
->get_deglitch(pio
, pin
))
861 if (info
->ops
->get_debounce
&& info
->ops
->get_debounce(pio
, pin
, &div
))
862 *config
|= DEBOUNCE
| (div
<< DEBOUNCE_VAL_SHIFT
);
863 if (info
->ops
->get_pulldown
&& info
->ops
->get_pulldown(pio
, pin
))
864 *config
|= PULL_DOWN
;
865 if (info
->ops
->get_schmitt_trig
&& info
->ops
->get_schmitt_trig(pio
, pin
))
866 *config
|= DIS_SCHMIT
;
867 if (info
->ops
->get_drivestrength
)
868 *config
|= (info
->ops
->get_drivestrength(pio
, pin
)
869 << DRIVE_STRENGTH_SHIFT
);
874 static int at91_pinconf_set(struct pinctrl_dev
*pctldev
,
875 unsigned pin_id
, unsigned long *configs
,
876 unsigned num_configs
)
878 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
882 unsigned long config
;
885 for (i
= 0; i
< num_configs
; i
++) {
889 "%s:%d, pin_id=%d, config=0x%lx",
890 __func__
, __LINE__
, pin_id
, config
);
891 pio
= pin_to_controller(info
, pin_to_bank(pin_id
));
892 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
893 mask
= pin_to_mask(pin
);
895 if (config
& PULL_UP
&& config
& PULL_DOWN
)
898 at91_mux_set_pullup(pio
, mask
, config
& PULL_UP
);
899 at91_mux_set_multidrive(pio
, mask
, config
& MULTI_DRIVE
);
900 if (info
->ops
->set_deglitch
)
901 info
->ops
->set_deglitch(pio
, mask
, config
& DEGLITCH
);
902 if (info
->ops
->set_debounce
)
903 info
->ops
->set_debounce(pio
, mask
, config
& DEBOUNCE
,
904 (config
& DEBOUNCE_VAL
) >> DEBOUNCE_VAL_SHIFT
);
905 if (info
->ops
->set_pulldown
)
906 info
->ops
->set_pulldown(pio
, mask
, config
& PULL_DOWN
);
907 if (info
->ops
->disable_schmitt_trig
&& config
& DIS_SCHMIT
)
908 info
->ops
->disable_schmitt_trig(pio
, mask
);
909 if (info
->ops
->set_drivestrength
)
910 info
->ops
->set_drivestrength(pio
, pin
,
911 (config
& DRIVE_STRENGTH
)
912 >> DRIVE_STRENGTH_SHIFT
);
914 } /* for each config */
919 #define DBG_SHOW_FLAG(flag) do { \
920 if (config & flag) { \
923 seq_puts(s, #flag); \
928 #define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
929 if ((config & mask) == flag) { \
932 seq_puts(s, #flag); \
937 static void at91_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
938 struct seq_file
*s
, unsigned pin_id
)
940 unsigned long config
;
941 int val
, num_conf
= 0;
943 at91_pinconf_get(pctldev
, pin_id
, &config
);
945 DBG_SHOW_FLAG(MULTI_DRIVE
);
946 DBG_SHOW_FLAG(PULL_UP
);
947 DBG_SHOW_FLAG(PULL_DOWN
);
948 DBG_SHOW_FLAG(DIS_SCHMIT
);
949 DBG_SHOW_FLAG(DEGLITCH
);
950 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH
, DRIVE_STRENGTH_LOW
);
951 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH
, DRIVE_STRENGTH_MED
);
952 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH
, DRIVE_STRENGTH_HI
);
953 DBG_SHOW_FLAG(DEBOUNCE
);
954 if (config
& DEBOUNCE
) {
955 val
= config
>> DEBOUNCE_VAL_SHIFT
;
956 seq_printf(s
, "(%d)", val
);
962 static void at91_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
963 struct seq_file
*s
, unsigned group
)
967 static const struct pinconf_ops at91_pinconf_ops
= {
968 .pin_config_get
= at91_pinconf_get
,
969 .pin_config_set
= at91_pinconf_set
,
970 .pin_config_dbg_show
= at91_pinconf_dbg_show
,
971 .pin_config_group_dbg_show
= at91_pinconf_group_dbg_show
,
974 static struct pinctrl_desc at91_pinctrl_desc
= {
975 .pctlops
= &at91_pctrl_ops
,
976 .pmxops
= &at91_pmx_ops
,
977 .confops
= &at91_pinconf_ops
,
978 .owner
= THIS_MODULE
,
981 static const char *gpio_compat
= "atmel,at91rm9200-gpio";
983 static void at91_pinctrl_child_count(struct at91_pinctrl
*info
,
984 struct device_node
*np
)
986 struct device_node
*child
;
988 for_each_child_of_node(np
, child
) {
989 if (of_device_is_compatible(child
, gpio_compat
)) {
990 if (of_device_is_available(child
))
991 info
->nactive_banks
++;
994 info
->ngroups
+= of_get_child_count(child
);
999 static int at91_pinctrl_mux_mask(struct at91_pinctrl
*info
,
1000 struct device_node
*np
)
1006 list
= of_get_property(np
, "atmel,mux-mask", &size
);
1008 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
1012 size
/= sizeof(*list
);
1013 if (!size
|| size
% gpio_banks
) {
1014 dev_err(info
->dev
, "wrong mux mask array should be by %d\n", gpio_banks
);
1017 info
->nmux
= size
/ gpio_banks
;
1019 info
->mux_mask
= devm_kzalloc(info
->dev
, sizeof(u32
) * size
, GFP_KERNEL
);
1020 if (!info
->mux_mask
) {
1021 dev_err(info
->dev
, "could not alloc mux_mask\n");
1025 ret
= of_property_read_u32_array(np
, "atmel,mux-mask",
1026 info
->mux_mask
, size
);
1028 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
1032 static int at91_pinctrl_parse_groups(struct device_node
*np
,
1033 struct at91_pin_group
*grp
,
1034 struct at91_pinctrl
*info
, u32 index
)
1036 struct at91_pmx_pin
*pin
;
1041 dev_dbg(info
->dev
, "group(%d): %s\n", index
, np
->name
);
1043 /* Initialise group */
1044 grp
->name
= np
->name
;
1047 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1048 * do sanity check and calculate pins number
1050 list
= of_get_property(np
, "atmel,pins", &size
);
1051 /* we do not check return since it's safe node passed down */
1052 size
/= sizeof(*list
);
1053 if (!size
|| size
% 4) {
1054 dev_err(info
->dev
, "wrong pins number or pins and configs should be by 4\n");
1058 grp
->npins
= size
/ 4;
1059 pin
= grp
->pins_conf
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(struct at91_pmx_pin
),
1061 grp
->pins
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(unsigned int),
1063 if (!grp
->pins_conf
|| !grp
->pins
)
1066 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
1067 pin
->bank
= be32_to_cpu(*list
++);
1068 pin
->pin
= be32_to_cpu(*list
++);
1069 grp
->pins
[j
] = pin
->bank
* MAX_NB_GPIO_PER_BANK
+ pin
->pin
;
1070 pin
->mux
= be32_to_cpu(*list
++);
1071 pin
->conf
= be32_to_cpu(*list
++);
1073 at91_pin_dbg(info
->dev
, pin
);
1080 static int at91_pinctrl_parse_functions(struct device_node
*np
,
1081 struct at91_pinctrl
*info
, u32 index
)
1083 struct device_node
*child
;
1084 struct at91_pmx_func
*func
;
1085 struct at91_pin_group
*grp
;
1087 static u32 grp_index
;
1090 dev_dbg(info
->dev
, "parse function(%d): %s\n", index
, np
->name
);
1092 func
= &info
->functions
[index
];
1094 /* Initialise function */
1095 func
->name
= np
->name
;
1096 func
->ngroups
= of_get_child_count(np
);
1097 if (func
->ngroups
== 0) {
1098 dev_err(info
->dev
, "no groups defined\n");
1101 func
->groups
= devm_kzalloc(info
->dev
,
1102 func
->ngroups
* sizeof(char *), GFP_KERNEL
);
1106 for_each_child_of_node(np
, child
) {
1107 func
->groups
[i
] = child
->name
;
1108 grp
= &info
->groups
[grp_index
++];
1109 ret
= at91_pinctrl_parse_groups(child
, grp
, info
, i
++);
1117 static const struct of_device_id at91_pinctrl_of_match
[] = {
1118 { .compatible
= "atmel,sama5d3-pinctrl", .data
= &sama5d3_ops
},
1119 { .compatible
= "atmel,at91sam9x5-pinctrl", .data
= &at91sam9x5_ops
},
1120 { .compatible
= "atmel,at91rm9200-pinctrl", .data
= &at91rm9200_ops
},
1124 static int at91_pinctrl_probe_dt(struct platform_device
*pdev
,
1125 struct at91_pinctrl
*info
)
1130 struct device_node
*np
= pdev
->dev
.of_node
;
1131 struct device_node
*child
;
1136 info
->dev
= &pdev
->dev
;
1137 info
->ops
= (struct at91_pinctrl_mux_ops
*)
1138 of_match_device(at91_pinctrl_of_match
, &pdev
->dev
)->data
;
1139 at91_pinctrl_child_count(info
, np
);
1141 if (gpio_banks
< 1) {
1142 dev_err(&pdev
->dev
, "you need to specify at least one gpio-controller\n");
1146 ret
= at91_pinctrl_mux_mask(info
, np
);
1150 dev_dbg(&pdev
->dev
, "nmux = %d\n", info
->nmux
);
1152 dev_dbg(&pdev
->dev
, "mux-mask\n");
1153 tmp
= info
->mux_mask
;
1154 for (i
= 0; i
< gpio_banks
; i
++) {
1155 for (j
= 0; j
< info
->nmux
; j
++, tmp
++) {
1156 dev_dbg(&pdev
->dev
, "%d:%d\t0x%x\n", i
, j
, tmp
[0]);
1160 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
1161 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
1162 info
->functions
= devm_kzalloc(&pdev
->dev
, info
->nfunctions
* sizeof(struct at91_pmx_func
),
1164 if (!info
->functions
)
1167 info
->groups
= devm_kzalloc(&pdev
->dev
, info
->ngroups
* sizeof(struct at91_pin_group
),
1172 dev_dbg(&pdev
->dev
, "nbanks = %d\n", gpio_banks
);
1173 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
1174 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
1178 for_each_child_of_node(np
, child
) {
1179 if (of_device_is_compatible(child
, gpio_compat
))
1181 ret
= at91_pinctrl_parse_functions(child
, info
, i
++);
1183 dev_err(&pdev
->dev
, "failed to parse function\n");
1191 static int at91_pinctrl_probe(struct platform_device
*pdev
)
1193 struct at91_pinctrl
*info
;
1194 struct pinctrl_pin_desc
*pdesc
;
1195 int ret
, i
, j
, k
, ngpio_chips_enabled
= 0;
1197 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
1201 ret
= at91_pinctrl_probe_dt(pdev
, info
);
1206 * We need all the GPIO drivers to probe FIRST, or we will not be able
1207 * to obtain references to the struct gpio_chip * for them, and we
1208 * need this to proceed.
1210 for (i
= 0; i
< gpio_banks
; i
++)
1212 ngpio_chips_enabled
++;
1214 if (ngpio_chips_enabled
< info
->nactive_banks
) {
1215 dev_warn(&pdev
->dev
,
1216 "All GPIO chips are not registered yet (%d/%d)\n",
1217 ngpio_chips_enabled
, info
->nactive_banks
);
1218 devm_kfree(&pdev
->dev
, info
);
1219 return -EPROBE_DEFER
;
1222 at91_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
1223 at91_pinctrl_desc
.npins
= gpio_banks
* MAX_NB_GPIO_PER_BANK
;
1224 at91_pinctrl_desc
.pins
= pdesc
=
1225 devm_kzalloc(&pdev
->dev
, sizeof(*pdesc
) * at91_pinctrl_desc
.npins
, GFP_KERNEL
);
1227 if (!at91_pinctrl_desc
.pins
)
1230 for (i
= 0, k
= 0; i
< gpio_banks
; i
++) {
1231 for (j
= 0; j
< MAX_NB_GPIO_PER_BANK
; j
++, k
++) {
1233 pdesc
->name
= kasprintf(GFP_KERNEL
, "pio%c%d", i
+ 'A', j
);
1238 platform_set_drvdata(pdev
, info
);
1239 info
->pctl
= pinctrl_register(&at91_pinctrl_desc
, &pdev
->dev
, info
);
1241 if (IS_ERR(info
->pctl
)) {
1242 dev_err(&pdev
->dev
, "could not register AT91 pinctrl driver\n");
1243 return PTR_ERR(info
->pctl
);
1246 /* We will handle a range of GPIO pins */
1247 for (i
= 0; i
< gpio_banks
; i
++)
1249 pinctrl_add_gpio_range(info
->pctl
, &gpio_chips
[i
]->range
);
1251 dev_info(&pdev
->dev
, "initialized AT91 pinctrl driver\n");
1256 static int at91_pinctrl_remove(struct platform_device
*pdev
)
1258 struct at91_pinctrl
*info
= platform_get_drvdata(pdev
);
1260 pinctrl_unregister(info
->pctl
);
1265 static int at91_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1268 * Map back to global GPIO space and request muxing, the direction
1269 * parameter does not matter for this controller.
1271 int gpio
= chip
->base
+ offset
;
1272 int bank
= chip
->base
/ chip
->ngpio
;
1274 dev_dbg(chip
->dev
, "%s:%d pio%c%d(%d)\n", __func__
, __LINE__
,
1275 'A' + bank
, offset
, gpio
);
1277 return pinctrl_request_gpio(gpio
);
1280 static void at91_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1282 int gpio
= chip
->base
+ offset
;
1284 pinctrl_free_gpio(gpio
);
1287 static int at91_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
1289 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1290 void __iomem
*pio
= at91_gpio
->regbase
;
1291 unsigned mask
= 1 << offset
;
1294 osr
= readl_relaxed(pio
+ PIO_OSR
);
1295 return !(osr
& mask
);
1298 static int at91_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1300 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1301 void __iomem
*pio
= at91_gpio
->regbase
;
1302 unsigned mask
= 1 << offset
;
1304 writel_relaxed(mask
, pio
+ PIO_ODR
);
1308 static int at91_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1310 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1311 void __iomem
*pio
= at91_gpio
->regbase
;
1312 unsigned mask
= 1 << offset
;
1315 pdsr
= readl_relaxed(pio
+ PIO_PDSR
);
1316 return (pdsr
& mask
) != 0;
1319 static void at91_gpio_set(struct gpio_chip
*chip
, unsigned offset
,
1322 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1323 void __iomem
*pio
= at91_gpio
->regbase
;
1324 unsigned mask
= 1 << offset
;
1326 writel_relaxed(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
1329 static void at91_gpio_set_multiple(struct gpio_chip
*chip
,
1330 unsigned long *mask
, unsigned long *bits
)
1332 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1333 void __iomem
*pio
= at91_gpio
->regbase
;
1335 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1336 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1337 uint32_t set_mask
= (*mask
& *bits
) & BITS_MASK(chip
->ngpio
);
1338 uint32_t clear_mask
= (*mask
& ~(*bits
)) & BITS_MASK(chip
->ngpio
);
1340 writel_relaxed(set_mask
, pio
+ PIO_SODR
);
1341 writel_relaxed(clear_mask
, pio
+ PIO_CODR
);
1344 static int at91_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
1347 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1348 void __iomem
*pio
= at91_gpio
->regbase
;
1349 unsigned mask
= 1 << offset
;
1351 writel_relaxed(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
1352 writel_relaxed(mask
, pio
+ PIO_OER
);
1357 #ifdef CONFIG_DEBUG_FS
1358 static void at91_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
1362 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1363 void __iomem
*pio
= at91_gpio
->regbase
;
1365 for (i
= 0; i
< chip
->ngpio
; i
++) {
1366 unsigned mask
= pin_to_mask(i
);
1367 const char *gpio_label
;
1369 gpio_label
= gpiochip_is_requested(chip
, i
);
1372 mode
= at91_gpio
->ops
->get_periph(pio
, mask
);
1373 seq_printf(s
, "[%s] GPIO%s%d: ",
1374 gpio_label
, chip
->label
, i
);
1375 if (mode
== AT91_MUX_GPIO
) {
1376 seq_printf(s
, "[gpio] ");
1377 seq_printf(s
, "%s ",
1378 readl_relaxed(pio
+ PIO_OSR
) & mask
?
1379 "output" : "input");
1380 seq_printf(s
, "%s\n",
1381 readl_relaxed(pio
+ PIO_PDSR
) & mask
?
1384 seq_printf(s
, "[periph %c]\n",
1390 #define at91_gpio_dbg_show NULL
1393 /* Several AIC controller irqs are dispatched through this GPIO handler.
1394 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1395 * at91_set_gpio_input() then maybe enable its glitch filter.
1396 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1398 * First implementation always triggers on rising and falling edges
1399 * whereas the newer PIO3 can be additionally configured to trigger on
1400 * level, edge with any polarity.
1402 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1403 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1404 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1407 static void gpio_irq_mask(struct irq_data
*d
)
1409 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1410 void __iomem
*pio
= at91_gpio
->regbase
;
1411 unsigned mask
= 1 << d
->hwirq
;
1414 writel_relaxed(mask
, pio
+ PIO_IDR
);
1417 static void gpio_irq_unmask(struct irq_data
*d
)
1419 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1420 void __iomem
*pio
= at91_gpio
->regbase
;
1421 unsigned mask
= 1 << d
->hwirq
;
1424 writel_relaxed(mask
, pio
+ PIO_IER
);
1427 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
1431 case IRQ_TYPE_EDGE_BOTH
:
1438 /* Alternate irq type for PIO3 support */
1439 static int alt_gpio_irq_type(struct irq_data
*d
, unsigned type
)
1441 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1442 void __iomem
*pio
= at91_gpio
->regbase
;
1443 unsigned mask
= 1 << d
->hwirq
;
1446 case IRQ_TYPE_EDGE_RISING
:
1447 __irq_set_handler_locked(d
->irq
, handle_simple_irq
);
1448 writel_relaxed(mask
, pio
+ PIO_ESR
);
1449 writel_relaxed(mask
, pio
+ PIO_REHLSR
);
1451 case IRQ_TYPE_EDGE_FALLING
:
1452 __irq_set_handler_locked(d
->irq
, handle_simple_irq
);
1453 writel_relaxed(mask
, pio
+ PIO_ESR
);
1454 writel_relaxed(mask
, pio
+ PIO_FELLSR
);
1456 case IRQ_TYPE_LEVEL_LOW
:
1457 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
1458 writel_relaxed(mask
, pio
+ PIO_LSR
);
1459 writel_relaxed(mask
, pio
+ PIO_FELLSR
);
1461 case IRQ_TYPE_LEVEL_HIGH
:
1462 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
1463 writel_relaxed(mask
, pio
+ PIO_LSR
);
1464 writel_relaxed(mask
, pio
+ PIO_REHLSR
);
1466 case IRQ_TYPE_EDGE_BOTH
:
1468 * disable additional interrupt modes:
1469 * fall back to default behavior
1471 __irq_set_handler_locked(d
->irq
, handle_simple_irq
);
1472 writel_relaxed(mask
, pio
+ PIO_AIMDR
);
1476 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d
->irq
));
1480 /* enable additional interrupt modes */
1481 writel_relaxed(mask
, pio
+ PIO_AIMER
);
1486 static void gpio_irq_ack(struct irq_data
*d
)
1488 /* the interrupt is already cleared before by reading ISR */
1491 static int gpio_irq_request_res(struct irq_data
*d
)
1493 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1494 unsigned pin
= d
->hwirq
;
1497 ret
= gpiochip_lock_as_irq(&at91_gpio
->chip
, pin
);
1499 dev_err(at91_gpio
->chip
.dev
, "unable to lock pind %lu IRQ\n",
1505 static void gpio_irq_release_res(struct irq_data
*d
)
1507 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1508 unsigned pin
= d
->hwirq
;
1510 gpiochip_unlock_as_irq(&at91_gpio
->chip
, pin
);
1515 static u32 wakeups
[MAX_GPIO_BANKS
];
1516 static u32 backups
[MAX_GPIO_BANKS
];
1518 static int gpio_irq_set_wake(struct irq_data
*d
, unsigned state
)
1520 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1521 unsigned bank
= at91_gpio
->pioc_idx
;
1522 unsigned mask
= 1 << d
->hwirq
;
1524 if (unlikely(bank
>= MAX_GPIO_BANKS
))
1528 wakeups
[bank
] |= mask
;
1530 wakeups
[bank
] &= ~mask
;
1532 irq_set_irq_wake(at91_gpio
->pioc_virq
, state
);
1537 void at91_pinctrl_gpio_suspend(void)
1541 for (i
= 0; i
< gpio_banks
; i
++) {
1547 pio
= gpio_chips
[i
]->regbase
;
1549 backups
[i
] = readl_relaxed(pio
+ PIO_IMR
);
1550 writel_relaxed(backups
[i
], pio
+ PIO_IDR
);
1551 writel_relaxed(wakeups
[i
], pio
+ PIO_IER
);
1554 clk_disable_unprepare(gpio_chips
[i
]->clock
);
1556 printk(KERN_DEBUG
"GPIO-%c may wake for %08x\n",
1561 void at91_pinctrl_gpio_resume(void)
1565 for (i
= 0; i
< gpio_banks
; i
++) {
1571 pio
= gpio_chips
[i
]->regbase
;
1574 clk_prepare_enable(gpio_chips
[i
]->clock
);
1576 writel_relaxed(wakeups
[i
], pio
+ PIO_IDR
);
1577 writel_relaxed(backups
[i
], pio
+ PIO_IER
);
1582 #define gpio_irq_set_wake NULL
1583 #endif /* CONFIG_PM */
1585 static struct irq_chip gpio_irqchip
= {
1587 .irq_ack
= gpio_irq_ack
,
1588 .irq_request_resources
= gpio_irq_request_res
,
1589 .irq_release_resources
= gpio_irq_release_res
,
1590 .irq_disable
= gpio_irq_mask
,
1591 .irq_mask
= gpio_irq_mask
,
1592 .irq_unmask
= gpio_irq_unmask
,
1593 /* .irq_set_type is set dynamically */
1594 .irq_set_wake
= gpio_irq_set_wake
,
1597 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
1599 struct irq_chip
*chip
= irq_get_chip(irq
);
1600 struct gpio_chip
*gpio_chip
= irq_desc_get_handler_data(desc
);
1601 struct at91_gpio_chip
*at91_gpio
= container_of(gpio_chip
,
1602 struct at91_gpio_chip
, chip
);
1604 void __iomem
*pio
= at91_gpio
->regbase
;
1608 chained_irq_enter(chip
, desc
);
1610 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1611 * When there are none pending, we're finished unless we need
1612 * to process multiple banks (like ID_PIOCDE on sam9263).
1614 isr
= readl_relaxed(pio
+ PIO_ISR
) & readl_relaxed(pio
+ PIO_IMR
);
1616 if (!at91_gpio
->next
)
1618 at91_gpio
= at91_gpio
->next
;
1619 pio
= at91_gpio
->regbase
;
1620 gpio_chip
= &at91_gpio
->chip
;
1624 for_each_set_bit(n
, &isr
, BITS_PER_LONG
) {
1625 generic_handle_irq(irq_find_mapping(
1626 gpio_chip
->irqdomain
, n
));
1629 chained_irq_exit(chip
, desc
);
1630 /* now it may re-trigger */
1633 static int at91_gpio_of_irq_setup(struct platform_device
*pdev
,
1634 struct at91_gpio_chip
*at91_gpio
)
1636 struct gpio_chip
*gpiochip_prev
= NULL
;
1637 struct at91_gpio_chip
*prev
= NULL
;
1638 struct irq_data
*d
= irq_get_irq_data(at91_gpio
->pioc_virq
);
1641 at91_gpio
->pioc_hwirq
= irqd_to_hwirq(d
);
1643 /* Setup proper .irq_set_type function */
1644 gpio_irqchip
.irq_set_type
= at91_gpio
->ops
->irq_type
;
1646 /* Disable irqs of this PIO controller */
1647 writel_relaxed(~0, at91_gpio
->regbase
+ PIO_IDR
);
1650 * Let the generic code handle this edge IRQ, the the chained
1651 * handler will perform the actual work of handling the parent
1654 ret
= gpiochip_irqchip_add(&at91_gpio
->chip
,
1658 IRQ_TYPE_EDGE_BOTH
);
1660 dev_err(&pdev
->dev
, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1661 at91_gpio
->pioc_idx
);
1665 /* The top level handler handles one bank of GPIOs, except
1666 * on some SoC it can handle up to three...
1667 * We only set up the handler for the first of the list.
1669 gpiochip_prev
= irq_get_handler_data(at91_gpio
->pioc_virq
);
1670 if (!gpiochip_prev
) {
1671 /* Then register the chain on the parent IRQ */
1672 gpiochip_set_chained_irqchip(&at91_gpio
->chip
,
1674 at91_gpio
->pioc_virq
,
1679 prev
= container_of(gpiochip_prev
, struct at91_gpio_chip
, chip
);
1681 /* we can only have 2 banks before */
1682 for (i
= 0; i
< 2; i
++) {
1686 prev
->next
= at91_gpio
;
1694 /* This structure is replicated for each GPIO block allocated at probe time */
1695 static struct gpio_chip at91_gpio_template
= {
1696 .request
= at91_gpio_request
,
1697 .free
= at91_gpio_free
,
1698 .get_direction
= at91_gpio_get_direction
,
1699 .direction_input
= at91_gpio_direction_input
,
1700 .get
= at91_gpio_get
,
1701 .direction_output
= at91_gpio_direction_output
,
1702 .set
= at91_gpio_set
,
1703 .set_multiple
= at91_gpio_set_multiple
,
1704 .dbg_show
= at91_gpio_dbg_show
,
1706 .ngpio
= MAX_NB_GPIO_PER_BANK
,
1709 static const struct of_device_id at91_gpio_of_match
[] = {
1710 { .compatible
= "atmel,at91sam9x5-gpio", .data
= &at91sam9x5_ops
, },
1711 { .compatible
= "atmel,at91rm9200-gpio", .data
= &at91rm9200_ops
},
1715 static int at91_gpio_probe(struct platform_device
*pdev
)
1717 struct device_node
*np
= pdev
->dev
.of_node
;
1718 struct resource
*res
;
1719 struct at91_gpio_chip
*at91_chip
= NULL
;
1720 struct gpio_chip
*chip
;
1721 struct pinctrl_gpio_range
*range
;
1724 int alias_idx
= of_alias_get_id(np
, "gpio");
1728 BUG_ON(alias_idx
>= ARRAY_SIZE(gpio_chips
));
1729 if (gpio_chips
[alias_idx
]) {
1734 irq
= platform_get_irq(pdev
, 0);
1740 at91_chip
= devm_kzalloc(&pdev
->dev
, sizeof(*at91_chip
), GFP_KERNEL
);
1746 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1747 at91_chip
->regbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1748 if (IS_ERR(at91_chip
->regbase
)) {
1749 ret
= PTR_ERR(at91_chip
->regbase
);
1753 at91_chip
->ops
= (struct at91_pinctrl_mux_ops
*)
1754 of_match_device(at91_gpio_of_match
, &pdev
->dev
)->data
;
1755 at91_chip
->pioc_virq
= irq
;
1756 at91_chip
->pioc_idx
= alias_idx
;
1758 at91_chip
->clock
= devm_clk_get(&pdev
->dev
, NULL
);
1759 if (IS_ERR(at91_chip
->clock
)) {
1760 dev_err(&pdev
->dev
, "failed to get clock, ignoring.\n");
1761 ret
= PTR_ERR(at91_chip
->clock
);
1765 ret
= clk_prepare(at91_chip
->clock
);
1767 goto clk_prepare_err
;
1769 /* enable PIO controller's clock */
1770 ret
= clk_enable(at91_chip
->clock
);
1772 dev_err(&pdev
->dev
, "failed to enable clock, ignoring.\n");
1773 goto clk_enable_err
;
1776 at91_chip
->chip
= at91_gpio_template
;
1778 chip
= &at91_chip
->chip
;
1780 chip
->label
= dev_name(&pdev
->dev
);
1781 chip
->dev
= &pdev
->dev
;
1782 chip
->owner
= THIS_MODULE
;
1783 chip
->base
= alias_idx
* MAX_NB_GPIO_PER_BANK
;
1785 if (!of_property_read_u32(np
, "#gpio-lines", &ngpio
)) {
1786 if (ngpio
>= MAX_NB_GPIO_PER_BANK
)
1787 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1788 alias_idx
, MAX_NB_GPIO_PER_BANK
, MAX_NB_GPIO_PER_BANK
);
1790 chip
->ngpio
= ngpio
;
1793 names
= devm_kzalloc(&pdev
->dev
, sizeof(char *) * chip
->ngpio
,
1798 goto clk_enable_err
;
1801 for (i
= 0; i
< chip
->ngpio
; i
++)
1802 names
[i
] = kasprintf(GFP_KERNEL
, "pio%c%d", alias_idx
+ 'A', i
);
1804 chip
->names
= (const char *const *)names
;
1806 range
= &at91_chip
->range
;
1807 range
->name
= chip
->label
;
1808 range
->id
= alias_idx
;
1809 range
->pin_base
= range
->base
= range
->id
* MAX_NB_GPIO_PER_BANK
;
1811 range
->npins
= chip
->ngpio
;
1814 ret
= gpiochip_add(chip
);
1816 goto gpiochip_add_err
;
1818 gpio_chips
[alias_idx
] = at91_chip
;
1819 gpio_banks
= max(gpio_banks
, alias_idx
+ 1);
1821 ret
= at91_gpio_of_irq_setup(pdev
, at91_chip
);
1825 dev_info(&pdev
->dev
, "at address %p\n", at91_chip
->regbase
);
1830 gpiochip_remove(chip
);
1832 clk_disable(at91_chip
->clock
);
1834 clk_unprepare(at91_chip
->clock
);
1837 dev_err(&pdev
->dev
, "Failure %i for GPIO %i\n", ret
, alias_idx
);
1842 static struct platform_driver at91_gpio_driver
= {
1844 .name
= "gpio-at91",
1845 .of_match_table
= at91_gpio_of_match
,
1847 .probe
= at91_gpio_probe
,
1850 static struct platform_driver at91_pinctrl_driver
= {
1852 .name
= "pinctrl-at91",
1853 .of_match_table
= at91_pinctrl_of_match
,
1855 .probe
= at91_pinctrl_probe
,
1856 .remove
= at91_pinctrl_remove
,
1859 static int __init
at91_pinctrl_init(void)
1863 ret
= platform_driver_register(&at91_gpio_driver
);
1866 return platform_driver_register(&at91_pinctrl_driver
);
1868 arch_initcall(at91_pinctrl_init
);
1870 static void __exit
at91_pinctrl_exit(void)
1872 platform_driver_unregister(&at91_pinctrl_driver
);
1875 module_exit(at91_pinctrl_exit
);
1876 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1877 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1878 MODULE_LICENSE("GPL v2");