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ARM: rockchip: fix broken build
[linux/fpc-iii.git] / drivers / pinctrl / qcom / pinctrl-spmi-mpp.c
blob3121de9b63310c7ed8f36a9fe6fbcd4faa6f6a8a
1 /*
2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/gpio.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24
25 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
26
27 #include "../core.h"
28 #include "../pinctrl-utils.h"
29
30 #define PMIC_MPP_ADDRESS_RANGE 0x100
31
32 /*
33 * Pull Up Values - it indicates whether a pull-up should be
34 * applied for bidirectional mode only. The hardware ignores the
35 * configuration when operating in other modes.
36 */
37 #define PMIC_MPP_PULL_UP_0P6KOHM 0
38 #define PMIC_MPP_PULL_UP_10KOHM 1
39 #define PMIC_MPP_PULL_UP_30KOHM 2
40 #define PMIC_MPP_PULL_UP_OPEN 3
41
42 /* type registers base address bases */
43 #define PMIC_MPP_REG_TYPE 0x4
44 #define PMIC_MPP_REG_SUBTYPE 0x5
45
46 /* mpp peripheral type and subtype values */
47 #define PMIC_MPP_TYPE 0x11
48 #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3
49 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4
50 #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5
51 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6
52 #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7
53 #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf
54
55 #define PMIC_MPP_REG_RT_STS 0x10
56 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
57
58 /* control register base address bases */
59 #define PMIC_MPP_REG_MODE_CTL 0x40
60 #define PMIC_MPP_REG_DIG_VIN_CTL 0x41
61 #define PMIC_MPP_REG_DIG_PULL_CTL 0x42
62 #define PMIC_MPP_REG_DIG_IN_CTL 0x43
63 #define PMIC_MPP_REG_EN_CTL 0x46
64 #define PMIC_MPP_REG_AIN_CTL 0x4a
65
66 /* PMIC_MPP_REG_MODE_CTL */
67 #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1
68 #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1
69 #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7
70 #define PMIC_MPP_REG_MODE_DIR_SHIFT 4
71 #define PMIC_MPP_REG_MODE_DIR_MASK 0x7
72
73 /* PMIC_MPP_REG_DIG_VIN_CTL */
74 #define PMIC_MPP_REG_VIN_SHIFT 0
75 #define PMIC_MPP_REG_VIN_MASK 0x7
76
77 /* PMIC_MPP_REG_DIG_PULL_CTL */
78 #define PMIC_MPP_REG_PULL_SHIFT 0
79 #define PMIC_MPP_REG_PULL_MASK 0x7
80
81 /* PMIC_MPP_REG_EN_CTL */
82 #define PMIC_MPP_REG_MASTER_EN_SHIFT 7
83
84 /* PMIC_MPP_REG_AIN_CTL */
85 #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0
86 #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7
87
88 #define PMIC_MPP_PHYSICAL_OFFSET 1
89
90 /* Qualcomm specific pin configurations */
91 #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1)
92 #define PMIC_MPP_CONF_ANALOG_MODE (PIN_CONFIG_END + 2)
93
94 /**
95 * struct pmic_mpp_pad - keep current MPP settings
96 * @base: Address base in SPMI device.
97 * @irq: IRQ number which this MPP generate.
98 * @is_enabled: Set to false when MPP should be put in high Z state.
99 * @out_value: Cached pin output value.
100 * @output_enabled: Set to true if MPP output logic is enabled.
101 * @input_enabled: Set to true if MPP input buffer logic is enabled.
102 * @analog_mode: Set to true when MPP should operate in Analog Input, Analog
103 * Output or Bidirectional Analog mode.
104 * @num_sources: Number of power-sources supported by this MPP.
105 * @power_source: Current power-source used.
106 * @amux_input: Set the source for analog input.
107 * @pullup: Pullup resistor value. Valid in Bidirectional mode only.
108 * @function: See pmic_mpp_functions[].
109 */
110 struct pmic_mpp_pad {
111 u16 base;
112 int irq;
113 bool is_enabled;
114 bool out_value;
115 bool output_enabled;
116 bool input_enabled;
117 bool analog_mode;
118 unsigned int num_sources;
119 unsigned int power_source;
120 unsigned int amux_input;
121 unsigned int pullup;
122 unsigned int function;
123 };
124
125 struct pmic_mpp_state {
126 struct device *dev;
127 struct regmap *map;
128 struct pinctrl_dev *ctrl;
129 struct gpio_chip chip;
130 };
131
132 struct pmic_mpp_bindings {
133 const char *property;
134 unsigned param;
135 };
136
137 static struct pmic_mpp_bindings pmic_mpp_bindings[] = {
138 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE},
139 {"qcom,analog-mode", PMIC_MPP_CONF_ANALOG_MODE},
140 };
141
142 static const char *const pmic_mpp_groups[] = {
143 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
144 };
145
146 static const char *const pmic_mpp_functions[] = {
147 PMIC_MPP_FUNC_NORMAL, PMIC_MPP_FUNC_PAIRED,
148 "reserved1", "reserved2",
149 PMIC_MPP_FUNC_DTEST1, PMIC_MPP_FUNC_DTEST2,
150 PMIC_MPP_FUNC_DTEST3, PMIC_MPP_FUNC_DTEST4,
151 };
152
153 static inline struct pmic_mpp_state *to_mpp_state(struct gpio_chip *chip)
154 {
155 return container_of(chip, struct pmic_mpp_state, chip);
156 };
157
158 static int pmic_mpp_read(struct pmic_mpp_state *state,
159 struct pmic_mpp_pad *pad, unsigned int addr)
160 {
161 unsigned int val;
162 int ret;
163
164 ret = regmap_read(state->map, pad->base + addr, &val);
165 if (ret < 0)
166 dev_err(state->dev, "read 0x%x failed\n", addr);
167 else
168 ret = val;
169
170 return ret;
171 }
172
173 static int pmic_mpp_write(struct pmic_mpp_state *state,
174 struct pmic_mpp_pad *pad, unsigned int addr,
175 unsigned int val)
176 {
177 int ret;
178
179 ret = regmap_write(state->map, pad->base + addr, val);
180 if (ret < 0)
181 dev_err(state->dev, "write 0x%x failed\n", addr);
182
183 return ret;
184 }
185
186 static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev)
187 {
188 /* Every PIN is a group */
189 return pctldev->desc->npins;
190 }
191
192 static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev,
193 unsigned pin)
194 {
195 return pctldev->desc->pins[pin].name;
196 }
197
198 static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev,
199 unsigned pin,
200 const unsigned **pins, unsigned *num_pins)
201 {
202 *pins = &pctldev->desc->pins[pin].number;
203 *num_pins = 1;
204 return 0;
205 }
206
207 static int pmic_mpp_parse_dt_config(struct device_node *np,
208 struct pinctrl_dev *pctldev,
209 unsigned long **configs,
210 unsigned int *nconfs)
211 {
212 struct pmic_mpp_bindings *par;
213 unsigned long cfg;
214 int ret, i;
215 u32 val;
216
217 for (i = 0; i < ARRAY_SIZE(pmic_mpp_bindings); i++) {
218 par = &pmic_mpp_bindings[i];
219 ret = of_property_read_u32(np, par->property, &val);
220
221 /* property not found */
222 if (ret == -EINVAL)
223 continue;
224
225 /* use zero as default value, when no value is specified */
226 if (ret)
227 val = 0;
228
229 dev_dbg(pctldev->dev, "found %s with value %u\n",
230 par->property, val);
231
232 cfg = pinconf_to_config_packed(par->param, val);
233
234 ret = pinctrl_utils_add_config(pctldev, configs, nconfs, cfg);
235 if (ret)
236 return ret;
237 }
238
239 return 0;
240 }
241
242 static int pmic_mpp_dt_subnode_to_map(struct pinctrl_dev *pctldev,
243 struct device_node *np,
244 struct pinctrl_map **map,
245 unsigned *reserv, unsigned *nmaps,
246 enum pinctrl_map_type type)
247 {
248 unsigned long *configs = NULL;
249 unsigned nconfs = 0;
250 struct property *prop;
251 const char *group;
252 int ret;
253
254 ret = pmic_mpp_parse_dt_config(np, pctldev, &configs, &nconfs);
255 if (ret < 0)
256 return ret;
257
258 if (!nconfs)
259 return 0;
260
261 ret = of_property_count_strings(np, "pins");
262 if (ret < 0)
263 goto exit;
264
265 ret = pinctrl_utils_reserve_map(pctldev, map, reserv, nmaps, ret);
266 if (ret < 0)
267 goto exit;
268
269 of_property_for_each_string(np, "pins", prop, group) {
270 ret = pinctrl_utils_add_map_configs(pctldev, map,
271 reserv, nmaps, group,
272 configs, nconfs, type);
273 if (ret < 0)
274 break;
275 }
276 exit:
277 kfree(configs);
278 return ret;
279 }
280
281 static int pmic_mpp_dt_node_to_map(struct pinctrl_dev *pctldev,
282 struct device_node *np_config,
283 struct pinctrl_map **map, unsigned *nmaps)
284 {
285 struct device_node *np;
286 enum pinctrl_map_type type;
287 unsigned reserv;
288 int ret;
289
290 ret = 0;
291 *map = NULL;
292 *nmaps = 0;
293 reserv = 0;
294 type = PIN_MAP_TYPE_CONFIGS_GROUP;
295
296 for_each_child_of_node(np_config, np) {
297 ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
298 &reserv, nmaps, type);
299 if (ret)
300 break;
301
302 ret = pmic_mpp_dt_subnode_to_map(pctldev, np, map, &reserv,
303 nmaps, type);
304 if (ret)
305 break;
306 }
307
308 if (ret < 0)
309 pinctrl_utils_dt_free_map(pctldev, *map, *nmaps);
310
311 return ret;
312 }
313
314 static const struct pinctrl_ops pmic_mpp_pinctrl_ops = {
315 .get_groups_count = pmic_mpp_get_groups_count,
316 .get_group_name = pmic_mpp_get_group_name,
317 .get_group_pins = pmic_mpp_get_group_pins,
318 .dt_node_to_map = pmic_mpp_dt_node_to_map,
319 .dt_free_map = pinctrl_utils_dt_free_map,
320 };
321
322 static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev)
323 {
324 return ARRAY_SIZE(pmic_mpp_functions);
325 }
326
327 static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev,
328 unsigned function)
329 {
330 return pmic_mpp_functions[function];
331 }
332
333 static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev,
334 unsigned function,
335 const char *const **groups,
336 unsigned *const num_qgroups)
337 {
338 *groups = pmic_mpp_groups;
339 *num_qgroups = pctldev->desc->npins;
340 return 0;
341 }
342
343 static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
344 unsigned pin)
345 {
346 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
347 struct pmic_mpp_pad *pad;
348 unsigned int val;
349 int ret;
350
351 pad = pctldev->desc->pins[pin].drv_data;
352
353 pad->function = function;
354
355 if (!pad->analog_mode) {
356 val = 0; /* just digital input */
357 if (pad->output_enabled) {
358 if (pad->input_enabled)
359 val = 2; /* digital input and output */
360 else
361 val = 1; /* just digital output */
362 }
363 } else {
364 val = 4; /* just analog input */
365 if (pad->output_enabled) {
366 if (pad->input_enabled)
367 val = 3; /* analog input and output */
368 else
369 val = 5; /* just analog output */
370 }
371 }
372
373 val = val << PMIC_MPP_REG_MODE_DIR_SHIFT;
374 val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
375 val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK;
376
377 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
378 if (ret < 0)
379 return ret;
380
381 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
382
383 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
384 }
385
386 static const struct pinmux_ops pmic_mpp_pinmux_ops = {
387 .get_functions_count = pmic_mpp_get_functions_count,
388 .get_function_name = pmic_mpp_get_function_name,
389 .get_function_groups = pmic_mpp_get_function_groups,
390 .set_mux = pmic_mpp_set_mux,
391 };
392
393 static int pmic_mpp_config_get(struct pinctrl_dev *pctldev,
394 unsigned int pin, unsigned long *config)
395 {
396 unsigned param = pinconf_to_config_param(*config);
397 struct pmic_mpp_pad *pad;
398 unsigned arg = 0;
399
400 pad = pctldev->desc->pins[pin].drv_data;
401
402 switch (param) {
403 case PIN_CONFIG_BIAS_DISABLE:
404 arg = pad->pullup == PMIC_MPP_PULL_UP_OPEN;
405 break;
406 case PIN_CONFIG_BIAS_PULL_UP:
407 switch (pad->pullup) {
408 case PMIC_MPP_PULL_UP_OPEN:
409 arg = 0;
410 break;
411 case PMIC_MPP_PULL_UP_0P6KOHM:
412 arg = 600;
413 break;
414 case PMIC_MPP_PULL_UP_10KOHM:
415 arg = 10000;
416 break;
417 case PMIC_MPP_PULL_UP_30KOHM:
418 arg = 30000;
419 break;
420 default:
421 return -EINVAL;
422 }
423 break;
424 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
425 arg = !pad->is_enabled;
426 break;
427 case PIN_CONFIG_POWER_SOURCE:
428 arg = pad->power_source;
429 break;
430 case PIN_CONFIG_INPUT_ENABLE:
431 arg = pad->input_enabled;
432 break;
433 case PIN_CONFIG_OUTPUT:
434 arg = pad->out_value;
435 break;
436 case PMIC_MPP_CONF_AMUX_ROUTE:
437 arg = pad->amux_input;
438 break;
439 case PMIC_MPP_CONF_ANALOG_MODE:
440 arg = pad->analog_mode;
441 break;
442 default:
443 return -EINVAL;
444 }
445
446 /* Convert register value to pinconf value */
447 *config = pinconf_to_config_packed(param, arg);
448 return 0;
449 }
450
451 static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
452 unsigned long *configs, unsigned nconfs)
453 {
454 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
455 struct pmic_mpp_pad *pad;
456 unsigned param, arg;
457 unsigned int val;
458 int i, ret;
459
460 pad = pctldev->desc->pins[pin].drv_data;
461
462 for (i = 0; i < nconfs; i++) {
463 param = pinconf_to_config_param(configs[i]);
464 arg = pinconf_to_config_argument(configs[i]);
465
466 switch (param) {
467 case PIN_CONFIG_BIAS_DISABLE:
468 pad->pullup = PMIC_MPP_PULL_UP_OPEN;
469 break;
470 case PIN_CONFIG_BIAS_PULL_UP:
471 switch (arg) {
472 case 600:
473 pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM;
474 break;
475 case 10000:
476 pad->pullup = PMIC_MPP_PULL_UP_10KOHM;
477 break;
478 case 30000:
479 pad->pullup = PMIC_MPP_PULL_UP_30KOHM;
480 break;
481 default:
482 return -EINVAL;
483 }
484 break;
485 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
486 pad->is_enabled = false;
487 break;
488 case PIN_CONFIG_POWER_SOURCE:
489 if (arg >= pad->num_sources)
490 return -EINVAL;
491 pad->power_source = arg;
492 break;
493 case PIN_CONFIG_INPUT_ENABLE:
494 pad->input_enabled = arg ? true : false;
495 break;
496 case PIN_CONFIG_OUTPUT:
497 pad->output_enabled = true;
498 pad->out_value = arg;
499 break;
500 case PMIC_MPP_CONF_AMUX_ROUTE:
501 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4)
502 return -EINVAL;
503 pad->amux_input = arg;
504 break;
505 case PMIC_MPP_CONF_ANALOG_MODE:
506 pad->analog_mode = true;
507 break;
508 default:
509 return -EINVAL;
510 }
511 }
512
513 val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT;
514
515 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val);
516 if (ret < 0)
517 return ret;
518
519 val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
520
521 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, val);
522 if (ret < 0)
523 return ret;
524
525 val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK;
526
527 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val);
528 if (ret < 0)
529 return ret;
530
531 if (!pad->analog_mode) {
532 val = 0; /* just digital input */
533 if (pad->output_enabled) {
534 if (pad->input_enabled)
535 val = 2; /* digital input and output */
536 else
537 val = 1; /* just digital output */
538 }
539 } else {
540 val = 4; /* just analog input */
541 if (pad->output_enabled) {
542 if (pad->input_enabled)
543 val = 3; /* analog input and output */
544 else
545 val = 5; /* just analog output */
546 }
547 }
548
549 val = val << PMIC_MPP_REG_MODE_DIR_SHIFT;
550 val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
551 val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK;
552
553 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
554 }
555
556 static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
557 struct seq_file *s, unsigned pin)
558 {
559 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
560 struct pmic_mpp_pad *pad;
561 int ret, val;
562
563 static const char *const biases[] = {
564 "0.6kOhm", "10kOhm", "30kOhm", "Disabled"
565 };
566
567
568 pad = pctldev->desc->pins[pin].drv_data;
569
570 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET);
571
572 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL);
573
574 if (val < 0 || !(val >> PMIC_MPP_REG_MASTER_EN_SHIFT)) {
575 seq_puts(s, " ---");
576 } else {
577
578 if (pad->input_enabled) {
579 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
580 if (ret < 0)
581 return;
582
583 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
584 pad->out_value = ret;
585 }
586
587 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
588 seq_printf(s, " %-4s", pad->analog_mode ? "ana" : "dig");
589 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
590 seq_printf(s, " vin-%d", pad->power_source);
591 seq_printf(s, " %-8s", biases[pad->pullup]);
592 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
593 }
594 }
595
596 static const struct pinconf_ops pmic_mpp_pinconf_ops = {
597 .pin_config_group_get = pmic_mpp_config_get,
598 .pin_config_group_set = pmic_mpp_config_set,
599 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show,
600 };
601
602 static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin)
603 {
604 struct pmic_mpp_state *state = to_mpp_state(chip);
605 unsigned long config;
606
607 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
608
609 return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
610 }
611
612 static int pmic_mpp_direction_output(struct gpio_chip *chip,
613 unsigned pin, int val)
614 {
615 struct pmic_mpp_state *state = to_mpp_state(chip);
616 unsigned long config;
617
618 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
619
620 return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
621 }
622
623 static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin)
624 {
625 struct pmic_mpp_state *state = to_mpp_state(chip);
626 struct pmic_mpp_pad *pad;
627 int ret;
628
629 pad = state->ctrl->desc->pins[pin].drv_data;
630
631 if (pad->input_enabled) {
632 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
633 if (ret < 0)
634 return ret;
635
636 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
637 }
638
639 return pad->out_value;
640 }
641
642 static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value)
643 {
644 struct pmic_mpp_state *state = to_mpp_state(chip);
645 unsigned long config;
646
647 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
648
649 pmic_mpp_config_set(state->ctrl, pin, &config, 1);
650 }
651
652 static int pmic_mpp_request(struct gpio_chip *chip, unsigned base)
653 {
654 return pinctrl_request_gpio(chip->base + base);
655 }
656
657 static void pmic_mpp_free(struct gpio_chip *chip, unsigned base)
658 {
659 pinctrl_free_gpio(chip->base + base);
660 }
661
662 static int pmic_mpp_of_xlate(struct gpio_chip *chip,
663 const struct of_phandle_args *gpio_desc,
664 u32 *flags)
665 {
666 if (chip->of_gpio_n_cells < 2)
667 return -EINVAL;
668
669 if (flags)
670 *flags = gpio_desc->args[1];
671
672 return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET;
673 }
674
675 static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin)
676 {
677 struct pmic_mpp_state *state = to_mpp_state(chip);
678 struct pmic_mpp_pad *pad;
679
680 pad = state->ctrl->desc->pins[pin].drv_data;
681
682 return pad->irq;
683 }
684
685 static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
686 {
687 struct pmic_mpp_state *state = to_mpp_state(chip);
688 unsigned i;
689
690 for (i = 0; i < chip->ngpio; i++) {
691 pmic_mpp_config_dbg_show(state->ctrl, s, i);
692 seq_puts(s, "\n");
693 }
694 }
695
696 static const struct gpio_chip pmic_mpp_gpio_template = {
697 .direction_input = pmic_mpp_direction_input,
698 .direction_output = pmic_mpp_direction_output,
699 .get = pmic_mpp_get,
700 .set = pmic_mpp_set,
701 .request = pmic_mpp_request,
702 .free = pmic_mpp_free,
703 .of_xlate = pmic_mpp_of_xlate,
704 .to_irq = pmic_mpp_to_irq,
705 .dbg_show = pmic_mpp_dbg_show,
706 };
707
708 static int pmic_mpp_populate(struct pmic_mpp_state *state,
709 struct pmic_mpp_pad *pad)
710 {
711 int type, subtype, val, dir;
712
713 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE);
714 if (type < 0)
715 return type;
716
717 if (type != PMIC_MPP_TYPE) {
718 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
719 type, pad->base);
720 return -ENODEV;
721 }
722
723 subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE);
724 if (subtype < 0)
725 return subtype;
726
727 switch (subtype) {
728 case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT:
729 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT:
730 case PMIC_MPP_SUBTYPE_4CH_NO_SINK:
731 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK:
732 case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC:
733 pad->num_sources = 4;
734 break;
735 case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC:
736 pad->num_sources = 8;
737 break;
738 default:
739 dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n",
740 subtype, pad->base);
741 return -ENODEV;
742 }
743
744 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL);
745 if (val < 0)
746 return val;
747
748 pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK;
749
750 dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT;
751 dir &= PMIC_MPP_REG_MODE_DIR_MASK;
752
753 switch (dir) {
754 case 0:
755 pad->input_enabled = true;
756 pad->output_enabled = false;
757 pad->analog_mode = false;
758 break;
759 case 1:
760 pad->input_enabled = false;
761 pad->output_enabled = true;
762 pad->analog_mode = false;
763 break;
764 case 2:
765 pad->input_enabled = true;
766 pad->output_enabled = true;
767 pad->analog_mode = false;
768 break;
769 case 3:
770 pad->input_enabled = true;
771 pad->output_enabled = true;
772 pad->analog_mode = true;
773 break;
774 case 4:
775 pad->input_enabled = true;
776 pad->output_enabled = false;
777 pad->analog_mode = true;
778 break;
779 case 5:
780 pad->input_enabled = false;
781 pad->output_enabled = true;
782 pad->analog_mode = true;
783 break;
784 default:
785 dev_err(state->dev, "unknown MPP direction\n");
786 return -ENODEV;
787 }
788
789 pad->function = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
790 pad->function &= PMIC_MPP_REG_MODE_FUNCTION_MASK;
791
792 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL);
793 if (val < 0)
794 return val;
795
796 pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT;
797 pad->power_source &= PMIC_MPP_REG_VIN_MASK;
798
799 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
800 if (val < 0)
801 return val;
802
803 pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
804 pad->pullup &= PMIC_MPP_REG_PULL_MASK;
805
806 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL);
807 if (val < 0)
808 return val;
809
810 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT;
811 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK;
812
813 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
814 pad->is_enabled = true;
815 return 0;
816 }
817
818 static int pmic_mpp_probe(struct platform_device *pdev)
819 {
820 struct device *dev = &pdev->dev;
821 struct pinctrl_pin_desc *pindesc;
822 struct pinctrl_desc *pctrldesc;
823 struct pmic_mpp_pad *pad, *pads;
824 struct pmic_mpp_state *state;
825 int ret, npins, i;
826 u32 res[2];
827
828 ret = of_property_read_u32_array(dev->of_node, "reg", res, 2);
829 if (ret < 0) {
830 dev_err(dev, "missing base address and/or range");
831 return ret;
832 }
833
834 npins = res[1] / PMIC_MPP_ADDRESS_RANGE;
835 if (!npins)
836 return -EINVAL;
837
838 BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups));
839
840 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
841 if (!state)
842 return -ENOMEM;
843
844 platform_set_drvdata(pdev, state);
845
846 state->dev = &pdev->dev;
847 state->map = dev_get_regmap(dev->parent, NULL);
848
849 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
850 if (!pindesc)
851 return -ENOMEM;
852
853 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
854 if (!pads)
855 return -ENOMEM;
856
857 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
858 if (!pctrldesc)
859 return -ENOMEM;
860
861 pctrldesc->pctlops = &pmic_mpp_pinctrl_ops;
862 pctrldesc->pmxops = &pmic_mpp_pinmux_ops;
863 pctrldesc->confops = &pmic_mpp_pinconf_ops;
864 pctrldesc->owner = THIS_MODULE;
865 pctrldesc->name = dev_name(dev);
866 pctrldesc->pins = pindesc;
867 pctrldesc->npins = npins;
868
869 for (i = 0; i < npins; i++, pindesc++) {
870 pad = &pads[i];
871 pindesc->drv_data = pad;
872 pindesc->number = i;
873 pindesc->name = pmic_mpp_groups[i];
874
875 pad->irq = platform_get_irq(pdev, i);
876 if (pad->irq < 0)
877 return pad->irq;
878
879 pad->base = res[0] + i * PMIC_MPP_ADDRESS_RANGE;
880
881 ret = pmic_mpp_populate(state, pad);
882 if (ret < 0)
883 return ret;
884 }
885
886 state->chip = pmic_mpp_gpio_template;
887 state->chip.dev = dev;
888 state->chip.base = -1;
889 state->chip.ngpio = npins;
890 state->chip.label = dev_name(dev);
891 state->chip.of_gpio_n_cells = 2;
892 state->chip.can_sleep = false;
893
894 state->ctrl = pinctrl_register(pctrldesc, dev, state);
895 if (IS_ERR(state->ctrl))
896 return PTR_ERR(state->ctrl);
897
898 ret = gpiochip_add(&state->chip);
899 if (ret) {
900 dev_err(state->dev, "can't add gpio chip\n");
901 goto err_chip;
902 }
903
904 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
905 if (ret) {
906 dev_err(dev, "failed to add pin range\n");
907 goto err_range;
908 }
909
910 return 0;
911
912 err_range:
913 gpiochip_remove(&state->chip);
914 err_chip:
915 pinctrl_unregister(state->ctrl);
916 return ret;
917 }
918
919 static int pmic_mpp_remove(struct platform_device *pdev)
920 {
921 struct pmic_mpp_state *state = platform_get_drvdata(pdev);
922
923 gpiochip_remove(&state->chip);
924 pinctrl_unregister(state->ctrl);
925 return 0;
926 }
927
928 static const struct of_device_id pmic_mpp_of_match[] = {
929 { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */
930 { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */
931 { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */
932 { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */
933 { },
934 };
935
936 MODULE_DEVICE_TABLE(of, pmic_mpp_of_match);
937
938 static struct platform_driver pmic_mpp_driver = {
939 .driver = {
940 .name = "qcom-spmi-mpp",
941 .of_match_table = pmic_mpp_of_match,
942 },
943 .probe = pmic_mpp_probe,
944 .remove = pmic_mpp_remove,
945 };
946
947 module_platform_driver(pmic_mpp_driver);
948
949 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
950 MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver");
951 MODULE_ALIAS("platform:qcom-spmi-mpp");
952 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support