drivers/pinctrl/sh-pfc/pfc-r8a7790.c

   1 /*
   2  * R8A7790 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Electronics Corporation
   5  * Copyright (C) 2013  Magnus Damm
   6  * Copyright (C) 2012  Renesas Solutions Corp.
   7  * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; version 2 of the
  12  * License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/platform_data/gpio-rcar.h>
  26
  27 #include "core.h"
  28 #include "sh_pfc.h"
  29
  30 #define CPU_ALL_PORT(fn, sfx)                                           \
  31         PORT_GP_32(0, fn, sfx),                                         \
  32         PORT_GP_32(1, fn, sfx),                                         \
  33         PORT_GP_32(2, fn, sfx),                                         \
  34         PORT_GP_32(3, fn, sfx),                                         \
  35         PORT_GP_32(4, fn, sfx),                                         \
  36         PORT_GP_32(5, fn, sfx)
  37
  38 enum {
  39         PINMUX_RESERVED = 0,
  40
  41         PINMUX_DATA_BEGIN,
  42         GP_ALL(DATA),
  43         PINMUX_DATA_END,
  44
  45         PINMUX_FUNCTION_BEGIN,
  46         GP_ALL(FN),
  47
  48         /* GPSR0 */
  49         FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
  50         FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
  51         FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
  52         FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
  53         FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
  54         FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
  55         FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
  56         FN_IP3_14_12, FN_IP3_17_15,
  57
  58         /* GPSR1 */
  59         FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
  60         FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
  61         FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
  62         FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
  63         FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
  64         FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
  65         FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
  66
  67         /* GPSR2 */
  68         FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
  69         FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
  70         FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
  71         FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
  72         FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
  73         FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
  74         FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
  75
  76         /* GPSR3 */
  77         FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
  78         FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
  79         FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
  80         FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
  81         FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
  82         FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
  83         FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
  84
  85         /* GPSR4 */
  86         FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
  87         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
  88         FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
  89         FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
  90         FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
  91         FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
  92         FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
  93         FN_IP14_15_12, FN_IP14_18_16,
  94
  95         /* GPSR5 */
  96         FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
  97         FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
  98         FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
  99         FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
 100         FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
 101         FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
 102         FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
 103
 104         /* IPSR0 */
 105         FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
 106         FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
 107         FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
 108         FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
 109         FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
 110         FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
 111         FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
 112         FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
 113         FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
 114         FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
 115         FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
 116         FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
 117         FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
 118         FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
 119
 120         /* IPSR1 */
 121         FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
 122         FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
 123         FN_SCIFA1_TXD_C, FN_AVB_TXD2,
 124         FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
 125         FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
 126         FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
 127         FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
 128         FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
 129         FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
 130         FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
 131         FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
 132         FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
 133         FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
 134         FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
 135         FN_A0, FN_PWM3, FN_A1, FN_PWM4,
 136
 137         /* IPSR2 */
 138         FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
 139         FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
 140         FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
 141         FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
 142         FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
 143         FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
 144         FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
 145         FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
 146         FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
 147         FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
 148         FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
 149
 150         /* IPSR3 */
 151         FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
 152         FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
 153         FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
 154         FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
 155         FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
 156         FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
 157         FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
 158         FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
 159         FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
 160         FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
 161         FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
 162         FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
 163         FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
 164
 165         /* IPSR4 */
 166         FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
 167         FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
 168         FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
 169         FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
 170         FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
 171         FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
 172         FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
 173         FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
 174         FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
 175         FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
 176         FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
 177         FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
 178         FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
 179         FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
 180         FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
 181
 182         /* IPSR5 */
 183         FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
 184         FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
 185         FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
 186         FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
 187         FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
 188         FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
 189         FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
 190         FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
 191         FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
 192         FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
 193         FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
 194         FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
 195         FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
 196         FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
 197         FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
 198         FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
 199         FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
 200         FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
 201         FN_SSI_WS78_B,
 202
 203         /* IPSR6 */
 204         FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
 205         FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
 206         FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
 207         FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
 208         FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
 209         FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
 210         FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
 211         FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
 212         FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
 213         FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
 214         FN_I2C2_SCL_E, FN_ETH_RX_ER,
 215         FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
 216         FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
 217         FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
 218         FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
 219         FN_HRX0_E, FN_STP_ISSYNC_0_B,
 220         FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
 221         FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
 222         FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
 223         FN_ETH_REF_CLK, FN_HCTS0_N_E,
 224         FN_STP_IVCXO27_1_B, FN_HRX0_F,
 225
 226         /* IPSR7 */
 227         FN_ETH_MDIO, FN_HRTS0_N_E,
 228         FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
 229         FN_HTX0_F, FN_BPFCLK_G,
 230         FN_ETH_TX_EN, FN_SIM0_CLK_C,
 231         FN_HRTS0_N_F, FN_ETH_MAGIC,
 232         FN_SIM0_RST_C, FN_ETH_TXD0,
 233         FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
 234         FN_ETH_MDC, FN_STP_ISD_1_B,
 235         FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
 236         FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
 237         FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
 238         FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
 239         FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
 240         FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
 241         FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
 242         FN_ATACS00_N, FN_AVB_RXD1,
 243         FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
 244
 245         /* IPSR8 */
 246         FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
 247         FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
 248         FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
 249         FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
 250         FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
 251         FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
 252         FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
 253         FN_VI1_CLK, FN_AVB_RX_DV,
 254         FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
 255         FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
 256         FN_SCIFA1_RXD_D, FN_AVB_MDC,
 257         FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
 258         FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
 259         FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
 260         FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
 261         FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
 262         FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
 263         FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
 264
 265         /* IPSR9 */
 266         FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
 267         FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
 268         FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
 269         FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
 270         FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
 271         FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
 272         FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
 273         FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
 274         FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
 275         FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
 276         FN_AVB_TX_EN, FN_SD1_CMD,
 277         FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
 278         FN_SD1_DAT0, FN_AVB_TX_CLK,
 279         FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
 280         FN_SCIFB0_TXD_B, FN_SD1_DAT2,
 281         FN_AVB_COL, FN_SCIFB0_CTS_N_B,
 282         FN_SD1_DAT3, FN_AVB_RXD0,
 283         FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
 284         FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
 285         FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
 286         FN_VI3_CLK_B,
 287
 288         /* IPSR10 */
 289         FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
 290         FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
 291         FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
 292         FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
 293         FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
 294         FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
 295         FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
 296         FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
 297         FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
 298         FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
 299         FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
 300         FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
 301         FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
 302         FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
 303         FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
 304         FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
 305         FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
 306         FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
 307         FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
 308         FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
 309         FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
 310         FN_GLO_I0_B, FN_VI3_DATA6_B,
 311
 312         /* IPSR11 */
 313         FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
 314         FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
 315         FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
 316         FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
 317         FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
 318         FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
 319         FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
 320         FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
 321         FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
 322         FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
 323         FN_FMIN_E, FN_FMIN_F,
 324         FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
 325         FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
 326         FN_I2C2_SDA_B, FN_MLB_DAT,
 327         FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
 328         FN_SSI_SCK0129, FN_CAN_CLK_B,
 329         FN_MOUT0,
 330
 331         /* IPSR12 */
 332         FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
 333         FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
 334         FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
 335         FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
 336         FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
 337         FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
 338         FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
 339         FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
 340         FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
 341         FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
 342         FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
 343         FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
 344         FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
 345         FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
 346         FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
 347         FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
 348         FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
 349         FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
 350         FN_CAN_DEBUGOUT4,
 351
 352         /* IPSR13 */
 353         FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
 354         FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
 355         FN_SCIFB1_CTS_N, FN_BPFCLK_D,
 356         FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
 357         FN_BPFCLK_F, FN_SSI_WS6,
 358         FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
 359         FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
 360         FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
 361         FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
 362         FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
 363         FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
 364         FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
 365         FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
 366         FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
 367         FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
 368         FN_BPFCLK_E, FN_SSI_SDATA7_B,
 369         FN_FMIN_G, FN_SSI_SDATA8,
 370         FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
 371         FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
 372         FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
 373         FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
 374         FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
 375
 376         /* IPSR14 */
 377         FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
 378         FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
 379         FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
 380         FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
 381         FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
 382         FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
 383         FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
 384         FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
 385         FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
 386         FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
 387         FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
 388         FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
 389         FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
 390         FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
 391         FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
 392         FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
 393         FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
 394         FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
 395         FN_HRTS0_N_C,
 396
 397         /* IPSR15 */
 398         FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
 399         FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
 400         FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
 401         FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
 402         FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
 403         FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
 404         FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
 405         FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
 406         FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
 407         FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
 408         FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
 409         FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
 410         FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
 411         FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
 412         FN_DU2_DG6, FN_LCDOUT14,
 413
 414         /* IPSR16 */
 415         FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
 416         FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
 417         FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
 418         FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
 419         FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
 420         FN_TCLK1_B,
 421
 422         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 423         FN_SEL_SCIF1_4,
 424         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
 425         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
 426         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 427         FN_SEL_SCIFB1_4,
 428         FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
 429         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
 430         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
 431         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 432         FN_SEL_SOF1_0, FN_SEL_SOF1_1,
 433         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 434         FN_SEL_SSI6_0, FN_SEL_SSI6_1,
 435         FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
 436         FN_SEL_VI3_0, FN_SEL_VI3_1,
 437         FN_SEL_VI2_0, FN_SEL_VI2_1,
 438         FN_SEL_VI1_0, FN_SEL_VI1_1,
 439         FN_SEL_VI0_0, FN_SEL_VI0_1,
 440         FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
 441         FN_SEL_LBS_0, FN_SEL_LBS_1,
 442         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 443         FN_SEL_SOF3_0, FN_SEL_SOF3_1,
 444         FN_SEL_SOF0_0, FN_SEL_SOF0_1,
 445
 446         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 447         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 448         FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
 449         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 450         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
 451         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
 452         FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 453         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
 454         FN_SEL_ADI_0, FN_SEL_ADI_1,
 455         FN_SEL_SSP_0, FN_SEL_SSP_1,
 456         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
 457         FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
 458         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
 459         FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
 460         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
 461         FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
 462         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 463
 464         FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
 465         FN_SEL_IIC0_0, FN_SEL_IIC0_1,
 466         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 467         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 468         FN_SEL_IIC2_4,
 469         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
 470         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 471         FN_SEL_I2C2_4,
 472         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
 473         PINMUX_FUNCTION_END,
 474
 475         PINMUX_MARK_BEGIN,
 476
 477         VI1_DATA7_VI1_B7_MARK,
 478
 479         USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
 480         USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
 481         DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
 482
 483         D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
 484         D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
 485         VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
 486         VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
 487         VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
 488         SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
 489         VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
 490         SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
 491         VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
 492         IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
 493         I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
 494         VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
 495         D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
 496         VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
 497
 498         D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
 499         VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
 500         SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
 501         VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
 502         SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
 503         VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
 504         D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
 505         VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
 506         D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
 507         VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
 508         SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
 509         VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
 510         D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
 511         VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
 512         A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
 513
 514         A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
 515         PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
 516         TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
 517         A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
 518         SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
 519         A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
 520         VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
 521         A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
 522         VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
 523         A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
 524         VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
 525
 526         A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
 527         VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
 528         A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
 529         VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
 530         A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
 531         MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
 532         VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
 533         ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
 534         ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
 535         A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
 536         AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
 537         ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
 538         VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
 539
 540         A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
 541         A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
 542         VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
 543         VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
 544         VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
 545         VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
 546         VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
 547         VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
 548         CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
 549         VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
 550         VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
 551         MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
 552         HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
 553         VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
 554         VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
 555
 556         EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
 557         VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
 558         EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
 559         VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
 560         INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
 561         MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
 562         VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
 563         I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
 564         CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
 565         CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
 566         VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
 567         INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
 568         VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
 569         WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
 570         VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
 571         IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
 572         VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
 573         MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
 574         VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
 575         SSI_WS78_B_MARK,
 576
 577         DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
 578         VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
 579         DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
 580         SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
 581         INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
 582         DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
 583         MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
 584         SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
 585         ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
 586         TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
 587         I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
 588         STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
 589         IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
 590         STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
 591         SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
 592         HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
 593         TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
 594         RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
 595         STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
 596         ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
 597         STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
 598
 599         ETH_MDIO_MARK, HRTS0_N_E_MARK,
 600         SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
 601         HTX0_F_MARK, BPFCLK_G_MARK,
 602         ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
 603         HRTS0_N_F_MARK, ETH_MAGIC_MARK,
 604         SIM0_RST_C_MARK, ETH_TXD0_MARK,
 605         STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
 606         ETH_MDC_MARK, STP_ISD_1_B_MARK,
 607         TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
 608         SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
 609         GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
 610         STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
 611         PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
 612         PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
 613         AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
 614         ATACS00_N_MARK, AVB_RXD1_MARK,
 615         VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
 616
 617         VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
 618         VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
 619         AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
 620         AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
 621         AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
 622         AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
 623         VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
 624         VI1_CLK_MARK, AVB_RX_DV_MARK,
 625         VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
 626         AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
 627         SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
 628         VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
 629         VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
 630         AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
 631         AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
 632         AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
 633         SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
 634         SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
 635
 636         SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
 637         SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
 638         SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
 639         SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
 640         SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
 641         GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
 642         I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
 643         MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
 644         GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
 645         I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
 646         AVB_TX_EN_MARK, SD1_CMD_MARK,
 647         AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
 648         SD1_DAT0_MARK, AVB_TX_CLK_MARK,
 649         SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
 650         SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
 651         AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
 652         SD1_DAT3_MARK, AVB_RXD0_MARK,
 653         SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
 654         TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
 655         IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
 656         VI3_CLK_B_MARK,
 657
 658         SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
 659         GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
 660         SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
 661         VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
 662         VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
 663         VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
 664         TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
 665         SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
 666         VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
 667         TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
 668         SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
 669         VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
 670         TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
 671         SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
 672         VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
 673         GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
 674         MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
 675         HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
 676         VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
 677         TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
 678         VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
 679         GLO_I0_B_MARK, VI3_DATA6_B_MARK,
 680
 681         SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
 682         GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
 683         TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
 684         SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
 685         MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
 686         SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
 687         MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
 688         SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
 689         VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
 690         MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
 691         FMIN_E_MARK, FMIN_F_MARK,
 692         MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
 693         MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
 694         I2C2_SDA_B_MARK, MLB_DAT_MARK,
 695         SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
 696         SSI_SCK0129_MARK, CAN_CLK_B_MARK,
 697         MOUT0_MARK,
 698
 699         SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
 700         SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
 701         SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
 702         SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
 703         SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
 704         MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
 705         STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
 706         CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
 707         SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
 708         SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
 709         MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
 710         SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
 711         MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
 712         SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
 713         CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
 714         IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
 715         CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
 716         IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
 717         CAN_DEBUGOUT4_MARK,
 718
 719         SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
 720         LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
 721         SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
 722         DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
 723         BPFCLK_F_MARK, SSI_WS6_MARK,
 724         SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
 725         LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
 726         FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
 727         CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
 728         SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
 729         CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
 730         SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
 731         LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
 732         STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
 733         TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
 734         BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
 735         FMIN_G_MARK, SSI_SDATA8_MARK,
 736         STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
 737         CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
 738         STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
 739         SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
 740         SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
 741
 742         AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
 743         DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
 744         REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
 745         MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
 746         I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
 747         DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
 748         TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
 749         HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
 750         LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
 751         SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
 752         MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
 753         SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
 754         DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 755         SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
 756         LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
 757         CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
 758         SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
 759         MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
 760         HRTS0_N_C_MARK,
 761
 762         SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
 763         LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
 764         TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
 765         SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
 766         IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
 767         DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
 768         DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
 769         LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
 770         LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
 771         LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
 772         DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
 773         SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
 774         HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
 775         DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
 776         DU2_DG6_MARK, LCDOUT14_MARK,
 777
 778         MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
 779         DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
 780         MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
 781         ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
 782         USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
 783         TCLK1_B_MARK,
 784
 785         IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
 786         IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
 787         PINMUX_MARK_END,
 788 };
 789
 790 static const u16 pinmux_data[] = {
 791         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 792
 793         PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
 794         PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
 795         PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
 796         PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
 797         PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
 798         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 799         PINMUX_DATA(AVS2_MARK, FN_AVS2),
 800         PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
 801         PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
 802
 803         PINMUX_IPSR_DATA(IP0_2_0, D0),
 804         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
 805         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
 806         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
 807         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
 808         PINMUX_IPSR_DATA(IP0_5_3, D1),
 809         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
 810         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
 811         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
 812         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
 813         PINMUX_IPSR_DATA(IP0_8_6, D2),
 814         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
 815         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
 816         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
 817         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
 818         PINMUX_IPSR_DATA(IP0_11_9, D3),
 819         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
 820         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
 821         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
 822         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
 823         PINMUX_IPSR_DATA(IP0_15_12, D4),
 824         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
 825         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
 826         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
 827         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
 828         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
 829         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
 830         PINMUX_IPSR_DATA(IP0_19_16, D5),
 831         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
 832         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
 833         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
 834         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
 835         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
 836         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
 837         PINMUX_IPSR_DATA(IP0_22_20, D6),
 838         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
 839         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
 840         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
 841         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
 842         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
 843         PINMUX_IPSR_DATA(IP0_26_23, D7),
 844         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
 845         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
 846         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
 847         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
 848         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
 849         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
 850         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0),
 851         PINMUX_IPSR_DATA(IP0_30_27, D8),
 852         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
 853         PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
 854         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
 855         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
 856         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
 857
 858         PINMUX_IPSR_DATA(IP1_3_0, D9),
 859         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
 860         PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
 861         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
 862         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
 863         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
 864         PINMUX_IPSR_DATA(IP1_7_4, D10),
 865         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
 866         PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
 867         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
 868         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
 869         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
 870         PINMUX_IPSR_DATA(IP1_11_8, D11),
 871         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
 872         PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
 873         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
 874         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
 875         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
 876         PINMUX_IPSR_DATA(IP1_14_12, D12),
 877         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
 878         PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
 879         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
 880         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
 881         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
 882         PINMUX_IPSR_DATA(IP1_17_15, D13),
 883         PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
 884         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
 885         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
 886         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
 887         PINMUX_IPSR_DATA(IP1_21_18, D14),
 888         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
 889         PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
 890         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
 891         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
 892         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
 893         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
 894         PINMUX_IPSR_DATA(IP1_25_22, D15),
 895         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
 896         PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
 897         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
 898         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
 899         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
 900         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
 901         PINMUX_IPSR_DATA(IP1_27_26, A0),
 902         PINMUX_IPSR_DATA(IP1_27_26, PWM3),
 903         PINMUX_IPSR_DATA(IP1_29_28, A1),
 904         PINMUX_IPSR_DATA(IP1_29_28, PWM4),
 905
 906         PINMUX_IPSR_DATA(IP2_2_0, A2),
 907         PINMUX_IPSR_DATA(IP2_2_0, PWM5),
 908         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
 909         PINMUX_IPSR_DATA(IP2_5_3, A3),
 910         PINMUX_IPSR_DATA(IP2_5_3, PWM6),
 911         PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
 912         PINMUX_IPSR_DATA(IP2_8_6, A4),
 913         PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
 914         PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
 915         PINMUX_IPSR_DATA(IP2_11_9, A5),
 916         PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
 917         PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
 918         PINMUX_IPSR_DATA(IP2_14_12, A6),
 919         PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
 920         PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
 921         PINMUX_IPSR_DATA(IP2_17_15, A7),
 922         PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
 923         PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
 924         PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
 925         PINMUX_IPSR_DATA(IP2_21_18, A8),
 926         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
 927         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
 928         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
 929         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
 930         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
 931         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1),
 932         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
 933         PINMUX_IPSR_DATA(IP2_25_22, A9),
 934         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
 935         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
 936         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
 937         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
 938         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
 939         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1),
 940         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
 941         PINMUX_IPSR_DATA(IP2_28_26, A10),
 942         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
 943         PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
 944         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
 945         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
 946         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
 947
 948         PINMUX_IPSR_DATA(IP3_3_0, A11),
 949         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
 950         PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
 951         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
 952         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
 953         PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
 954         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
 955         PINMUX_IPSR_DATA(IP3_7_4, A12),
 956         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
 957         PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
 958         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
 959         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
 960         PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
 961         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
 962         PINMUX_IPSR_DATA(IP3_11_8, A13),
 963         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
 964         PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
 965         PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
 966         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
 967         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
 968         PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
 969         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
 970         PINMUX_IPSR_DATA(IP3_14_12, A14),
 971         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
 972         PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
 973         PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
 974         PINMUX_IPSR_DATA(IP3_17_15, A15),
 975         PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
 976         PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
 977         PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
 978         PINMUX_IPSR_DATA(IP3_19_18, A16),
 979         PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
 980         PINMUX_IPSR_DATA(IP3_22_20, A17),
 981         PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
 982         PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
 983         PINMUX_IPSR_DATA(IP3_25_23, A18),
 984         PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
 985         PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
 986         PINMUX_IPSR_DATA(IP3_28_26, A19),
 987         PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
 988         PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
 989         PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
 990         PINMUX_IPSR_DATA(IP3_31_29, A20),
 991         PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
 992         PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
 993         PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
 994         PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
 995
 996         PINMUX_IPSR_DATA(IP4_2_0, A21),
 997         PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
 998         PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
 999         PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1000         PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1001         PINMUX_IPSR_DATA(IP4_5_3, A22),
1002         PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1003         PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
1004         PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1005         PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1006         PINMUX_IPSR_DATA(IP4_8_6, A23),
1007         PINMUX_IPSR_DATA(IP4_8_6, IO2),
1008         PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
1009         PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1010         PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1011         PINMUX_IPSR_DATA(IP4_11_9, A24),
1012         PINMUX_IPSR_DATA(IP4_11_9, IO3),
1013         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
1014         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1015         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1016         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1017         PINMUX_IPSR_DATA(IP4_14_12, A25),
1018         PINMUX_IPSR_DATA(IP4_14_12, SSL),
1019         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
1020         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1021         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1022         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1023         PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1024         PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
1025         PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1026         PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1027         PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1028         PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1029         PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1030         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
1031         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1032         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
1033         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1034         PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1035         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1036         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
1037         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1038         PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1039         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1040         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1041         PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1042         PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1043         PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1044         PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1045         PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1046         PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1047         PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1048         PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1049         PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1050         PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1051         PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
1052         PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1053         PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1054
1055         PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1056         PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1057         PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1058         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1059         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1060         PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
1061         PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
1062         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1063         PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1064         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1065         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1066         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1067         PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
1068         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1069         PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1070         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1071         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1072         PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1073         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1074         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1075         PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
1076         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1077         PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
1078         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1079         PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1080         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1081         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1082         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1083         PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1084         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
1085         PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1086         PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1087         PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1088         PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1089         PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
1090         PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1091         PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1092         PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1093         PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1094         PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1095         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
1096         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1097         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1098         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1099         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1100         PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1101         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
1102         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1103         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
1104         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1105         PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1106         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1107         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
1108         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1109         PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1110         PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1111         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
1112         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1113         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1114         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1115         PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1116         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1117         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1118         PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1119         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1120         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1121
1122         PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1123         PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1124         PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1125         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1126         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1127         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1128         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1129         PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1130         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1131         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1132         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1133         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1134         PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1135         PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1136         PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1137         PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1138         PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1139         PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1140         PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1141         PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1142         PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1143         PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1144         PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1145         PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1146         PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1147         PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1148         PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1149         PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
1150         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1151         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1152         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1153         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1154         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1155         PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
1156         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1157         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1158         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1159         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1160         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1161         PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
1162         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1163         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1164         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1165         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1166         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1167         PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
1168         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1169         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1170         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1171         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1172         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1173         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1174         PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
1175         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1176         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1177         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1178         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1179         PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
1180         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1181         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1182         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1183
1184         PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
1185         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1186         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1187         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1188         PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
1189         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1190         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6),
1191         PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
1192         PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1193         PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1194         PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
1195         PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1196         PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
1197         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1198         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1199         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1200         PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
1201         PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1202         PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1203         PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1204         PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1205         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1206         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1207         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1208         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1209         PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1210         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1211         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1212         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1213         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1214         PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1215         PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1216         PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1217         PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1218         PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1219         PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
1220         PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1),
1221         PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1222         PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1223         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1224         PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1225         PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
1226         PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1227         PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1228         PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
1229
1230         PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1231         PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1232         PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
1233         PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1234         PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1235         PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1236         PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1237         PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1238         PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1239         PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1240         PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1241         PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1242         PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1243         PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1244         PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1245         PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1246         PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
1247         PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1248         PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
1249         PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1250         PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
1251         PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1252         PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1253         PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
1254         PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1255         PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1256         PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
1257         PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1258         PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1259         PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
1260         PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1261         PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1262         PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1263         PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1264         PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1265         PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
1266         PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1267         PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
1268         PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1269         PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1270         PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1271         PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1272         PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1273         PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1274         PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1275
1276         PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1277         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1278         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1279         PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1280         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1281         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1282         PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1283         PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1284         PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1285         PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1286         PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1287         PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1288         PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1289         PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1290         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1291         PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1292         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1293         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1294         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1295         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1296         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1297         PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1298         PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1299         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1300         PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1301         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1302         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1303         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1304         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1305         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1306         PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1307         PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
1308         PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1309         PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
1310         PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1311         PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1312         PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
1313         PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1314         PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1315         PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
1316         PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1317         PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1318         PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
1319         PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1320         PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1321         PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
1322         PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1323         PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1324         PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1325         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1326         PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1327         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1328         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1329         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1330         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1331         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1332         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1333
1334         PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1335         PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1336         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1337         PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1338         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1339         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1340         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1341         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1342         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1343         PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1344         PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1345         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1346         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1347         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1348         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1349         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1350         PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1351         PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1352         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
1353         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1354         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1355         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1356         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1357         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1358         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1359         PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1360         PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1361         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
1362         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1363         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1364         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
1365         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1366         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1367         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1368         PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1369         PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1370         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
1371         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1372         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1373         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
1374         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1375         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1376         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1377         PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1378         PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1379         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
1380         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1381         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1382         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1383         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1384         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1385         PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1386         PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1387         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
1388         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1389         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1390         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1391         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1392         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1393         PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1394         PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1395         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1396         PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1397         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
1398         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1399         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1400         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1401         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1402         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1403
1404         PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1405         PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1406         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1407         PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1408         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
1409         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1410         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1411         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1412         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1413         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1414         PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1415         PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1416         PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
1417         PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
1418         PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
1419         PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
1420         PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
1421         PINMUX_IPSR_DATA(IP11_8_7, STM_N),
1422         PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
1423         PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
1424         PINMUX_IPSR_DATA(IP11_10_9, MDATA),
1425         PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
1426         PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
1427         PINMUX_IPSR_DATA(IP11_12_11, SDATA),
1428         PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
1429         PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
1430         PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1431         PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1432         PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1433         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1434         PINMUX_IPSR_DATA(IP11_17_15, VSP),
1435         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
1436         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1437         PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1438         PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1439         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1440         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1441         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
1442         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
1443         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
1444         PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
1445         PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1446         PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1447         PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1448         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1449         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
1450         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1451         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1452         PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
1453         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1454         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1455         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
1456         PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1457         PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1458         PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1459
1460         PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1461         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1462         PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1463         PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1464         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1465         PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1466         PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1467         PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1468         PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1469         PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1470         PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1471         PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
1472         PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1473         PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1474         PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1475         PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1476         PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1477         PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1478         PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1479         PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1480         PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1481         PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1482         PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1483         PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1484         PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1485         PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1486         PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1487         PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1488         PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1489         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1490         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1491         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1492         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1493         PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1494         PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1495         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1496         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1497         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1498         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1499         PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1500         PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1501         PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1502         PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1503         PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1504         PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1505         PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1506         PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
1507         PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1508         PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1509         PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1510         PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1511         PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1512         PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
1513         PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1514         PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1515         PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1516
1517         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1518         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1519         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
1520         PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1521         PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1522         PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1523         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1524         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1525         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
1526         PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1527         PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1528         PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1529         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
1530         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1531         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1532         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1533         PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1534         PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1535         PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1536         PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1537         PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
1538         PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1539         PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1540         PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1541         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1542         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1543         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
1544         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1545         PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1546         PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1547         PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1548         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1549         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1550         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1551         PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1552         PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1553         PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1554         PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1555         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1556         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1557         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1558         PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1559         PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1560         PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1561         PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1562         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
1563         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1564         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
1565         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1566         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1567         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1568         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1569         PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1570         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1571         PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1572         PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1573         PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1574         PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1575         PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1576         PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1577         PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1578         PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1579         PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1580
1581         PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1582         PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1583         PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1584         PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1585         PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1586         PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1587         PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1588         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1589         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1590         PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1591         PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1592         PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1593         PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
1594         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1595         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1596         PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1597         PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1598         PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
1599         PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1600         PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1601         PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1602         PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
1603         PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
1604         PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1605         PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1606         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1607         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1608         PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
1609         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1610         PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
1611         PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
1612         PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
1613         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1614         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1615         PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1616         PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1617         PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
1618         PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1619         PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1620         PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1621         PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1622         PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1623         PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
1624         PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
1625         PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1626         PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1627         PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1628         PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
1629         PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
1630         PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1631         PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1632         PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1633         PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
1634         PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1635         PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1636         PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1637         PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1638         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1639         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1640         PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
1641         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1642         PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1643         PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1644         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1645
1646         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1647         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1648         PINMUX_IPSR_DATA(IP15_2_0, SCK2),
1649         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1650         PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1651         PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
1652         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1653         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1654         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1655         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0),
1656         PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1657         PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
1658         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1659         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1660         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1661         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1662         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0),
1663         PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1664         PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
1665         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1666         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1667         PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1668         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1669         PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1670         PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
1671         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1672         PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1673         PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1674         PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1675         PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
1676         PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1677         PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1678         PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1679         PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1680         PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1681         PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1682         PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1683         PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1684         PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1685         PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1686         PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1687         PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1688         PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1689         PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1690         PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1691         PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1692         PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1693         PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1694         PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1695         PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1696         PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
1697         PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1698         PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1699         PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1700         PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1701         PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1702         PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1703         PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1704         PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1705         PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1706
1707         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1708         PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1709         PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1710         PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1711         PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1712         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1713         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1714         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1715         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1716         PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1717         PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1718         PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1719         PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
1720         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1721         PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1722         PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1723         PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1724         PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
1725
1726         PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1727         PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1728         PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1729         PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1730
1731         PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1732         PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1733         PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1734         PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1735 };
1736
1737 /* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1738 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1739 #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1740 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1741
1742 static const struct sh_pfc_pin pinmux_pins[] = {
1743         PINMUX_GPIO_GP_ALL(),
1744
1745         /* Pins not associated with a GPIO port */
1746         SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
1747         SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
1748         SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1749         SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1750 };
1751
1752 /* - AUDIO CLOCK ------------------------------------------------------------ */
1753 static const unsigned int audio_clk_a_pins[] = {
1754         /* CLK A */
1755         RCAR_GP_PIN(4, 25),
1756 };
1757 static const unsigned int audio_clk_a_mux[] = {
1758         AUDIO_CLKA_MARK,
1759 };
1760 static const unsigned int audio_clk_b_pins[] = {
1761         /* CLK B */
1762         RCAR_GP_PIN(4, 26),
1763 };
1764 static const unsigned int audio_clk_b_mux[] = {
1765         AUDIO_CLKB_MARK,
1766 };
1767 static const unsigned int audio_clk_c_pins[] = {
1768         /* CLK C */
1769         RCAR_GP_PIN(5, 27),
1770 };
1771 static const unsigned int audio_clk_c_mux[] = {
1772         AUDIO_CLKC_MARK,
1773 };
1774 static const unsigned int audio_clkout_pins[] = {
1775         /* CLK OUT */
1776         RCAR_GP_PIN(5, 16),
1777 };
1778 static const unsigned int audio_clkout_mux[] = {
1779         AUDIO_CLKOUT_MARK,
1780 };
1781 static const unsigned int audio_clkout_b_pins[] = {
1782         /* CLK OUT B */
1783         RCAR_GP_PIN(0, 23),
1784 };
1785 static const unsigned int audio_clkout_b_mux[] = {
1786         AUDIO_CLKOUT_B_MARK,
1787 };
1788 static const unsigned int audio_clkout_c_pins[] = {
1789         /* CLK OUT C */
1790         RCAR_GP_PIN(5, 27),
1791 };
1792 static const unsigned int audio_clkout_c_mux[] = {
1793         AUDIO_CLKOUT_C_MARK,
1794 };
1795 static const unsigned int audio_clkout_d_pins[] = {
1796         /* CLK OUT D */
1797         RCAR_GP_PIN(5, 20),
1798 };
1799 static const unsigned int audio_clkout_d_mux[] = {
1800         AUDIO_CLKOUT_D_MARK,
1801 };
1802 /* - AVB -------------------------------------------------------------------- */
1803 static const unsigned int avb_link_pins[] = {
1804         RCAR_GP_PIN(3, 11),
1805 };
1806 static const unsigned int avb_link_mux[] = {
1807         AVB_LINK_MARK,
1808 };
1809 static const unsigned int avb_magic_pins[] = {
1810         RCAR_GP_PIN(2, 14),
1811 };
1812 static const unsigned int avb_magic_mux[] = {
1813         AVB_MAGIC_MARK,
1814 };
1815 static const unsigned int avb_phy_int_pins[] = {
1816         RCAR_GP_PIN(2, 15),
1817 };
1818 static const unsigned int avb_phy_int_mux[] = {
1819         AVB_PHY_INT_MARK,
1820 };
1821 static const unsigned int avb_mdio_pins[] = {
1822         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1823 };
1824 static const unsigned int avb_mdio_mux[] = {
1825         AVB_MDC_MARK, AVB_MDIO_MARK,
1826 };
1827 static const unsigned int avb_mii_pins[] = {
1828         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1829         RCAR_GP_PIN(0, 11),
1830
1831         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1832         RCAR_GP_PIN(2, 2),
1833
1834         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1835         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
1836         RCAR_GP_PIN(3, 12),
1837 };
1838 static const unsigned int avb_mii_mux[] = {
1839         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1840         AVB_TXD3_MARK,
1841
1842         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1843         AVB_RXD3_MARK,
1844
1845         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1846         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
1847         AVB_COL_MARK,
1848 };
1849 static const unsigned int avb_gmii_pins[] = {
1850         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1851         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1852         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1853
1854         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1855         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1856         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1857
1858         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1859         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1860         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1861         RCAR_GP_PIN(3, 12),
1862 };
1863 static const unsigned int avb_gmii_mux[] = {
1864         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1865         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1866         AVB_TXD6_MARK, AVB_TXD7_MARK,
1867
1868         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1869         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1870         AVB_RXD6_MARK, AVB_RXD7_MARK,
1871
1872         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1873         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1874         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1875         AVB_COL_MARK,
1876 };
1877 /* - DU RGB ----------------------------------------------------------------- */
1878 static const unsigned int du_rgb666_pins[] = {
1879         /* R[7:2], G[7:2], B[7:2] */
1880         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1881         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1882         RCAR_GP_PIN(5, 4),  RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1883         RCAR_GP_PIN(5, 7),  RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1884         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1885         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),  RCAR_GP_PIN(5, 8),
1886 };
1887 static const unsigned int du_rgb666_mux[] = {
1888         DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1889         DU2_DR3_MARK, DU2_DR2_MARK,
1890         DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1891         DU2_DG3_MARK, DU2_DG2_MARK,
1892         DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1893         DU2_DB3_MARK, DU2_DB2_MARK,
1894 };
1895 static const unsigned int du_rgb888_pins[] = {
1896         /* R[7:0], G[7:0], B[7:0] */
1897         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1898         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1899         RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1900         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1901         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1902         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1903         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1904         RCAR_GP_PIN(5, 8),  RCAR_GP_PIN(5, 6),  RCAR_GP_PIN(5, 5),
1905 };
1906 static const unsigned int du_rgb888_mux[] = {
1907         DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1908         DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1909         DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1910         DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1911         DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1912         DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1913 };
1914 static const unsigned int du_clk_out_0_pins[] = {
1915         /* CLKOUT */
1916         RCAR_GP_PIN(5, 2),
1917 };
1918 static const unsigned int du_clk_out_0_mux[] = {
1919         DU0_DOTCLKOUT_MARK
1920 };
1921 static const unsigned int du_clk_out_1_pins[] = {
1922         /* CLKOUT */
1923         RCAR_GP_PIN(5, 3),
1924 };
1925 static const unsigned int du_clk_out_1_mux[] = {
1926         DU1_DOTCLKOUT_MARK
1927 };
1928 static const unsigned int du_sync_0_pins[] = {
1929         /* VSYNC, HSYNC, DISP */
1930         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1931 };
1932 static const unsigned int du_sync_0_mux[] = {
1933         DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1934         DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1935 };
1936 static const unsigned int du_sync_1_pins[] = {
1937         /* VSYNC, HSYNC, DISP */
1938         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1939 };
1940 static const unsigned int du_sync_1_mux[] = {
1941         DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1942         DU2_DISP_MARK
1943 };
1944 static const unsigned int du_cde_pins[] = {
1945         /* CDE */
1946         RCAR_GP_PIN(5, 17),
1947 };
1948 static const unsigned int du_cde_mux[] = {
1949         DU2_CDE_MARK,
1950 };
1951 /* - DU0 -------------------------------------------------------------------- */
1952 static const unsigned int du0_clk_in_pins[] = {
1953         /* CLKIN */
1954         RCAR_GP_PIN(5, 26),
1955 };
1956 static const unsigned int du0_clk_in_mux[] = {
1957         DU_DOTCLKIN0_MARK
1958 };
1959 /* - DU1 -------------------------------------------------------------------- */
1960 static const unsigned int du1_clk_in_pins[] = {
1961         /* CLKIN */
1962         RCAR_GP_PIN(5, 27),
1963 };
1964 static const unsigned int du1_clk_in_mux[] = {
1965         DU_DOTCLKIN1_MARK,
1966 };
1967 /* - DU2 -------------------------------------------------------------------- */
1968 static const unsigned int du2_clk_in_pins[] = {
1969         /* CLKIN */
1970         RCAR_GP_PIN(5, 28),
1971 };
1972 static const unsigned int du2_clk_in_mux[] = {
1973         DU_DOTCLKIN2_MARK,
1974 };
1975 /* - ETH -------------------------------------------------------------------- */
1976 static const unsigned int eth_link_pins[] = {
1977         /* LINK */
1978         RCAR_GP_PIN(2, 22),
1979 };
1980 static const unsigned int eth_link_mux[] = {
1981         ETH_LINK_MARK,
1982 };
1983 static const unsigned int eth_magic_pins[] = {
1984         /* MAGIC */
1985         RCAR_GP_PIN(2, 27),
1986 };
1987 static const unsigned int eth_magic_mux[] = {
1988         ETH_MAGIC_MARK,
1989 };
1990 static const unsigned int eth_mdio_pins[] = {
1991         /* MDC, MDIO */
1992         RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1993 };
1994 static const unsigned int eth_mdio_mux[] = {
1995         ETH_MDC_MARK, ETH_MDIO_MARK,
1996 };
1997 static const unsigned int eth_rmii_pins[] = {
1998         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1999         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
2000         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
2001         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
2002 };
2003 static const unsigned int eth_rmii_mux[] = {
2004         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2005         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
2006 };
2007 /* - HSCIF0 ----------------------------------------------------------------- */
2008 static const unsigned int hscif0_data_pins[] = {
2009         /* RX, TX */
2010         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2011 };
2012 static const unsigned int hscif0_data_mux[] = {
2013         HRX0_MARK, HTX0_MARK,
2014 };
2015 static const unsigned int hscif0_clk_pins[] = {
2016         /* SCK */
2017         RCAR_GP_PIN(5, 7),
2018 };
2019 static const unsigned int hscif0_clk_mux[] = {
2020         HSCK0_MARK,
2021 };
2022 static const unsigned int hscif0_ctrl_pins[] = {
2023         /* RTS, CTS */
2024         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2025 };
2026 static const unsigned int hscif0_ctrl_mux[] = {
2027         HRTS0_N_MARK, HCTS0_N_MARK,
2028 };
2029 static const unsigned int hscif0_data_b_pins[] = {
2030         /* RX, TX */
2031         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2032 };
2033 static const unsigned int hscif0_data_b_mux[] = {
2034         HRX0_B_MARK, HTX0_B_MARK,
2035 };
2036 static const unsigned int hscif0_ctrl_b_pins[] = {
2037         /* RTS, CTS */
2038         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2039 };
2040 static const unsigned int hscif0_ctrl_b_mux[] = {
2041         HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2042 };
2043 static const unsigned int hscif0_data_c_pins[] = {
2044         /* RX, TX */
2045         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2046 };
2047 static const unsigned int hscif0_data_c_mux[] = {
2048         HRX0_C_MARK, HTX0_C_MARK,
2049 };
2050 static const unsigned int hscif0_ctrl_c_pins[] = {
2051         /* RTS, CTS */
2052         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2053 };
2054 static const unsigned int hscif0_ctrl_c_mux[] = {
2055         HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2056 };
2057 static const unsigned int hscif0_data_d_pins[] = {
2058         /* RX, TX */
2059         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2060 };
2061 static const unsigned int hscif0_data_d_mux[] = {
2062         HRX0_D_MARK, HTX0_D_MARK,
2063 };
2064 static const unsigned int hscif0_ctrl_d_pins[] = {
2065         /* RTS, CTS */
2066         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2067 };
2068 static const unsigned int hscif0_ctrl_d_mux[] = {
2069         HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2070 };
2071 static const unsigned int hscif0_data_e_pins[] = {
2072         /* RX, TX */
2073         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2074 };
2075 static const unsigned int hscif0_data_e_mux[] = {
2076         HRX0_E_MARK, HTX0_E_MARK,
2077 };
2078 static const unsigned int hscif0_ctrl_e_pins[] = {
2079         /* RTS, CTS */
2080         RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2081 };
2082 static const unsigned int hscif0_ctrl_e_mux[] = {
2083         HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2084 };
2085 static const unsigned int hscif0_data_f_pins[] = {
2086         /* RX, TX */
2087         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2088 };
2089 static const unsigned int hscif0_data_f_mux[] = {
2090         HRX0_F_MARK, HTX0_F_MARK,
2091 };
2092 static const unsigned int hscif0_ctrl_f_pins[] = {
2093         /* RTS, CTS */
2094         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2095 };
2096 static const unsigned int hscif0_ctrl_f_mux[] = {
2097         HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2098 };
2099 /* - HSCIF1 ----------------------------------------------------------------- */
2100 static const unsigned int hscif1_data_pins[] = {
2101         /* RX, TX */
2102         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2103 };
2104 static const unsigned int hscif1_data_mux[] = {
2105         HRX1_MARK, HTX1_MARK,
2106 };
2107 static const unsigned int hscif1_clk_pins[] = {
2108         /* SCK */
2109         RCAR_GP_PIN(4, 27),
2110 };
2111 static const unsigned int hscif1_clk_mux[] = {
2112         HSCK1_MARK,
2113 };
2114 static const unsigned int hscif1_ctrl_pins[] = {
2115         /* RTS, CTS */
2116         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2117 };
2118 static const unsigned int hscif1_ctrl_mux[] = {
2119         HRTS1_N_MARK, HCTS1_N_MARK,
2120 };
2121 static const unsigned int hscif1_data_b_pins[] = {
2122         /* RX, TX */
2123         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2124 };
2125 static const unsigned int hscif1_data_b_mux[] = {
2126         HRX1_B_MARK, HTX1_B_MARK,
2127 };
2128 static const unsigned int hscif1_clk_b_pins[] = {
2129         /* SCK */
2130         RCAR_GP_PIN(1, 28),
2131 };
2132 static const unsigned int hscif1_clk_b_mux[] = {
2133         HSCK1_B_MARK,
2134 };
2135 static const unsigned int hscif1_ctrl_b_pins[] = {
2136         /* RTS, CTS */
2137         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2138 };
2139 static const unsigned int hscif1_ctrl_b_mux[] = {
2140         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2141 };
2142 /* - I2C0 ------------------------------------------------------------------- */
2143 static const unsigned int i2c0_pins[] = {
2144         /* SCL, SDA */
2145         PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2146 };
2147 static const unsigned int i2c0_mux[] = {
2148         I2C0_SCL_MARK, I2C0_SDA_MARK,
2149 };
2150 /* - I2C1 ------------------------------------------------------------------- */
2151 static const unsigned int i2c1_pins[] = {
2152         /* SCL, SDA */
2153         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2154 };
2155 static const unsigned int i2c1_mux[] = {
2156         I2C1_SCL_MARK, I2C1_SDA_MARK,
2157 };
2158 static const unsigned int i2c1_b_pins[] = {
2159         /* SCL, SDA */
2160         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2161 };
2162 static const unsigned int i2c1_b_mux[] = {
2163         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2164 };
2165 static const unsigned int i2c1_c_pins[] = {
2166         /* SCL, SDA */
2167         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2168 };
2169 static const unsigned int i2c1_c_mux[] = {
2170         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2171 };
2172 /* - I2C2 ------------------------------------------------------------------- */
2173 static const unsigned int i2c2_pins[] = {
2174         /* SCL, SDA */
2175         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2176 };
2177 static const unsigned int i2c2_mux[] = {
2178         I2C2_SCL_MARK, I2C2_SDA_MARK,
2179 };
2180 static const unsigned int i2c2_b_pins[] = {
2181         /* SCL, SDA */
2182         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2183 };
2184 static const unsigned int i2c2_b_mux[] = {
2185         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2186 };
2187 static const unsigned int i2c2_c_pins[] = {
2188         /* SCL, SDA */
2189         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2190 };
2191 static const unsigned int i2c2_c_mux[] = {
2192         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2193 };
2194 static const unsigned int i2c2_d_pins[] = {
2195         /* SCL, SDA */
2196         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2197 };
2198 static const unsigned int i2c2_d_mux[] = {
2199         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2200 };
2201 static const unsigned int i2c2_e_pins[] = {
2202         /* SCL, SDA */
2203         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2204 };
2205 static const unsigned int i2c2_e_mux[] = {
2206         I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2207 };
2208 /* - I2C3 ------------------------------------------------------------------- */
2209 static const unsigned int i2c3_pins[] = {
2210         /* SCL, SDA */
2211         PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2212 };
2213 static const unsigned int i2c3_mux[] = {
2214         I2C3_SCL_MARK, I2C3_SDA_MARK,
2215 };
2216 /* - IIC0 (I2C4) ------------------------------------------------------------ */
2217 static const unsigned int iic0_pins[] = {
2218         /* SCL, SDA */
2219         PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2220 };
2221 static const unsigned int iic0_mux[] = {
2222         IIC0_SCL_MARK, IIC0_SDA_MARK,
2223 };
2224 /* - IIC1 (I2C5) ------------------------------------------------------------ */
2225 static const unsigned int iic1_pins[] = {
2226         /* SCL, SDA */
2227         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2228 };
2229 static const unsigned int iic1_mux[] = {
2230         IIC1_SCL_MARK, IIC1_SDA_MARK,
2231 };
2232 static const unsigned int iic1_b_pins[] = {
2233         /* SCL, SDA */
2234         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2235 };
2236 static const unsigned int iic1_b_mux[] = {
2237         IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2238 };
2239 static const unsigned int iic1_c_pins[] = {
2240         /* SCL, SDA */
2241         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2242 };
2243 static const unsigned int iic1_c_mux[] = {
2244         IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2245 };
2246 /* - IIC2 (I2C6) ------------------------------------------------------------ */
2247 static const unsigned int iic2_pins[] = {
2248         /* SCL, SDA */
2249         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2250 };
2251 static const unsigned int iic2_mux[] = {
2252         IIC2_SCL_MARK, IIC2_SDA_MARK,
2253 };
2254 static const unsigned int iic2_b_pins[] = {
2255         /* SCL, SDA */
2256         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2257 };
2258 static const unsigned int iic2_b_mux[] = {
2259         IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2260 };
2261 static const unsigned int iic2_c_pins[] = {
2262         /* SCL, SDA */
2263         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2264 };
2265 static const unsigned int iic2_c_mux[] = {
2266         IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2267 };
2268 static const unsigned int iic2_d_pins[] = {
2269         /* SCL, SDA */
2270         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2271 };
2272 static const unsigned int iic2_d_mux[] = {
2273         IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2274 };
2275 static const unsigned int iic2_e_pins[] = {
2276         /* SCL, SDA */
2277         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2278 };
2279 static const unsigned int iic2_e_mux[] = {
2280         IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2281 };
2282 /* - IIC3 (I2C7) ------------------------------------------------------------ */
2283 static const unsigned int iic3_pins[] = {
2284 /* SCL, SDA */
2285         PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2286 };
2287 static const unsigned int iic3_mux[] = {
2288         IIC3_SCL_MARK, IIC3_SDA_MARK,
2289 };
2290 /* - INTC ------------------------------------------------------------------- */
2291 static const unsigned int intc_irq0_pins[] = {
2292         /* IRQ */
2293         RCAR_GP_PIN(1, 25),
2294 };
2295 static const unsigned int intc_irq0_mux[] = {
2296         IRQ0_MARK,
2297 };
2298 static const unsigned int intc_irq1_pins[] = {
2299         /* IRQ */
2300         RCAR_GP_PIN(1, 27),
2301 };
2302 static const unsigned int intc_irq1_mux[] = {
2303         IRQ1_MARK,
2304 };
2305 static const unsigned int intc_irq2_pins[] = {
2306         /* IRQ */
2307         RCAR_GP_PIN(1, 29),
2308 };
2309 static const unsigned int intc_irq2_mux[] = {
2310         IRQ2_MARK,
2311 };
2312 static const unsigned int intc_irq3_pins[] = {
2313         /* IRQ */
2314         RCAR_GP_PIN(1, 23),
2315 };
2316 static const unsigned int intc_irq3_mux[] = {
2317         IRQ3_MARK,
2318 };
2319 /* - MLB+ ------------------------------------------------------------------- */
2320 static const unsigned int mlb_3pin_pins[] = {
2321         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2322 };
2323 static const unsigned int mlb_3pin_mux[] = {
2324         MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2325 };
2326 /* - MMCIF0 ----------------------------------------------------------------- */
2327 static const unsigned int mmc0_data1_pins[] = {
2328         /* D[0] */
2329         RCAR_GP_PIN(3, 18),
2330 };
2331 static const unsigned int mmc0_data1_mux[] = {
2332         MMC0_D0_MARK,
2333 };
2334 static const unsigned int mmc0_data4_pins[] = {
2335         /* D[0:3] */
2336         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2337         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2338 };
2339 static const unsigned int mmc0_data4_mux[] = {
2340         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2341 };
2342 static const unsigned int mmc0_data8_pins[] = {
2343         /* D[0:7] */
2344         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2345         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2346         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2347         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2348 };
2349 static const unsigned int mmc0_data8_mux[] = {
2350         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2351         MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2352 };
2353 static const unsigned int mmc0_ctrl_pins[] = {
2354         /* CLK, CMD */
2355         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2356 };
2357 static const unsigned int mmc0_ctrl_mux[] = {
2358         MMC0_CLK_MARK, MMC0_CMD_MARK,
2359 };
2360 /* - MMCIF1 ----------------------------------------------------------------- */
2361 static const unsigned int mmc1_data1_pins[] = {
2362         /* D[0] */
2363         RCAR_GP_PIN(3, 26),
2364 };
2365 static const unsigned int mmc1_data1_mux[] = {
2366         MMC1_D0_MARK,
2367 };
2368 static const unsigned int mmc1_data4_pins[] = {
2369         /* D[0:3] */
2370         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2371         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2372 };
2373 static const unsigned int mmc1_data4_mux[] = {
2374         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2375 };
2376 static const unsigned int mmc1_data8_pins[] = {
2377         /* D[0:7] */
2378         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2379         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2380         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2381         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2382 };
2383 static const unsigned int mmc1_data8_mux[] = {
2384         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2385         MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2386 };
2387 static const unsigned int mmc1_ctrl_pins[] = {
2388         /* CLK, CMD */
2389         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2390 };
2391 static const unsigned int mmc1_ctrl_mux[] = {
2392         MMC1_CLK_MARK, MMC1_CMD_MARK,
2393 };
2394 /* - MSIOF0 ----------------------------------------------------------------- */
2395 static const unsigned int msiof0_clk_pins[] = {
2396         /* SCK */
2397         RCAR_GP_PIN(5, 12),
2398 };
2399 static const unsigned int msiof0_clk_mux[] = {
2400         MSIOF0_SCK_MARK,
2401 };
2402 static const unsigned int msiof0_sync_pins[] = {
2403         /* SYNC */
2404         RCAR_GP_PIN(5, 13),
2405 };
2406 static const unsigned int msiof0_sync_mux[] = {
2407         MSIOF0_SYNC_MARK,
2408 };
2409 static const unsigned int msiof0_ss1_pins[] = {
2410         /* SS1 */
2411         RCAR_GP_PIN(5, 14),
2412 };
2413 static const unsigned int msiof0_ss1_mux[] = {
2414         MSIOF0_SS1_MARK,
2415 };
2416 static const unsigned int msiof0_ss2_pins[] = {
2417         /* SS2 */
2418         RCAR_GP_PIN(5, 16),
2419 };
2420 static const unsigned int msiof0_ss2_mux[] = {
2421         MSIOF0_SS2_MARK,
2422 };
2423 static const unsigned int msiof0_rx_pins[] = {
2424         /* RXD */
2425         RCAR_GP_PIN(5, 17),
2426 };
2427 static const unsigned int msiof0_rx_mux[] = {
2428         MSIOF0_RXD_MARK,
2429 };
2430 static const unsigned int msiof0_tx_pins[] = {
2431         /* TXD */
2432         RCAR_GP_PIN(5, 15),
2433 };
2434 static const unsigned int msiof0_tx_mux[] = {
2435         MSIOF0_TXD_MARK,
2436 };
2437
2438 static const unsigned int msiof0_clk_b_pins[] = {
2439         /* SCK */
2440         RCAR_GP_PIN(1, 23),
2441 };
2442 static const unsigned int msiof0_clk_b_mux[] = {
2443         MSIOF0_SCK_B_MARK,
2444 };
2445 static const unsigned int msiof0_ss1_b_pins[] = {
2446         /* SS1 */
2447         RCAR_GP_PIN(1, 12),
2448 };
2449 static const unsigned int msiof0_ss1_b_mux[] = {
2450         MSIOF0_SS1_B_MARK,
2451 };
2452 static const unsigned int msiof0_ss2_b_pins[] = {
2453         /* SS2 */
2454         RCAR_GP_PIN(1, 10),
2455 };
2456 static const unsigned int msiof0_ss2_b_mux[] = {
2457         MSIOF0_SS2_B_MARK,
2458 };
2459 static const unsigned int msiof0_rx_b_pins[] = {
2460         /* RXD */
2461         RCAR_GP_PIN(1, 29),
2462 };
2463 static const unsigned int msiof0_rx_b_mux[] = {
2464         MSIOF0_RXD_B_MARK,
2465 };
2466 static const unsigned int msiof0_tx_b_pins[] = {
2467         /* TXD */
2468         RCAR_GP_PIN(1, 28),
2469 };
2470 static const unsigned int msiof0_tx_b_mux[] = {
2471         MSIOF0_TXD_B_MARK,
2472 };
2473 /* - MSIOF1 ----------------------------------------------------------------- */
2474 static const unsigned int msiof1_clk_pins[] = {
2475         /* SCK */
2476         RCAR_GP_PIN(4, 8),
2477 };
2478 static const unsigned int msiof1_clk_mux[] = {
2479         MSIOF1_SCK_MARK,
2480 };
2481 static const unsigned int msiof1_sync_pins[] = {
2482         /* SYNC */
2483         RCAR_GP_PIN(4, 9),
2484 };
2485 static const unsigned int msiof1_sync_mux[] = {
2486         MSIOF1_SYNC_MARK,
2487 };
2488 static const unsigned int msiof1_ss1_pins[] = {
2489         /* SS1 */
2490         RCAR_GP_PIN(4, 10),
2491 };
2492 static const unsigned int msiof1_ss1_mux[] = {
2493         MSIOF1_SS1_MARK,
2494 };
2495 static const unsigned int msiof1_ss2_pins[] = {
2496         /* SS2 */
2497         RCAR_GP_PIN(4, 11),
2498 };
2499 static const unsigned int msiof1_ss2_mux[] = {
2500         MSIOF1_SS2_MARK,
2501 };
2502 static const unsigned int msiof1_rx_pins[] = {
2503         /* RXD */
2504         RCAR_GP_PIN(4, 13),
2505 };
2506 static const unsigned int msiof1_rx_mux[] = {
2507         MSIOF1_RXD_MARK,
2508 };
2509 static const unsigned int msiof1_tx_pins[] = {
2510         /* TXD */
2511         RCAR_GP_PIN(4, 12),
2512 };
2513 static const unsigned int msiof1_tx_mux[] = {
2514         MSIOF1_TXD_MARK,
2515 };
2516
2517 static const unsigned int msiof1_clk_b_pins[] = {
2518         /* SCK */
2519         RCAR_GP_PIN(1, 16),
2520 };
2521 static const unsigned int msiof1_clk_b_mux[] = {
2522         MSIOF1_SCK_B_MARK,
2523 };
2524 static const unsigned int msiof1_ss1_b_pins[] = {
2525         /* SS1 */
2526         RCAR_GP_PIN(0, 18),
2527 };
2528 static const unsigned int msiof1_ss1_b_mux[] = {
2529         MSIOF1_SS1_B_MARK,
2530 };
2531 static const unsigned int msiof1_ss2_b_pins[] = {
2532         /* SS2 */
2533         RCAR_GP_PIN(0, 19),
2534 };
2535 static const unsigned int msiof1_ss2_b_mux[] = {
2536         MSIOF1_SS2_B_MARK,
2537 };
2538 static const unsigned int msiof1_rx_b_pins[] = {
2539         /* RXD */
2540         RCAR_GP_PIN(1, 17),
2541 };
2542 static const unsigned int msiof1_rx_b_mux[] = {
2543         MSIOF1_RXD_B_MARK,
2544 };
2545 static const unsigned int msiof1_tx_b_pins[] = {
2546         /* TXD */
2547         RCAR_GP_PIN(0, 20),
2548 };
2549 static const unsigned int msiof1_tx_b_mux[] = {
2550         MSIOF1_TXD_B_MARK,
2551 };
2552 /* - MSIOF2 ----------------------------------------------------------------- */
2553 static const unsigned int msiof2_clk_pins[] = {
2554         /* SCK */
2555         RCAR_GP_PIN(0, 27),
2556 };
2557 static const unsigned int msiof2_clk_mux[] = {
2558         MSIOF2_SCK_MARK,
2559 };
2560 static const unsigned int msiof2_sync_pins[] = {
2561         /* SYNC */
2562         RCAR_GP_PIN(0, 26),
2563 };
2564 static const unsigned int msiof2_sync_mux[] = {
2565         MSIOF2_SYNC_MARK,
2566 };
2567 static const unsigned int msiof2_ss1_pins[] = {
2568         /* SS1 */
2569         RCAR_GP_PIN(0, 30),
2570 };
2571 static const unsigned int msiof2_ss1_mux[] = {
2572         MSIOF2_SS1_MARK,
2573 };
2574 static const unsigned int msiof2_ss2_pins[] = {
2575         /* SS2 */
2576         RCAR_GP_PIN(0, 31),
2577 };
2578 static const unsigned int msiof2_ss2_mux[] = {
2579         MSIOF2_SS2_MARK,
2580 };
2581 static const unsigned int msiof2_rx_pins[] = {
2582         /* RXD */
2583         RCAR_GP_PIN(0, 29),
2584 };
2585 static const unsigned int msiof2_rx_mux[] = {
2586         MSIOF2_RXD_MARK,
2587 };
2588 static const unsigned int msiof2_tx_pins[] = {
2589         /* TXD */
2590         RCAR_GP_PIN(0, 28),
2591 };
2592 static const unsigned int msiof2_tx_mux[] = {
2593         MSIOF2_TXD_MARK,
2594 };
2595 /* - MSIOF3 ----------------------------------------------------------------- */
2596 static const unsigned int msiof3_clk_pins[] = {
2597         /* SCK */
2598         RCAR_GP_PIN(5, 4),
2599 };
2600 static const unsigned int msiof3_clk_mux[] = {
2601         MSIOF3_SCK_MARK,
2602 };
2603 static const unsigned int msiof3_sync_pins[] = {
2604         /* SYNC */
2605         RCAR_GP_PIN(4, 30),
2606 };
2607 static const unsigned int msiof3_sync_mux[] = {
2608         MSIOF3_SYNC_MARK,
2609 };
2610 static const unsigned int msiof3_ss1_pins[] = {
2611         /* SS1 */
2612         RCAR_GP_PIN(4, 31),
2613 };
2614 static const unsigned int msiof3_ss1_mux[] = {
2615         MSIOF3_SS1_MARK,
2616 };
2617 static const unsigned int msiof3_ss2_pins[] = {
2618         /* SS2 */
2619         RCAR_GP_PIN(4, 27),
2620 };
2621 static const unsigned int msiof3_ss2_mux[] = {
2622         MSIOF3_SS2_MARK,
2623 };
2624 static const unsigned int msiof3_rx_pins[] = {
2625         /* RXD */
2626         RCAR_GP_PIN(5, 2),
2627 };
2628 static const unsigned int msiof3_rx_mux[] = {
2629         MSIOF3_RXD_MARK,
2630 };
2631 static const unsigned int msiof3_tx_pins[] = {
2632         /* TXD */
2633         RCAR_GP_PIN(5, 3),
2634 };
2635 static const unsigned int msiof3_tx_mux[] = {
2636         MSIOF3_TXD_MARK,
2637 };
2638
2639 static const unsigned int msiof3_clk_b_pins[] = {
2640         /* SCK */
2641         RCAR_GP_PIN(0, 0),
2642 };
2643 static const unsigned int msiof3_clk_b_mux[] = {
2644         MSIOF3_SCK_B_MARK,
2645 };
2646 static const unsigned int msiof3_sync_b_pins[] = {
2647         /* SYNC */
2648         RCAR_GP_PIN(0, 1),
2649 };
2650 static const unsigned int msiof3_sync_b_mux[] = {
2651         MSIOF3_SYNC_B_MARK,
2652 };
2653 static const unsigned int msiof3_rx_b_pins[] = {
2654         /* RXD */
2655         RCAR_GP_PIN(0, 2),
2656 };
2657 static const unsigned int msiof3_rx_b_mux[] = {
2658         MSIOF3_RXD_B_MARK,
2659 };
2660 static const unsigned int msiof3_tx_b_pins[] = {
2661         /* TXD */
2662         RCAR_GP_PIN(0, 3),
2663 };
2664 static const unsigned int msiof3_tx_b_mux[] = {
2665         MSIOF3_TXD_B_MARK,
2666 };
2667 /* - PWM -------------------------------------------------------------------- */
2668 static const unsigned int pwm0_pins[] = {
2669         RCAR_GP_PIN(5, 29),
2670 };
2671 static const unsigned int pwm0_mux[] = {
2672         PWM0_MARK,
2673 };
2674 static const unsigned int pwm0_b_pins[] = {
2675         RCAR_GP_PIN(4, 30),
2676 };
2677 static const unsigned int pwm0_b_mux[] = {
2678         PWM0_B_MARK,
2679 };
2680 static const unsigned int pwm1_pins[] = {
2681         RCAR_GP_PIN(5, 30),
2682 };
2683 static const unsigned int pwm1_mux[] = {
2684         PWM1_MARK,
2685 };
2686 static const unsigned int pwm1_b_pins[] = {
2687         RCAR_GP_PIN(4, 31),
2688 };
2689 static const unsigned int pwm1_b_mux[] = {
2690         PWM1_B_MARK,
2691 };
2692 static const unsigned int pwm2_pins[] = {
2693         RCAR_GP_PIN(5, 31),
2694 };
2695 static const unsigned int pwm2_mux[] = {
2696         PWM2_MARK,
2697 };
2698 static const unsigned int pwm3_pins[] = {
2699         RCAR_GP_PIN(0, 16),
2700 };
2701 static const unsigned int pwm3_mux[] = {
2702         PWM3_MARK,
2703 };
2704 static const unsigned int pwm4_pins[] = {
2705         RCAR_GP_PIN(0, 17),
2706 };
2707 static const unsigned int pwm4_mux[] = {
2708         PWM4_MARK,
2709 };
2710 static const unsigned int pwm5_pins[] = {
2711         RCAR_GP_PIN(0, 18),
2712 };
2713 static const unsigned int pwm5_mux[] = {
2714         PWM5_MARK,
2715 };
2716 static const unsigned int pwm6_pins[] = {
2717         RCAR_GP_PIN(0, 19),
2718 };
2719 static const unsigned int pwm6_mux[] = {
2720         PWM6_MARK,
2721 };
2722 /* - QSPI ------------------------------------------------------------------- */
2723 static const unsigned int qspi_ctrl_pins[] = {
2724         /* SPCLK, SSL */
2725         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2726 };
2727 static const unsigned int qspi_ctrl_mux[] = {
2728         SPCLK_MARK, SSL_MARK,
2729 };
2730 static const unsigned int qspi_data2_pins[] = {
2731         /* MOSI_IO0, MISO_IO1 */
2732         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2733 };
2734 static const unsigned int qspi_data2_mux[] = {
2735         MOSI_IO0_MARK, MISO_IO1_MARK,
2736 };
2737 static const unsigned int qspi_data4_pins[] = {
2738         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2739         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2740         RCAR_GP_PIN(1, 8),
2741 };
2742 static const unsigned int qspi_data4_mux[] = {
2743         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2744 };
2745 /* - SCIF0 ------------------------------------------------------------------ */
2746 static const unsigned int scif0_data_pins[] = {
2747         /* RX, TX */
2748         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2749 };
2750 static const unsigned int scif0_data_mux[] = {
2751         RX0_MARK, TX0_MARK,
2752 };
2753 static const unsigned int scif0_clk_pins[] = {
2754         /* SCK */
2755         RCAR_GP_PIN(4, 27),
2756 };
2757 static const unsigned int scif0_clk_mux[] = {
2758         SCK0_MARK,
2759 };
2760 static const unsigned int scif0_ctrl_pins[] = {
2761         /* RTS, CTS */
2762         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2763 };
2764 static const unsigned int scif0_ctrl_mux[] = {
2765         RTS0_N_MARK, CTS0_N_MARK,
2766 };
2767 static const unsigned int scif0_data_b_pins[] = {
2768         /* RX, TX */
2769         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2770 };
2771 static const unsigned int scif0_data_b_mux[] = {
2772         RX0_B_MARK, TX0_B_MARK,
2773 };
2774 /* - SCIF1 ------------------------------------------------------------------ */
2775 static const unsigned int scif1_data_pins[] = {
2776         /* RX, TX */
2777         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2778 };
2779 static const unsigned int scif1_data_mux[] = {
2780         RX1_MARK, TX1_MARK,
2781 };
2782 static const unsigned int scif1_clk_pins[] = {
2783         /* SCK */
2784         RCAR_GP_PIN(4, 20),
2785 };
2786 static const unsigned int scif1_clk_mux[] = {
2787         SCK1_MARK,
2788 };
2789 static const unsigned int scif1_ctrl_pins[] = {
2790         /* RTS, CTS */
2791         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2792 };
2793 static const unsigned int scif1_ctrl_mux[] = {
2794         RTS1_N_MARK, CTS1_N_MARK,
2795 };
2796 static const unsigned int scif1_data_b_pins[] = {
2797         /* RX, TX */
2798         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2799 };
2800 static const unsigned int scif1_data_b_mux[] = {
2801         RX1_B_MARK, TX1_B_MARK,
2802 };
2803 static const unsigned int scif1_data_c_pins[] = {
2804         /* RX, TX */
2805         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2806 };
2807 static const unsigned int scif1_data_c_mux[] = {
2808         RX1_C_MARK, TX1_C_MARK,
2809 };
2810 static const unsigned int scif1_data_d_pins[] = {
2811         /* RX, TX */
2812         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2813 };
2814 static const unsigned int scif1_data_d_mux[] = {
2815         RX1_D_MARK, TX1_D_MARK,
2816 };
2817 static const unsigned int scif1_clk_d_pins[] = {
2818         /* SCK */
2819         RCAR_GP_PIN(3, 17),
2820 };
2821 static const unsigned int scif1_clk_d_mux[] = {
2822         SCK1_D_MARK,
2823 };
2824 static const unsigned int scif1_data_e_pins[] = {
2825         /* RX, TX */
2826         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2827 };
2828 static const unsigned int scif1_data_e_mux[] = {
2829         RX1_E_MARK, TX1_E_MARK,
2830 };
2831 static const unsigned int scif1_clk_e_pins[] = {
2832         /* SCK */
2833         RCAR_GP_PIN(2, 20),
2834 };
2835 static const unsigned int scif1_clk_e_mux[] = {
2836         SCK1_E_MARK,
2837 };
2838 /* - SCIF2 ------------------------------------------------------------------ */
2839 static const unsigned int scif2_data_pins[] = {
2840         /* RX, TX */
2841         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2842 };
2843 static const unsigned int scif2_data_mux[] = {
2844         RX2_MARK, TX2_MARK,
2845 };
2846 static const unsigned int scif2_clk_pins[] = {
2847         /* SCK */
2848         RCAR_GP_PIN(5, 4),
2849 };
2850 static const unsigned int scif2_clk_mux[] = {
2851         SCK2_MARK,
2852 };
2853 static const unsigned int scif2_data_b_pins[] = {
2854         /* RX, TX */
2855         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2856 };
2857 static const unsigned int scif2_data_b_mux[] = {
2858         RX2_B_MARK, TX2_B_MARK,
2859 };
2860 /* - SCIFA0 ----------------------------------------------------------------- */
2861 static const unsigned int scifa0_data_pins[] = {
2862         /* RXD, TXD */
2863         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2864 };
2865 static const unsigned int scifa0_data_mux[] = {
2866         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2867 };
2868 static const unsigned int scifa0_clk_pins[] = {
2869         /* SCK */
2870         RCAR_GP_PIN(4, 27),
2871 };
2872 static const unsigned int scifa0_clk_mux[] = {
2873         SCIFA0_SCK_MARK,
2874 };
2875 static const unsigned int scifa0_ctrl_pins[] = {
2876         /* RTS, CTS */
2877         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2878 };
2879 static const unsigned int scifa0_ctrl_mux[] = {
2880         SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2881 };
2882 static const unsigned int scifa0_data_b_pins[] = {
2883         /* RXD, TXD */
2884         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2885 };
2886 static const unsigned int scifa0_data_b_mux[] = {
2887         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2888 };
2889 static const unsigned int scifa0_clk_b_pins[] = {
2890         /* SCK */
2891         RCAR_GP_PIN(1, 19),
2892 };
2893 static const unsigned int scifa0_clk_b_mux[] = {
2894         SCIFA0_SCK_B_MARK,
2895 };
2896 static const unsigned int scifa0_ctrl_b_pins[] = {
2897         /* RTS, CTS */
2898         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2899 };
2900 static const unsigned int scifa0_ctrl_b_mux[] = {
2901         SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2902 };
2903 /* - SCIFA1 ----------------------------------------------------------------- */
2904 static const unsigned int scifa1_data_pins[] = {
2905         /* RXD, TXD */
2906         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2907 };
2908 static const unsigned int scifa1_data_mux[] = {
2909         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2910 };
2911 static const unsigned int scifa1_clk_pins[] = {
2912         /* SCK */
2913         RCAR_GP_PIN(4, 20),
2914 };
2915 static const unsigned int scifa1_clk_mux[] = {
2916         SCIFA1_SCK_MARK,
2917 };
2918 static const unsigned int scifa1_ctrl_pins[] = {
2919         /* RTS, CTS */
2920         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2921 };
2922 static const unsigned int scifa1_ctrl_mux[] = {
2923         SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2924 };
2925 static const unsigned int scifa1_data_b_pins[] = {
2926         /* RXD, TXD */
2927         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2928 };
2929 static const unsigned int scifa1_data_b_mux[] = {
2930         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2931 };
2932 static const unsigned int scifa1_clk_b_pins[] = {
2933         /* SCK */
2934         RCAR_GP_PIN(0, 23),
2935 };
2936 static const unsigned int scifa1_clk_b_mux[] = {
2937         SCIFA1_SCK_B_MARK,
2938 };
2939 static const unsigned int scifa1_ctrl_b_pins[] = {
2940         /* RTS, CTS */
2941         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2942 };
2943 static const unsigned int scifa1_ctrl_b_mux[] = {
2944         SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2945 };
2946 static const unsigned int scifa1_data_c_pins[] = {
2947         /* RXD, TXD */
2948         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2949 };
2950 static const unsigned int scifa1_data_c_mux[] = {
2951         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2952 };
2953 static const unsigned int scifa1_clk_c_pins[] = {
2954         /* SCK */
2955         RCAR_GP_PIN(0, 8),
2956 };
2957 static const unsigned int scifa1_clk_c_mux[] = {
2958         SCIFA1_SCK_C_MARK,
2959 };
2960 static const unsigned int scifa1_ctrl_c_pins[] = {
2961         /* RTS, CTS */
2962         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2963 };
2964 static const unsigned int scifa1_ctrl_c_mux[] = {
2965         SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2966 };
2967 static const unsigned int scifa1_data_d_pins[] = {
2968         /* RXD, TXD */
2969         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2970 };
2971 static const unsigned int scifa1_data_d_mux[] = {
2972         SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2973 };
2974 static const unsigned int scifa1_clk_d_pins[] = {
2975         /* SCK */
2976         RCAR_GP_PIN(2, 10),
2977 };
2978 static const unsigned int scifa1_clk_d_mux[] = {
2979         SCIFA1_SCK_D_MARK,
2980 };
2981 static const unsigned int scifa1_ctrl_d_pins[] = {
2982         /* RTS, CTS */
2983         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2984 };
2985 static const unsigned int scifa1_ctrl_d_mux[] = {
2986         SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2987 };
2988 /* - SCIFA2 ----------------------------------------------------------------- */
2989 static const unsigned int scifa2_data_pins[] = {
2990         /* RXD, TXD */
2991         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2992 };
2993 static const unsigned int scifa2_data_mux[] = {
2994         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2995 };
2996 static const unsigned int scifa2_clk_pins[] = {
2997         /* SCK */
2998         RCAR_GP_PIN(5, 4),
2999 };
3000 static const unsigned int scifa2_clk_mux[] = {
3001         SCIFA2_SCK_MARK,
3002 };
3003 static const unsigned int scifa2_ctrl_pins[] = {
3004         /* RTS, CTS */
3005         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3006 };
3007 static const unsigned int scifa2_ctrl_mux[] = {
3008         SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
3009 };
3010 static const unsigned int scifa2_data_b_pins[] = {
3011         /* RXD, TXD */
3012         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3013 };
3014 static const unsigned int scifa2_data_b_mux[] = {
3015         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3016 };
3017 static const unsigned int scifa2_data_c_pins[] = {
3018         /* RXD, TXD */
3019         RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3020 };
3021 static const unsigned int scifa2_data_c_mux[] = {
3022         SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
3023 };
3024 static const unsigned int scifa2_clk_c_pins[] = {
3025         /* SCK */
3026         RCAR_GP_PIN(5, 29),
3027 };
3028 static const unsigned int scifa2_clk_c_mux[] = {
3029         SCIFA2_SCK_C_MARK,
3030 };
3031 /* - SCIFB0 ----------------------------------------------------------------- */
3032 static const unsigned int scifb0_data_pins[] = {
3033         /* RXD, TXD */
3034         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3035 };
3036 static const unsigned int scifb0_data_mux[] = {
3037         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3038 };
3039 static const unsigned int scifb0_clk_pins[] = {
3040         /* SCK */
3041         RCAR_GP_PIN(4, 8),
3042 };
3043 static const unsigned int scifb0_clk_mux[] = {
3044         SCIFB0_SCK_MARK,
3045 };
3046 static const unsigned int scifb0_ctrl_pins[] = {
3047         /* RTS, CTS */
3048         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3049 };
3050 static const unsigned int scifb0_ctrl_mux[] = {
3051         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3052 };
3053 static const unsigned int scifb0_data_b_pins[] = {
3054         /* RXD, TXD */
3055         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3056 };
3057 static const unsigned int scifb0_data_b_mux[] = {
3058         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3059 };
3060 static const unsigned int scifb0_clk_b_pins[] = {
3061         /* SCK */
3062         RCAR_GP_PIN(3, 9),
3063 };
3064 static const unsigned int scifb0_clk_b_mux[] = {
3065         SCIFB0_SCK_B_MARK,
3066 };
3067 static const unsigned int scifb0_ctrl_b_pins[] = {
3068         /* RTS, CTS */
3069         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3070 };
3071 static const unsigned int scifb0_ctrl_b_mux[] = {
3072         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3073 };
3074 static const unsigned int scifb0_data_c_pins[] = {
3075         /* RXD, TXD */
3076         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3077 };
3078 static const unsigned int scifb0_data_c_mux[] = {
3079         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3080 };
3081 /* - SCIFB1 ----------------------------------------------------------------- */
3082 static const unsigned int scifb1_data_pins[] = {
3083         /* RXD, TXD */
3084         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3085 };
3086 static const unsigned int scifb1_data_mux[] = {
3087         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3088 };
3089 static const unsigned int scifb1_clk_pins[] = {
3090         /* SCK */
3091         RCAR_GP_PIN(4, 14),
3092 };
3093 static const unsigned int scifb1_clk_mux[] = {
3094         SCIFB1_SCK_MARK,
3095 };
3096 static const unsigned int scifb1_ctrl_pins[] = {
3097         /* RTS, CTS */
3098         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3099 };
3100 static const unsigned int scifb1_ctrl_mux[] = {
3101         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3102 };
3103 static const unsigned int scifb1_data_b_pins[] = {
3104         /* RXD, TXD */
3105         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3106 };
3107 static const unsigned int scifb1_data_b_mux[] = {
3108         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3109 };
3110 static const unsigned int scifb1_clk_b_pins[] = {
3111         /* SCK */
3112         RCAR_GP_PIN(3, 1),
3113 };
3114 static const unsigned int scifb1_clk_b_mux[] = {
3115         SCIFB1_SCK_B_MARK,
3116 };
3117 static const unsigned int scifb1_ctrl_b_pins[] = {
3118         /* RTS, CTS */
3119         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3120 };
3121 static const unsigned int scifb1_ctrl_b_mux[] = {
3122         SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
3123 };
3124 static const unsigned int scifb1_data_c_pins[] = {
3125         /* RXD, TXD */
3126         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3127 };
3128 static const unsigned int scifb1_data_c_mux[] = {
3129         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3130 };
3131 static const unsigned int scifb1_data_d_pins[] = {
3132         /* RXD, TXD */
3133         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3134 };
3135 static const unsigned int scifb1_data_d_mux[] = {
3136         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3137 };
3138 static const unsigned int scifb1_data_e_pins[] = {
3139         /* RXD, TXD */
3140         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3141 };
3142 static const unsigned int scifb1_data_e_mux[] = {
3143         SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3144 };
3145 static const unsigned int scifb1_clk_e_pins[] = {
3146         /* SCK */
3147         RCAR_GP_PIN(3, 17),
3148 };
3149 static const unsigned int scifb1_clk_e_mux[] = {
3150         SCIFB1_SCK_E_MARK,
3151 };
3152 static const unsigned int scifb1_data_f_pins[] = {
3153         /* RXD, TXD */
3154         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3155 };
3156 static const unsigned int scifb1_data_f_mux[] = {
3157         SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3158 };
3159 static const unsigned int scifb1_data_g_pins[] = {
3160         /* RXD, TXD */
3161         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3162 };
3163 static const unsigned int scifb1_data_g_mux[] = {
3164         SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3165 };
3166 static const unsigned int scifb1_clk_g_pins[] = {
3167         /* SCK */
3168         RCAR_GP_PIN(2, 20),
3169 };
3170 static const unsigned int scifb1_clk_g_mux[] = {
3171         SCIFB1_SCK_G_MARK,
3172 };
3173 /* - SCIFB2 ----------------------------------------------------------------- */
3174 static const unsigned int scifb2_data_pins[] = {
3175         /* RXD, TXD */
3176         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3177 };
3178 static const unsigned int scifb2_data_mux[] = {
3179         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3180 };
3181 static const unsigned int scifb2_clk_pins[] = {
3182         /* SCK */
3183         RCAR_GP_PIN(4, 21),
3184 };
3185 static const unsigned int scifb2_clk_mux[] = {
3186         SCIFB2_SCK_MARK,
3187 };
3188 static const unsigned int scifb2_ctrl_pins[] = {
3189         /* RTS, CTS */
3190         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3191 };
3192 static const unsigned int scifb2_ctrl_mux[] = {
3193         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3194 };
3195 static const unsigned int scifb2_data_b_pins[] = {
3196         /* RXD, TXD */
3197         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3198 };
3199 static const unsigned int scifb2_data_b_mux[] = {
3200         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3201 };
3202 static const unsigned int scifb2_clk_b_pins[] = {
3203         /* SCK */
3204         RCAR_GP_PIN(0, 31),
3205 };
3206 static const unsigned int scifb2_clk_b_mux[] = {
3207         SCIFB2_SCK_B_MARK,
3208 };
3209 static const unsigned int scifb2_ctrl_b_pins[] = {
3210         /* RTS, CTS */
3211         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3212 };
3213 static const unsigned int scifb2_ctrl_b_mux[] = {
3214         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3215 };
3216 static const unsigned int scifb2_data_c_pins[] = {
3217         /* RXD, TXD */
3218         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3219 };
3220 static const unsigned int scifb2_data_c_mux[] = {
3221         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3222 };
3223 /* - SDHI0 ------------------------------------------------------------------ */
3224 static const unsigned int sdhi0_data1_pins[] = {
3225         /* D0 */
3226         RCAR_GP_PIN(3, 2),
3227 };
3228 static const unsigned int sdhi0_data1_mux[] = {
3229         SD0_DAT0_MARK,
3230 };
3231 static const unsigned int sdhi0_data4_pins[] = {
3232         /* D[0:3] */
3233         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3234 };
3235 static const unsigned int sdhi0_data4_mux[] = {
3236         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3237 };
3238 static const unsigned int sdhi0_ctrl_pins[] = {
3239         /* CLK, CMD */
3240         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3241 };
3242 static const unsigned int sdhi0_ctrl_mux[] = {
3243         SD0_CLK_MARK, SD0_CMD_MARK,
3244 };
3245 static const unsigned int sdhi0_cd_pins[] = {
3246         /* CD */
3247         RCAR_GP_PIN(3, 6),
3248 };
3249 static const unsigned int sdhi0_cd_mux[] = {
3250         SD0_CD_MARK,
3251 };
3252 static const unsigned int sdhi0_wp_pins[] = {
3253         /* WP */
3254         RCAR_GP_PIN(3, 7),
3255 };
3256 static const unsigned int sdhi0_wp_mux[] = {
3257         SD0_WP_MARK,
3258 };
3259 /* - SDHI1 ------------------------------------------------------------------ */
3260 static const unsigned int sdhi1_data1_pins[] = {
3261         /* D0 */
3262         RCAR_GP_PIN(3, 10),
3263 };
3264 static const unsigned int sdhi1_data1_mux[] = {
3265         SD1_DAT0_MARK,
3266 };
3267 static const unsigned int sdhi1_data4_pins[] = {
3268         /* D[0:3] */
3269         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3270 };
3271 static const unsigned int sdhi1_data4_mux[] = {
3272         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3273 };
3274 static const unsigned int sdhi1_ctrl_pins[] = {
3275         /* CLK, CMD */
3276         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3277 };
3278 static const unsigned int sdhi1_ctrl_mux[] = {
3279         SD1_CLK_MARK, SD1_CMD_MARK,
3280 };
3281 static const unsigned int sdhi1_cd_pins[] = {
3282         /* CD */
3283         RCAR_GP_PIN(3, 14),
3284 };
3285 static const unsigned int sdhi1_cd_mux[] = {
3286         SD1_CD_MARK,
3287 };
3288 static const unsigned int sdhi1_wp_pins[] = {
3289         /* WP */
3290         RCAR_GP_PIN(3, 15),
3291 };
3292 static const unsigned int sdhi1_wp_mux[] = {
3293         SD1_WP_MARK,
3294 };
3295 /* - SDHI2 ------------------------------------------------------------------ */
3296 static const unsigned int sdhi2_data1_pins[] = {
3297         /* D0 */
3298         RCAR_GP_PIN(3, 18),
3299 };
3300 static const unsigned int sdhi2_data1_mux[] = {
3301         SD2_DAT0_MARK,
3302 };
3303 static const unsigned int sdhi2_data4_pins[] = {
3304         /* D[0:3] */
3305         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3306 };
3307 static const unsigned int sdhi2_data4_mux[] = {
3308         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3309 };
3310 static const unsigned int sdhi2_ctrl_pins[] = {
3311         /* CLK, CMD */
3312         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3313 };
3314 static const unsigned int sdhi2_ctrl_mux[] = {
3315         SD2_CLK_MARK, SD2_CMD_MARK,
3316 };
3317 static const unsigned int sdhi2_cd_pins[] = {
3318         /* CD */
3319         RCAR_GP_PIN(3, 22),
3320 };
3321 static const unsigned int sdhi2_cd_mux[] = {
3322         SD2_CD_MARK,
3323 };
3324 static const unsigned int sdhi2_wp_pins[] = {
3325         /* WP */
3326         RCAR_GP_PIN(3, 23),
3327 };
3328 static const unsigned int sdhi2_wp_mux[] = {
3329         SD2_WP_MARK,
3330 };
3331 /* - SDHI3 ------------------------------------------------------------------ */
3332 static const unsigned int sdhi3_data1_pins[] = {
3333         /* D0 */
3334         RCAR_GP_PIN(3, 26),
3335 };
3336 static const unsigned int sdhi3_data1_mux[] = {
3337         SD3_DAT0_MARK,
3338 };
3339 static const unsigned int sdhi3_data4_pins[] = {
3340         /* D[0:3] */
3341         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3342 };
3343 static const unsigned int sdhi3_data4_mux[] = {
3344         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3345 };
3346 static const unsigned int sdhi3_ctrl_pins[] = {
3347         /* CLK, CMD */
3348         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3349 };
3350 static const unsigned int sdhi3_ctrl_mux[] = {
3351         SD3_CLK_MARK, SD3_CMD_MARK,
3352 };
3353 static const unsigned int sdhi3_cd_pins[] = {
3354         /* CD */
3355         RCAR_GP_PIN(3, 30),
3356 };
3357 static const unsigned int sdhi3_cd_mux[] = {
3358         SD3_CD_MARK,
3359 };
3360 static const unsigned int sdhi3_wp_pins[] = {
3361         /* WP */
3362         RCAR_GP_PIN(3, 31),
3363 };
3364 static const unsigned int sdhi3_wp_mux[] = {
3365         SD3_WP_MARK,
3366 };
3367 /* - SSI -------------------------------------------------------------------- */
3368 static const unsigned int ssi0_data_pins[] = {
3369         /* SDATA0 */
3370         RCAR_GP_PIN(4, 5),
3371 };
3372 static const unsigned int ssi0_data_mux[] = {
3373         SSI_SDATA0_MARK,
3374 };
3375 static const unsigned int ssi0129_ctrl_pins[] = {
3376         /* SCK, WS */
3377         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3378 };
3379 static const unsigned int ssi0129_ctrl_mux[] = {
3380         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3381 };
3382 static const unsigned int ssi1_data_pins[] = {
3383         /* SDATA1 */
3384         RCAR_GP_PIN(4, 6),
3385 };
3386 static const unsigned int ssi1_data_mux[] = {
3387         SSI_SDATA1_MARK,
3388 };
3389 static const unsigned int ssi1_ctrl_pins[] = {
3390         /* SCK, WS */
3391         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3392 };
3393 static const unsigned int ssi1_ctrl_mux[] = {
3394         SSI_SCK1_MARK, SSI_WS1_MARK,
3395 };
3396 static const unsigned int ssi2_data_pins[] = {
3397         /* SDATA2 */
3398         RCAR_GP_PIN(4, 7),
3399 };
3400 static const unsigned int ssi2_data_mux[] = {
3401         SSI_SDATA2_MARK,
3402 };
3403 static const unsigned int ssi2_ctrl_pins[] = {
3404         /* SCK, WS */
3405         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3406 };
3407 static const unsigned int ssi2_ctrl_mux[] = {
3408         SSI_SCK2_MARK, SSI_WS2_MARK,
3409 };
3410 static const unsigned int ssi3_data_pins[] = {
3411         /* SDATA3 */
3412         RCAR_GP_PIN(4, 10),
3413 };
3414 static const unsigned int ssi3_data_mux[] = {
3415         SSI_SDATA3_MARK
3416 };
3417 static const unsigned int ssi34_ctrl_pins[] = {
3418         /* SCK, WS */
3419         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3420 };
3421 static const unsigned int ssi34_ctrl_mux[] = {
3422         SSI_SCK34_MARK, SSI_WS34_MARK,
3423 };
3424 static const unsigned int ssi4_data_pins[] = {
3425         /* SDATA4 */
3426         RCAR_GP_PIN(4, 13),
3427 };
3428 static const unsigned int ssi4_data_mux[] = {
3429         SSI_SDATA4_MARK,
3430 };
3431 static const unsigned int ssi4_ctrl_pins[] = {
3432         /* SCK, WS */
3433         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3434 };
3435 static const unsigned int ssi4_ctrl_mux[] = {
3436         SSI_SCK4_MARK, SSI_WS4_MARK,
3437 };
3438 static const unsigned int ssi5_pins[] = {
3439         /* SDATA5, SCK, WS */
3440         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3441 };
3442 static const unsigned int ssi5_mux[] = {
3443         SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3444 };
3445 static const unsigned int ssi5_b_pins[] = {
3446         /* SDATA5, SCK, WS */
3447         RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3448 };
3449 static const unsigned int ssi5_b_mux[] = {
3450         SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3451 };
3452 static const unsigned int ssi5_c_pins[] = {
3453         /* SDATA5, SCK, WS */
3454         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3455 };
3456 static const unsigned int ssi5_c_mux[] = {
3457         SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3458 };
3459 static const unsigned int ssi6_pins[] = {
3460         /* SDATA6, SCK, WS */
3461         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3462 };
3463 static const unsigned int ssi6_mux[] = {
3464         SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3465 };
3466 static const unsigned int ssi6_b_pins[] = {
3467         /* SDATA6, SCK, WS */
3468         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3469 };
3470 static const unsigned int ssi6_b_mux[] = {
3471         SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3472 };
3473 static const unsigned int ssi7_data_pins[] = {
3474         /* SDATA7 */
3475         RCAR_GP_PIN(4, 22),
3476 };
3477 static const unsigned int ssi7_data_mux[] = {
3478         SSI_SDATA7_MARK,
3479 };
3480 static const unsigned int ssi7_b_data_pins[] = {
3481         /* SDATA7 */
3482         RCAR_GP_PIN(4, 22),
3483 };
3484 static const unsigned int ssi7_b_data_mux[] = {
3485         SSI_SDATA7_B_MARK,
3486 };
3487 static const unsigned int ssi7_c_data_pins[] = {
3488         /* SDATA7 */
3489         RCAR_GP_PIN(1, 26),
3490 };
3491 static const unsigned int ssi7_c_data_mux[] = {
3492         SSI_SDATA7_C_MARK,
3493 };
3494 static const unsigned int ssi78_ctrl_pins[] = {
3495         /* SCK, WS */
3496         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3497 };
3498 static const unsigned int ssi78_ctrl_mux[] = {
3499         SSI_SCK78_MARK, SSI_WS78_MARK,
3500 };
3501 static const unsigned int ssi78_b_ctrl_pins[] = {
3502         /* SCK, WS */
3503         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3504 };
3505 static const unsigned int ssi78_b_ctrl_mux[] = {
3506         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3507 };
3508 static const unsigned int ssi78_c_ctrl_pins[] = {
3509         /* SCK, WS */
3510         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3511 };
3512 static const unsigned int ssi78_c_ctrl_mux[] = {
3513         SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3514 };
3515 static const unsigned int ssi8_data_pins[] = {
3516         /* SDATA8 */
3517         RCAR_GP_PIN(4, 23),
3518 };
3519 static const unsigned int ssi8_data_mux[] = {
3520         SSI_SDATA8_MARK,
3521 };
3522 static const unsigned int ssi8_b_data_pins[] = {
3523         /* SDATA8 */
3524         RCAR_GP_PIN(4, 23),
3525 };
3526 static const unsigned int ssi8_b_data_mux[] = {
3527         SSI_SDATA8_B_MARK,
3528 };
3529 static const unsigned int ssi8_c_data_pins[] = {
3530         /* SDATA8 */
3531         RCAR_GP_PIN(1, 27),
3532 };
3533 static const unsigned int ssi8_c_data_mux[] = {
3534         SSI_SDATA8_C_MARK,
3535 };
3536 static const unsigned int ssi9_data_pins[] = {
3537         /* SDATA9 */
3538         RCAR_GP_PIN(4, 24),
3539 };
3540 static const unsigned int ssi9_data_mux[] = {
3541         SSI_SDATA9_MARK,
3542 };
3543 static const unsigned int ssi9_ctrl_pins[] = {
3544         /* SCK, WS */
3545         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3546 };
3547 static const unsigned int ssi9_ctrl_mux[] = {
3548         SSI_SCK9_MARK, SSI_WS9_MARK,
3549 };
3550 /* - TPU0 ------------------------------------------------------------------- */
3551 static const unsigned int tpu0_to0_pins[] = {
3552         /* TO */
3553         RCAR_GP_PIN(0, 20),
3554 };
3555 static const unsigned int tpu0_to0_mux[] = {
3556         TPU0TO0_MARK,
3557 };
3558 static const unsigned int tpu0_to1_pins[] = {
3559         /* TO */
3560         RCAR_GP_PIN(0, 21),
3561 };
3562 static const unsigned int tpu0_to1_mux[] = {
3563         TPU0TO1_MARK,
3564 };
3565 static const unsigned int tpu0_to2_pins[] = {
3566         /* TO */
3567         RCAR_GP_PIN(0, 22),
3568 };
3569 static const unsigned int tpu0_to2_mux[] = {
3570         TPU0TO2_MARK,
3571 };
3572 static const unsigned int tpu0_to3_pins[] = {
3573         /* TO */
3574         RCAR_GP_PIN(0, 23),
3575 };
3576 static const unsigned int tpu0_to3_mux[] = {
3577         TPU0TO3_MARK,
3578 };
3579 /* - USB0 ------------------------------------------------------------------- */
3580 static const unsigned int usb0_pins[] = {
3581         /* PWEN, OVC/VBUS */
3582         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3583 };
3584 static const unsigned int usb0_mux[] = {
3585         USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3586 };
3587 static const unsigned int usb0_ovc_vbus_pins[] = {
3588         /* OVC/VBUS */
3589         RCAR_GP_PIN(5, 19),
3590 };
3591 static const unsigned int usb0_ovc_vbus_mux[] = {
3592         USB0_OVC_VBUS_MARK,
3593 };
3594 /* - USB1 ------------------------------------------------------------------- */
3595 static const unsigned int usb1_pins[] = {
3596         /* PWEN, OVC */
3597         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3598 };
3599 static const unsigned int usb1_mux[] = {
3600         USB1_PWEN_MARK, USB1_OVC_MARK,
3601 };
3602 /* - USB2 ------------------------------------------------------------------- */
3603 static const unsigned int usb2_pins[] = {
3604         /* PWEN, OVC */
3605         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3606 };
3607 static const unsigned int usb2_mux[] = {
3608         USB2_PWEN_MARK, USB2_OVC_MARK,
3609 };
3610
3611 union vin_data {
3612         unsigned int data24[24];
3613         unsigned int data20[20];
3614         unsigned int data16[16];
3615         unsigned int data12[12];
3616         unsigned int data10[10];
3617         unsigned int data8[8];
3618         unsigned int data4[4];
3619 };
3620
3621 #define VIN_DATA_PIN_GROUP(n, s)                                \
3622         {                                                       \
3623                 .name = #n#s,                                   \
3624                 .pins = n##_pins.data##s,                       \
3625                 .mux = n##_mux.data##s,                         \
3626                 .nr_pins = ARRAY_SIZE(n##_pins.data##s),        \
3627         }
3628
3629 /* - VIN0 ------------------------------------------------------------------- */
3630 static const union vin_data vin0_data_pins = {
3631         .data24 = {
3632                 /* B */
3633                 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3634                 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3635                 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3636                 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3637                 /* G */
3638                 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3639                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3640                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3641                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3642                 /* R */
3643                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3644                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3645                 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3646                 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3647         },
3648 };
3649 static const union vin_data vin0_data_mux = {
3650         .data24 = {
3651                 /* B */
3652                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3653                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3654                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3655                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3656                 /* G */
3657                 VI0_G0_MARK, VI0_G1_MARK,
3658                 VI0_G2_MARK, VI0_G3_MARK,
3659                 VI0_G4_MARK, VI0_G5_MARK,
3660                 VI0_G6_MARK, VI0_G7_MARK,
3661                 /* R */
3662                 VI0_R0_MARK, VI0_R1_MARK,
3663                 VI0_R2_MARK, VI0_R3_MARK,
3664                 VI0_R4_MARK, VI0_R5_MARK,
3665                 VI0_R6_MARK, VI0_R7_MARK,
3666         },
3667 };
3668 static const unsigned int vin0_data18_pins[] = {
3669         /* B */
3670         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3671         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3672         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3673         /* G */
3674         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3675         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3676         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3677         /* R */
3678         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3679         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3680         RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3681 };
3682 static const unsigned int vin0_data18_mux[] = {
3683         /* B */
3684         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3685         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3686         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3687         /* G */
3688         VI0_G2_MARK, VI0_G3_MARK,
3689         VI0_G4_MARK, VI0_G5_MARK,
3690         VI0_G6_MARK, VI0_G7_MARK,
3691         /* R */
3692         VI0_R2_MARK, VI0_R3_MARK,
3693         VI0_R4_MARK, VI0_R5_MARK,
3694         VI0_R6_MARK, VI0_R7_MARK,
3695 };
3696 static const unsigned int vin0_sync_pins[] = {
3697         RCAR_GP_PIN(0, 12), /* HSYNC */
3698         RCAR_GP_PIN(0, 13), /* VSYNC */
3699 };
3700 static const unsigned int vin0_sync_mux[] = {
3701         VI0_HSYNC_N_MARK,
3702         VI0_VSYNC_N_MARK,
3703 };
3704 static const unsigned int vin0_field_pins[] = {
3705         RCAR_GP_PIN(0, 15),
3706 };
3707 static const unsigned int vin0_field_mux[] = {
3708         VI0_FIELD_MARK,
3709 };
3710 static const unsigned int vin0_clkenb_pins[] = {
3711         RCAR_GP_PIN(0, 14),
3712 };
3713 static const unsigned int vin0_clkenb_mux[] = {
3714         VI0_CLKENB_MARK,
3715 };
3716 static const unsigned int vin0_clk_pins[] = {
3717         RCAR_GP_PIN(2, 0),
3718 };
3719 static const unsigned int vin0_clk_mux[] = {
3720         VI0_CLK_MARK,
3721 };
3722 /* - VIN1 ------------------------------------------------------------------- */
3723 static const union vin_data vin1_data_pins = {
3724         .data24 = {
3725                 /* B */
3726                 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3727                 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3728                 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3729                 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3730                 /* G */
3731                 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3732                 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3733                 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3734                 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3735                 /* R */
3736                 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3737                 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3738                 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3739                 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3740         },
3741 };
3742 static const union vin_data vin1_data_mux = {
3743         .data24 = {
3744                 /* B */
3745                 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3746                 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3747                 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3748                 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3749                 /* G */
3750                 VI1_G0_MARK, VI1_G1_MARK,
3751                 VI1_G2_MARK, VI1_G3_MARK,
3752                 VI1_G4_MARK, VI1_G5_MARK,
3753                 VI1_G6_MARK, VI1_G7_MARK,
3754                 /* R */
3755                 VI1_R0_MARK, VI1_R1_MARK,
3756                 VI1_R2_MARK, VI1_R3_MARK,
3757                 VI1_R4_MARK, VI1_R5_MARK,
3758                 VI1_R6_MARK, VI1_R7_MARK,
3759         },
3760 };
3761 static const unsigned int vin1_data18_pins[] = {
3762         /* B */
3763         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3764         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3765         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3766         /* G */
3767         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3768         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3769         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3770         /* R */
3771         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3772         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3773         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3774 };
3775 static const unsigned int vin1_data18_mux[] = {
3776         /* B */
3777         VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3778         VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3779         VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3780         /* G */
3781         VI1_G2_MARK, VI1_G3_MARK,
3782         VI1_G4_MARK, VI1_G5_MARK,
3783         VI1_G6_MARK, VI1_G7_MARK,
3784         /* R */
3785         VI1_R2_MARK, VI1_R3_MARK,
3786         VI1_R4_MARK, VI1_R5_MARK,
3787         VI1_R6_MARK, VI1_R7_MARK,
3788 };
3789 static const unsigned int vin1_sync_pins[] = {
3790         RCAR_GP_PIN(1, 24), /* HSYNC */
3791         RCAR_GP_PIN(1, 25), /* VSYNC */
3792 };
3793 static const unsigned int vin1_sync_mux[] = {
3794         VI1_HSYNC_N_MARK,
3795         VI1_VSYNC_N_MARK,
3796 };
3797 static const unsigned int vin1_field_pins[] = {
3798         RCAR_GP_PIN(1, 13),
3799 };
3800 static const unsigned int vin1_field_mux[] = {
3801         VI1_FIELD_MARK,
3802 };
3803 static const unsigned int vin1_clkenb_pins[] = {
3804         RCAR_GP_PIN(1, 26),
3805 };
3806 static const unsigned int vin1_clkenb_mux[] = {
3807         VI1_CLKENB_MARK,
3808 };
3809 static const unsigned int vin1_clk_pins[] = {
3810         RCAR_GP_PIN(2, 9),
3811 };
3812 static const unsigned int vin1_clk_mux[] = {
3813         VI1_CLK_MARK,
3814 };
3815 /* - VIN2 ----------------------------------------------------------------- */
3816 static const union vin_data vin2_data_pins = {
3817         .data24 = {
3818                 /* B */
3819                 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3820                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3821                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3822                 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3823                 /* G */
3824                 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3825                 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3826                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3827                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3828                 /* R */
3829                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3830                 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3831                 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3832                 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3833         },
3834 };
3835 static const union vin_data vin2_data_mux = {
3836         .data24 = {
3837                 /* B */
3838                 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3839                 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3840                 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3841                 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3842                 /* G */
3843                 VI2_G0_MARK, VI2_G1_MARK,
3844                 VI2_G2_MARK, VI2_G3_MARK,
3845                 VI2_G4_MARK, VI2_G5_MARK,
3846                 VI2_G6_MARK, VI2_G7_MARK,
3847                 /* R */
3848                 VI2_R0_MARK, VI2_R1_MARK,
3849                 VI2_R2_MARK, VI2_R3_MARK,
3850                 VI2_R4_MARK, VI2_R5_MARK,
3851                 VI2_R6_MARK, VI2_R7_MARK,
3852         },
3853 };
3854 static const unsigned int vin2_data18_pins[] = {
3855         /* B */
3856         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3857         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3858         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3859         /* G */
3860         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3861         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3862         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3863         /* R */
3864         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3865         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3866         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3867 };
3868 static const unsigned int vin2_data18_mux[] = {
3869         /* B */
3870         VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3871         VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3872         VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3873         /* G */
3874         VI2_G2_MARK, VI2_G3_MARK,
3875         VI2_G4_MARK, VI2_G5_MARK,
3876         VI2_G6_MARK, VI2_G7_MARK,
3877         /* R */
3878         VI2_R2_MARK, VI2_R3_MARK,
3879         VI2_R4_MARK, VI2_R5_MARK,
3880         VI2_R6_MARK, VI2_R7_MARK,
3881 };
3882 static const unsigned int vin2_sync_pins[] = {
3883         RCAR_GP_PIN(1, 16), /* HSYNC */
3884         RCAR_GP_PIN(1, 21), /* VSYNC */
3885 };
3886 static const unsigned int vin2_sync_mux[] = {
3887         VI2_HSYNC_N_MARK,
3888         VI2_VSYNC_N_MARK,
3889 };
3890 static const unsigned int vin2_field_pins[] = {
3891         RCAR_GP_PIN(1, 9),
3892 };
3893 static const unsigned int vin2_field_mux[] = {
3894         VI2_FIELD_MARK,
3895 };
3896 static const unsigned int vin2_clkenb_pins[] = {
3897         RCAR_GP_PIN(1, 8),
3898 };
3899 static const unsigned int vin2_clkenb_mux[] = {
3900         VI2_CLKENB_MARK,
3901 };
3902 static const unsigned int vin2_clk_pins[] = {
3903         RCAR_GP_PIN(1, 11),
3904 };
3905 static const unsigned int vin2_clk_mux[] = {
3906         VI2_CLK_MARK,
3907 };
3908 /* - VIN3 ----------------------------------------------------------------- */
3909 static const unsigned int vin3_data8_pins[] = {
3910         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3911         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3912         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3913         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3914 };
3915 static const unsigned int vin3_data8_mux[] = {
3916         VI3_DATA0_MARK, VI3_DATA1_MARK,
3917         VI3_DATA2_MARK, VI3_DATA3_MARK,
3918         VI3_DATA4_MARK, VI3_DATA5_MARK,
3919         VI3_DATA6_MARK, VI3_DATA7_MARK,
3920 };
3921 static const unsigned int vin3_sync_pins[] = {
3922         RCAR_GP_PIN(1, 16), /* HSYNC */
3923         RCAR_GP_PIN(1, 17), /* VSYNC */
3924 };
3925 static const unsigned int vin3_sync_mux[] = {
3926         VI3_HSYNC_N_MARK,
3927         VI3_VSYNC_N_MARK,
3928 };
3929 static const unsigned int vin3_field_pins[] = {
3930         RCAR_GP_PIN(1, 15),
3931 };
3932 static const unsigned int vin3_field_mux[] = {
3933         VI3_FIELD_MARK,
3934 };
3935 static const unsigned int vin3_clkenb_pins[] = {
3936         RCAR_GP_PIN(1, 14),
3937 };
3938 static const unsigned int vin3_clkenb_mux[] = {
3939         VI3_CLKENB_MARK,
3940 };
3941 static const unsigned int vin3_clk_pins[] = {
3942         RCAR_GP_PIN(1, 23),
3943 };
3944 static const unsigned int vin3_clk_mux[] = {
3945         VI3_CLK_MARK,
3946 };
3947
3948 static const struct sh_pfc_pin_group pinmux_groups[] = {
3949         SH_PFC_PIN_GROUP(audio_clk_a),
3950         SH_PFC_PIN_GROUP(audio_clk_b),
3951         SH_PFC_PIN_GROUP(audio_clk_c),
3952         SH_PFC_PIN_GROUP(audio_clkout),
3953         SH_PFC_PIN_GROUP(audio_clkout_b),
3954         SH_PFC_PIN_GROUP(audio_clkout_c),
3955         SH_PFC_PIN_GROUP(audio_clkout_d),
3956         SH_PFC_PIN_GROUP(avb_link),
3957         SH_PFC_PIN_GROUP(avb_magic),
3958         SH_PFC_PIN_GROUP(avb_phy_int),
3959         SH_PFC_PIN_GROUP(avb_mdio),
3960         SH_PFC_PIN_GROUP(avb_mii),
3961         SH_PFC_PIN_GROUP(avb_gmii),
3962         SH_PFC_PIN_GROUP(du_rgb666),
3963         SH_PFC_PIN_GROUP(du_rgb888),
3964         SH_PFC_PIN_GROUP(du_clk_out_0),
3965         SH_PFC_PIN_GROUP(du_clk_out_1),
3966         SH_PFC_PIN_GROUP(du_sync_0),
3967         SH_PFC_PIN_GROUP(du_sync_1),
3968         SH_PFC_PIN_GROUP(du_cde),
3969         SH_PFC_PIN_GROUP(du0_clk_in),
3970         SH_PFC_PIN_GROUP(du1_clk_in),
3971         SH_PFC_PIN_GROUP(du2_clk_in),
3972         SH_PFC_PIN_GROUP(eth_link),
3973         SH_PFC_PIN_GROUP(eth_magic),
3974         SH_PFC_PIN_GROUP(eth_mdio),
3975         SH_PFC_PIN_GROUP(eth_rmii),
3976         SH_PFC_PIN_GROUP(hscif0_data),
3977         SH_PFC_PIN_GROUP(hscif0_clk),
3978         SH_PFC_PIN_GROUP(hscif0_ctrl),
3979         SH_PFC_PIN_GROUP(hscif0_data_b),
3980         SH_PFC_PIN_GROUP(hscif0_ctrl_b),
3981         SH_PFC_PIN_GROUP(hscif0_data_c),
3982         SH_PFC_PIN_GROUP(hscif0_ctrl_c),
3983         SH_PFC_PIN_GROUP(hscif0_data_d),
3984         SH_PFC_PIN_GROUP(hscif0_ctrl_d),
3985         SH_PFC_PIN_GROUP(hscif0_data_e),
3986         SH_PFC_PIN_GROUP(hscif0_ctrl_e),
3987         SH_PFC_PIN_GROUP(hscif0_data_f),
3988         SH_PFC_PIN_GROUP(hscif0_ctrl_f),
3989         SH_PFC_PIN_GROUP(hscif1_data),
3990         SH_PFC_PIN_GROUP(hscif1_clk),
3991         SH_PFC_PIN_GROUP(hscif1_ctrl),
3992         SH_PFC_PIN_GROUP(hscif1_data_b),
3993         SH_PFC_PIN_GROUP(hscif1_clk_b),
3994         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3995         SH_PFC_PIN_GROUP(i2c0),
3996         SH_PFC_PIN_GROUP(i2c1),
3997         SH_PFC_PIN_GROUP(i2c1_b),
3998         SH_PFC_PIN_GROUP(i2c1_c),
3999         SH_PFC_PIN_GROUP(i2c2),
4000         SH_PFC_PIN_GROUP(i2c2_b),
4001         SH_PFC_PIN_GROUP(i2c2_c),
4002         SH_PFC_PIN_GROUP(i2c2_d),
4003         SH_PFC_PIN_GROUP(i2c2_e),
4004         SH_PFC_PIN_GROUP(i2c3),
4005         SH_PFC_PIN_GROUP(iic0),
4006         SH_PFC_PIN_GROUP(iic1),
4007         SH_PFC_PIN_GROUP(iic1_b),
4008         SH_PFC_PIN_GROUP(iic1_c),
4009         SH_PFC_PIN_GROUP(iic2),
4010         SH_PFC_PIN_GROUP(iic2_b),
4011         SH_PFC_PIN_GROUP(iic2_c),
4012         SH_PFC_PIN_GROUP(iic2_d),
4013         SH_PFC_PIN_GROUP(iic2_e),
4014         SH_PFC_PIN_GROUP(iic3),
4015         SH_PFC_PIN_GROUP(intc_irq0),
4016         SH_PFC_PIN_GROUP(intc_irq1),
4017         SH_PFC_PIN_GROUP(intc_irq2),
4018         SH_PFC_PIN_GROUP(intc_irq3),
4019         SH_PFC_PIN_GROUP(mlb_3pin),
4020         SH_PFC_PIN_GROUP(mmc0_data1),
4021         SH_PFC_PIN_GROUP(mmc0_data4),
4022         SH_PFC_PIN_GROUP(mmc0_data8),
4023         SH_PFC_PIN_GROUP(mmc0_ctrl),
4024         SH_PFC_PIN_GROUP(mmc1_data1),
4025         SH_PFC_PIN_GROUP(mmc1_data4),
4026         SH_PFC_PIN_GROUP(mmc1_data8),
4027         SH_PFC_PIN_GROUP(mmc1_ctrl),
4028         SH_PFC_PIN_GROUP(msiof0_clk),
4029         SH_PFC_PIN_GROUP(msiof0_sync),
4030         SH_PFC_PIN_GROUP(msiof0_ss1),
4031         SH_PFC_PIN_GROUP(msiof0_ss2),
4032         SH_PFC_PIN_GROUP(msiof0_rx),
4033         SH_PFC_PIN_GROUP(msiof0_tx),
4034         SH_PFC_PIN_GROUP(msiof0_clk_b),
4035         SH_PFC_PIN_GROUP(msiof0_ss1_b),
4036         SH_PFC_PIN_GROUP(msiof0_ss2_b),
4037         SH_PFC_PIN_GROUP(msiof0_rx_b),
4038         SH_PFC_PIN_GROUP(msiof0_tx_b),
4039         SH_PFC_PIN_GROUP(msiof1_clk),
4040         SH_PFC_PIN_GROUP(msiof1_sync),
4041         SH_PFC_PIN_GROUP(msiof1_ss1),
4042         SH_PFC_PIN_GROUP(msiof1_ss2),
4043         SH_PFC_PIN_GROUP(msiof1_rx),
4044         SH_PFC_PIN_GROUP(msiof1_tx),
4045         SH_PFC_PIN_GROUP(msiof1_clk_b),
4046         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4047         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4048         SH_PFC_PIN_GROUP(msiof1_rx_b),
4049         SH_PFC_PIN_GROUP(msiof1_tx_b),
4050         SH_PFC_PIN_GROUP(msiof2_clk),
4051         SH_PFC_PIN_GROUP(msiof2_sync),
4052         SH_PFC_PIN_GROUP(msiof2_ss1),
4053         SH_PFC_PIN_GROUP(msiof2_ss2),
4054         SH_PFC_PIN_GROUP(msiof2_rx),
4055         SH_PFC_PIN_GROUP(msiof2_tx),
4056         SH_PFC_PIN_GROUP(msiof3_clk),
4057         SH_PFC_PIN_GROUP(msiof3_sync),
4058         SH_PFC_PIN_GROUP(msiof3_ss1),
4059         SH_PFC_PIN_GROUP(msiof3_ss2),
4060         SH_PFC_PIN_GROUP(msiof3_rx),
4061         SH_PFC_PIN_GROUP(msiof3_tx),
4062         SH_PFC_PIN_GROUP(msiof3_clk_b),
4063         SH_PFC_PIN_GROUP(msiof3_sync_b),
4064         SH_PFC_PIN_GROUP(msiof3_rx_b),
4065         SH_PFC_PIN_GROUP(msiof3_tx_b),
4066         SH_PFC_PIN_GROUP(pwm0),
4067         SH_PFC_PIN_GROUP(pwm0_b),
4068         SH_PFC_PIN_GROUP(pwm1),
4069         SH_PFC_PIN_GROUP(pwm1_b),
4070         SH_PFC_PIN_GROUP(pwm2),
4071         SH_PFC_PIN_GROUP(pwm3),
4072         SH_PFC_PIN_GROUP(pwm4),
4073         SH_PFC_PIN_GROUP(pwm5),
4074         SH_PFC_PIN_GROUP(pwm6),
4075         SH_PFC_PIN_GROUP(qspi_ctrl),
4076         SH_PFC_PIN_GROUP(qspi_data2),
4077         SH_PFC_PIN_GROUP(qspi_data4),
4078         SH_PFC_PIN_GROUP(scif0_data),
4079         SH_PFC_PIN_GROUP(scif0_clk),
4080         SH_PFC_PIN_GROUP(scif0_ctrl),
4081         SH_PFC_PIN_GROUP(scif0_data_b),
4082         SH_PFC_PIN_GROUP(scif1_data),
4083         SH_PFC_PIN_GROUP(scif1_clk),
4084         SH_PFC_PIN_GROUP(scif1_ctrl),
4085         SH_PFC_PIN_GROUP(scif1_data_b),
4086         SH_PFC_PIN_GROUP(scif1_data_c),
4087         SH_PFC_PIN_GROUP(scif1_data_d),
4088         SH_PFC_PIN_GROUP(scif1_clk_d),
4089         SH_PFC_PIN_GROUP(scif1_data_e),
4090         SH_PFC_PIN_GROUP(scif1_clk_e),
4091         SH_PFC_PIN_GROUP(scif2_data),
4092         SH_PFC_PIN_GROUP(scif2_clk),
4093         SH_PFC_PIN_GROUP(scif2_data_b),
4094         SH_PFC_PIN_GROUP(scifa0_data),
4095         SH_PFC_PIN_GROUP(scifa0_clk),
4096         SH_PFC_PIN_GROUP(scifa0_ctrl),
4097         SH_PFC_PIN_GROUP(scifa0_data_b),
4098         SH_PFC_PIN_GROUP(scifa0_clk_b),
4099         SH_PFC_PIN_GROUP(scifa0_ctrl_b),
4100         SH_PFC_PIN_GROUP(scifa1_data),
4101         SH_PFC_PIN_GROUP(scifa1_clk),
4102         SH_PFC_PIN_GROUP(scifa1_ctrl),
4103         SH_PFC_PIN_GROUP(scifa1_data_b),
4104         SH_PFC_PIN_GROUP(scifa1_clk_b),
4105         SH_PFC_PIN_GROUP(scifa1_ctrl_b),
4106         SH_PFC_PIN_GROUP(scifa1_data_c),
4107         SH_PFC_PIN_GROUP(scifa1_clk_c),
4108         SH_PFC_PIN_GROUP(scifa1_ctrl_c),
4109         SH_PFC_PIN_GROUP(scifa1_data_d),
4110         SH_PFC_PIN_GROUP(scifa1_clk_d),
4111         SH_PFC_PIN_GROUP(scifa1_ctrl_d),
4112         SH_PFC_PIN_GROUP(scifa2_data),
4113         SH_PFC_PIN_GROUP(scifa2_clk),
4114         SH_PFC_PIN_GROUP(scifa2_ctrl),
4115         SH_PFC_PIN_GROUP(scifa2_data_b),
4116         SH_PFC_PIN_GROUP(scifa2_data_c),
4117         SH_PFC_PIN_GROUP(scifa2_clk_c),
4118         SH_PFC_PIN_GROUP(scifb0_data),
4119         SH_PFC_PIN_GROUP(scifb0_clk),
4120         SH_PFC_PIN_GROUP(scifb0_ctrl),
4121         SH_PFC_PIN_GROUP(scifb0_data_b),
4122         SH_PFC_PIN_GROUP(scifb0_clk_b),
4123         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4124         SH_PFC_PIN_GROUP(scifb0_data_c),
4125         SH_PFC_PIN_GROUP(scifb1_data),
4126         SH_PFC_PIN_GROUP(scifb1_clk),
4127         SH_PFC_PIN_GROUP(scifb1_ctrl),
4128         SH_PFC_PIN_GROUP(scifb1_data_b),
4129         SH_PFC_PIN_GROUP(scifb1_clk_b),
4130         SH_PFC_PIN_GROUP(scifb1_ctrl_b),
4131         SH_PFC_PIN_GROUP(scifb1_data_c),
4132         SH_PFC_PIN_GROUP(scifb1_data_d),
4133         SH_PFC_PIN_GROUP(scifb1_data_e),
4134         SH_PFC_PIN_GROUP(scifb1_clk_e),
4135         SH_PFC_PIN_GROUP(scifb1_data_f),
4136         SH_PFC_PIN_GROUP(scifb1_data_g),
4137         SH_PFC_PIN_GROUP(scifb1_clk_g),
4138         SH_PFC_PIN_GROUP(scifb2_data),
4139         SH_PFC_PIN_GROUP(scifb2_clk),
4140         SH_PFC_PIN_GROUP(scifb2_ctrl),
4141         SH_PFC_PIN_GROUP(scifb2_data_b),
4142         SH_PFC_PIN_GROUP(scifb2_clk_b),
4143         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4144         SH_PFC_PIN_GROUP(scifb2_data_c),
4145         SH_PFC_PIN_GROUP(sdhi0_data1),
4146         SH_PFC_PIN_GROUP(sdhi0_data4),
4147         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4148         SH_PFC_PIN_GROUP(sdhi0_cd),
4149         SH_PFC_PIN_GROUP(sdhi0_wp),
4150         SH_PFC_PIN_GROUP(sdhi1_data1),
4151         SH_PFC_PIN_GROUP(sdhi1_data4),
4152         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4153         SH_PFC_PIN_GROUP(sdhi1_cd),
4154         SH_PFC_PIN_GROUP(sdhi1_wp),
4155         SH_PFC_PIN_GROUP(sdhi2_data1),
4156         SH_PFC_PIN_GROUP(sdhi2_data4),
4157         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4158         SH_PFC_PIN_GROUP(sdhi2_cd),
4159         SH_PFC_PIN_GROUP(sdhi2_wp),
4160         SH_PFC_PIN_GROUP(sdhi3_data1),
4161         SH_PFC_PIN_GROUP(sdhi3_data4),
4162         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4163         SH_PFC_PIN_GROUP(sdhi3_cd),
4164         SH_PFC_PIN_GROUP(sdhi3_wp),
4165         SH_PFC_PIN_GROUP(ssi0_data),
4166         SH_PFC_PIN_GROUP(ssi0129_ctrl),
4167         SH_PFC_PIN_GROUP(ssi1_data),
4168         SH_PFC_PIN_GROUP(ssi1_ctrl),
4169         SH_PFC_PIN_GROUP(ssi2_data),
4170         SH_PFC_PIN_GROUP(ssi2_ctrl),
4171         SH_PFC_PIN_GROUP(ssi3_data),
4172         SH_PFC_PIN_GROUP(ssi34_ctrl),
4173         SH_PFC_PIN_GROUP(ssi4_data),
4174         SH_PFC_PIN_GROUP(ssi4_ctrl),
4175         SH_PFC_PIN_GROUP(ssi5),
4176         SH_PFC_PIN_GROUP(ssi5_b),
4177         SH_PFC_PIN_GROUP(ssi5_c),
4178         SH_PFC_PIN_GROUP(ssi6),
4179         SH_PFC_PIN_GROUP(ssi6_b),
4180         SH_PFC_PIN_GROUP(ssi7_data),
4181         SH_PFC_PIN_GROUP(ssi7_b_data),
4182         SH_PFC_PIN_GROUP(ssi7_c_data),
4183         SH_PFC_PIN_GROUP(ssi78_ctrl),
4184         SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4185         SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4186         SH_PFC_PIN_GROUP(ssi8_data),
4187         SH_PFC_PIN_GROUP(ssi8_b_data),
4188         SH_PFC_PIN_GROUP(ssi8_c_data),
4189         SH_PFC_PIN_GROUP(ssi9_data),
4190         SH_PFC_PIN_GROUP(ssi9_ctrl),
4191         SH_PFC_PIN_GROUP(tpu0_to0),
4192         SH_PFC_PIN_GROUP(tpu0_to1),
4193         SH_PFC_PIN_GROUP(tpu0_to2),
4194         SH_PFC_PIN_GROUP(tpu0_to3),
4195         SH_PFC_PIN_GROUP(usb0),
4196         SH_PFC_PIN_GROUP(usb0_ovc_vbus),
4197         SH_PFC_PIN_GROUP(usb1),
4198         SH_PFC_PIN_GROUP(usb2),
4199         VIN_DATA_PIN_GROUP(vin0_data, 24),
4200         VIN_DATA_PIN_GROUP(vin0_data, 20),
4201         SH_PFC_PIN_GROUP(vin0_data18),
4202         VIN_DATA_PIN_GROUP(vin0_data, 16),
4203         VIN_DATA_PIN_GROUP(vin0_data, 12),
4204         VIN_DATA_PIN_GROUP(vin0_data, 10),
4205         VIN_DATA_PIN_GROUP(vin0_data, 8),
4206         VIN_DATA_PIN_GROUP(vin0_data, 4),
4207         SH_PFC_PIN_GROUP(vin0_sync),
4208         SH_PFC_PIN_GROUP(vin0_field),
4209         SH_PFC_PIN_GROUP(vin0_clkenb),
4210         SH_PFC_PIN_GROUP(vin0_clk),
4211         VIN_DATA_PIN_GROUP(vin1_data, 24),
4212         VIN_DATA_PIN_GROUP(vin1_data, 20),
4213         SH_PFC_PIN_GROUP(vin1_data18),
4214         VIN_DATA_PIN_GROUP(vin1_data, 16),
4215         VIN_DATA_PIN_GROUP(vin1_data, 12),
4216         VIN_DATA_PIN_GROUP(vin1_data, 10),
4217         VIN_DATA_PIN_GROUP(vin1_data, 8),
4218         VIN_DATA_PIN_GROUP(vin1_data, 4),
4219         SH_PFC_PIN_GROUP(vin1_sync),
4220         SH_PFC_PIN_GROUP(vin1_field),
4221         SH_PFC_PIN_GROUP(vin1_clkenb),
4222         SH_PFC_PIN_GROUP(vin1_clk),
4223         VIN_DATA_PIN_GROUP(vin2_data, 24),
4224         SH_PFC_PIN_GROUP(vin2_data18),
4225         VIN_DATA_PIN_GROUP(vin2_data, 16),
4226         VIN_DATA_PIN_GROUP(vin2_data, 8),
4227         VIN_DATA_PIN_GROUP(vin2_data, 4),
4228         SH_PFC_PIN_GROUP(vin2_sync),
4229         SH_PFC_PIN_GROUP(vin2_field),
4230         SH_PFC_PIN_GROUP(vin2_clkenb),
4231         SH_PFC_PIN_GROUP(vin2_clk),
4232         SH_PFC_PIN_GROUP(vin3_data8),
4233         SH_PFC_PIN_GROUP(vin3_sync),
4234         SH_PFC_PIN_GROUP(vin3_field),
4235         SH_PFC_PIN_GROUP(vin3_clkenb),
4236         SH_PFC_PIN_GROUP(vin3_clk),
4237 };
4238
4239 static const char * const audio_clk_groups[] = {
4240         "audio_clk_a",
4241         "audio_clk_b",
4242         "audio_clk_c",
4243         "audio_clkout",
4244         "audio_clkout_b",
4245         "audio_clkout_c",
4246         "audio_clkout_d",
4247 };
4248
4249 static const char * const avb_groups[] = {
4250         "avb_link",
4251         "avb_magic",
4252         "avb_phy_int",
4253         "avb_mdio",
4254         "avb_mii",
4255         "avb_gmii",
4256 };
4257
4258 static const char * const du_groups[] = {
4259         "du_rgb666",
4260         "du_rgb888",
4261         "du_clk_out_0",
4262         "du_clk_out_1",
4263         "du_sync_0",
4264         "du_sync_1",
4265         "du_cde",
4266 };
4267
4268 static const char * const du0_groups[] = {
4269         "du0_clk_in",
4270 };
4271
4272 static const char * const du1_groups[] = {
4273         "du1_clk_in",
4274 };
4275
4276 static const char * const du2_groups[] = {
4277         "du2_clk_in",
4278 };
4279
4280 static const char * const eth_groups[] = {
4281         "eth_link",
4282         "eth_magic",
4283         "eth_mdio",
4284         "eth_rmii",
4285 };
4286
4287 static const char * const hscif0_groups[] = {
4288         "hscif0_data",
4289         "hscif0_clk",
4290         "hscif0_ctrl",
4291         "hscif0_data_b",
4292         "hscif0_ctrl_b",
4293         "hscif0_data_c",
4294         "hscif0_ctrl_c",
4295         "hscif0_data_d",
4296         "hscif0_ctrl_d",
4297         "hscif0_data_e",
4298         "hscif0_ctrl_e",
4299         "hscif0_data_f",
4300         "hscif0_ctrl_f",
4301 };
4302
4303 static const char * const hscif1_groups[] = {
4304         "hscif1_data",
4305         "hscif1_clk",
4306         "hscif1_ctrl",
4307         "hscif1_data_b",
4308         "hscif1_clk_b",
4309         "hscif1_ctrl_b",
4310 };
4311
4312 static const char * const i2c0_groups[] = {
4313         "i2c0",
4314 };
4315
4316 static const char * const i2c1_groups[] = {
4317         "i2c1",
4318         "i2c1_b",
4319         "i2c1_c",
4320 };
4321
4322 static const char * const i2c2_groups[] = {
4323         "i2c2",
4324         "i2c2_b",
4325         "i2c2_c",
4326         "i2c2_d",
4327         "i2c2_e",
4328 };
4329
4330 static const char * const i2c3_groups[] = {
4331         "i2c3",
4332 };
4333
4334 static const char * const iic0_groups[] = {
4335         "iic0",
4336 };
4337
4338 static const char * const iic1_groups[] = {
4339         "iic1",
4340         "iic1_b",
4341         "iic1_c",
4342 };
4343
4344 static const char * const iic2_groups[] = {
4345         "iic2",
4346         "iic2_b",
4347         "iic2_c",
4348         "iic2_d",
4349         "iic2_e",
4350 };
4351
4352 static const char * const iic3_groups[] = {
4353         "iic3",
4354 };
4355
4356 static const char * const intc_groups[] = {
4357         "intc_irq0",
4358         "intc_irq1",
4359         "intc_irq2",
4360         "intc_irq3",
4361 };
4362
4363 static const char * const mlb_groups[] = {
4364         "mlb_3pin",
4365 };
4366
4367 static const char * const mmc0_groups[] = {
4368         "mmc0_data1",
4369         "mmc0_data4",
4370         "mmc0_data8",
4371         "mmc0_ctrl",
4372 };
4373
4374 static const char * const mmc1_groups[] = {
4375         "mmc1_data1",
4376         "mmc1_data4",
4377         "mmc1_data8",
4378         "mmc1_ctrl",
4379 };
4380
4381 static const char * const msiof0_groups[] = {
4382         "msiof0_clk",
4383         "msiof0_sync",
4384         "msiof0_ss1",
4385         "msiof0_ss2",
4386         "msiof0_rx",
4387         "msiof0_tx",
4388         "msiof0_clk_b",
4389         "msiof0_ss1_b",
4390         "msiof0_ss2_b",
4391         "msiof0_rx_b",
4392         "msiof0_tx_b",
4393 };
4394
4395 static const char * const msiof1_groups[] = {
4396         "msiof1_clk",
4397         "msiof1_sync",
4398         "msiof1_ss1",
4399         "msiof1_ss2",
4400         "msiof1_rx",
4401         "msiof1_tx",
4402         "msiof1_clk_b",
4403         "msiof1_ss1_b",
4404         "msiof1_ss2_b",
4405         "msiof1_rx_b",
4406         "msiof1_tx_b",
4407 };
4408
4409 static const char * const msiof2_groups[] = {
4410         "msiof2_clk",
4411         "msiof2_sync",
4412         "msiof2_ss1",
4413         "msiof2_ss2",
4414         "msiof2_rx",
4415         "msiof2_tx",
4416 };
4417
4418 static const char * const msiof3_groups[] = {
4419         "msiof3_clk",
4420         "msiof3_sync",
4421         "msiof3_ss1",
4422         "msiof3_ss2",
4423         "msiof3_rx",
4424         "msiof3_tx",
4425         "msiof3_clk_b",
4426         "msiof3_sync_b",
4427         "msiof3_rx_b",
4428         "msiof3_tx_b",
4429 };
4430
4431 static const char * const pwm0_groups[] = {
4432         "pwm0",
4433         "pwm0_b",
4434 };
4435
4436 static const char * const pwm1_groups[] = {
4437         "pwm1",
4438         "pwm1_b",
4439 };
4440
4441 static const char * const pwm2_groups[] = {
4442         "pwm2",
4443 };
4444
4445 static const char * const pwm3_groups[] = {
4446         "pwm3",
4447 };
4448
4449 static const char * const pwm4_groups[] = {
4450         "pwm4",
4451 };
4452
4453 static const char * const pwm5_groups[] = {
4454         "pwm5",
4455 };
4456
4457 static const char * const pwm6_groups[] = {
4458         "pwm6",
4459 };
4460
4461 static const char * const qspi_groups[] = {
4462         "qspi_ctrl",
4463         "qspi_data2",
4464         "qspi_data4",
4465 };
4466
4467 static const char * const scif0_groups[] = {
4468         "scif0_data",
4469         "scif0_clk",
4470         "scif0_ctrl",
4471         "scif0_data_b",
4472 };
4473
4474 static const char * const scif1_groups[] = {
4475         "scif1_data",
4476         "scif1_clk",
4477         "scif1_ctrl",
4478         "scif1_data_b",
4479         "scif1_data_c",
4480         "scif1_data_d",
4481         "scif1_clk_d",
4482         "scif1_data_e",
4483         "scif1_clk_e",
4484 };
4485
4486 static const char * const scif2_groups[] = {
4487         "scif2_data",
4488         "scif2_clk",
4489         "scif2_data_b",
4490 };
4491
4492 static const char * const scifa0_groups[] = {
4493         "scifa0_data",
4494         "scifa0_clk",
4495         "scifa0_ctrl",
4496         "scifa0_data_b",
4497         "scifa0_clk_b",
4498         "scifa0_ctrl_b",
4499 };
4500
4501 static const char * const scifa1_groups[] = {
4502         "scifa1_data",
4503         "scifa1_clk",
4504         "scifa1_ctrl",
4505         "scifa1_data_b",
4506         "scifa1_clk_b",
4507         "scifa1_ctrl_b",
4508         "scifa1_data_c",
4509         "scifa1_clk_c",
4510         "scifa1_ctrl_c",
4511         "scifa1_data_d",
4512         "scifa1_clk_d",
4513         "scifa1_ctrl_d",
4514 };
4515
4516 static const char * const scifa2_groups[] = {
4517         "scifa2_data",
4518         "scifa2_clk",
4519         "scifa2_ctrl",
4520         "scifa2_data_b",
4521         "scifa2_data_c",
4522         "scifa2_clk_c",
4523 };
4524
4525 static const char * const scifb0_groups[] = {
4526         "scifb0_data",
4527         "scifb0_clk",
4528         "scifb0_ctrl",
4529         "scifb0_data_b",
4530         "scifb0_clk_b",
4531         "scifb0_ctrl_b",
4532         "scifb0_data_c",
4533 };
4534
4535 static const char * const scifb1_groups[] = {
4536         "scifb1_data",
4537         "scifb1_clk",
4538         "scifb1_ctrl",
4539         "scifb1_data_b",
4540         "scifb1_clk_b",
4541         "scifb1_ctrl_b",
4542         "scifb1_data_c",
4543         "scifb1_data_d",
4544         "scifb1_data_e",
4545         "scifb1_clk_e",
4546         "scifb1_data_f",
4547         "scifb1_data_g",
4548         "scifb1_clk_g",
4549 };
4550
4551 static const char * const scifb2_groups[] = {
4552         "scifb2_data",
4553         "scifb2_clk",
4554         "scifb2_ctrl",
4555         "scifb2_data_b",
4556         "scifb2_clk_b",
4557         "scifb2_ctrl_b",
4558         "scifb2_data_c",
4559 };
4560
4561 static const char * const sdhi0_groups[] = {
4562         "sdhi0_data1",
4563         "sdhi0_data4",
4564         "sdhi0_ctrl",
4565         "sdhi0_cd",
4566         "sdhi0_wp",
4567 };
4568
4569 static const char * const sdhi1_groups[] = {
4570         "sdhi1_data1",
4571         "sdhi1_data4",
4572         "sdhi1_ctrl",
4573         "sdhi1_cd",
4574         "sdhi1_wp",
4575 };
4576
4577 static const char * const sdhi2_groups[] = {
4578         "sdhi2_data1",
4579         "sdhi2_data4",
4580         "sdhi2_ctrl",
4581         "sdhi2_cd",
4582         "sdhi2_wp",
4583 };
4584
4585 static const char * const sdhi3_groups[] = {
4586         "sdhi3_data1",
4587         "sdhi3_data4",
4588         "sdhi3_ctrl",
4589         "sdhi3_cd",
4590         "sdhi3_wp",
4591 };
4592
4593 static const char * const ssi_groups[] = {
4594         "ssi0_data",
4595         "ssi0129_ctrl",
4596         "ssi1_data",
4597         "ssi1_ctrl",
4598         "ssi2_data",
4599         "ssi2_ctrl",
4600         "ssi3_data",
4601         "ssi34_ctrl",
4602         "ssi4_data",
4603         "ssi4_ctrl",
4604         "ssi5",
4605         "ssi5_b",
4606         "ssi5_c",
4607         "ssi6",
4608         "ssi6_b",
4609         "ssi7_data",
4610         "ssi7_b_data",
4611         "ssi7_c_data",
4612         "ssi78_ctrl",
4613         "ssi78_b_ctrl",
4614         "ssi78_c_ctrl",
4615         "ssi8_data",
4616         "ssi8_b_data",
4617         "ssi8_c_data",
4618         "ssi9_data",
4619         "ssi9_ctrl",
4620 };
4621
4622 static const char * const tpu0_groups[] = {
4623         "tpu0_to0",
4624         "tpu0_to1",
4625         "tpu0_to2",
4626         "tpu0_to3",
4627 };
4628
4629 static const char * const usb0_groups[] = {
4630         "usb0",
4631         "usb0_ovc_vbus",
4632 };
4633
4634 static const char * const usb1_groups[] = {
4635         "usb1",
4636 };
4637
4638 static const char * const usb2_groups[] = {
4639         "usb2",
4640 };
4641
4642 static const char * const vin0_groups[] = {
4643         "vin0_data24",
4644         "vin0_data20",
4645         "vin0_data18",
4646         "vin0_data16",
4647         "vin0_data12",
4648         "vin0_data10",
4649         "vin0_data8",
4650         "vin0_data4",
4651         "vin0_sync",
4652         "vin0_field",
4653         "vin0_clkenb",
4654         "vin0_clk",
4655 };
4656
4657 static const char * const vin1_groups[] = {
4658         "vin1_data24",
4659         "vin1_data20",
4660         "vin1_data18",
4661         "vin1_data16",
4662         "vin1_data12",
4663         "vin1_data10",
4664         "vin1_data8",
4665         "vin1_data4",
4666         "vin1_sync",
4667         "vin1_field",
4668         "vin1_clkenb",
4669         "vin1_clk",
4670 };
4671
4672 static const char * const vin2_groups[] = {
4673         "vin2_data24",
4674         "vin2_data18",
4675         "vin2_data16",
4676         "vin2_data8",
4677         "vin2_data4",
4678         "vin2_sync",
4679         "vin2_field",
4680         "vin2_clkenb",
4681         "vin2_clk",
4682 };
4683
4684 static const char * const vin3_groups[] = {
4685         "vin3_data8",
4686         "vin3_sync",
4687         "vin3_field",
4688         "vin3_clkenb",
4689         "vin3_clk",
4690 };
4691
4692 static const struct sh_pfc_function pinmux_functions[] = {
4693         SH_PFC_FUNCTION(audio_clk),
4694         SH_PFC_FUNCTION(avb),
4695         SH_PFC_FUNCTION(du),
4696         SH_PFC_FUNCTION(du0),
4697         SH_PFC_FUNCTION(du1),
4698         SH_PFC_FUNCTION(du2),
4699         SH_PFC_FUNCTION(eth),
4700         SH_PFC_FUNCTION(hscif0),
4701         SH_PFC_FUNCTION(hscif1),
4702         SH_PFC_FUNCTION(i2c0),
4703         SH_PFC_FUNCTION(i2c1),
4704         SH_PFC_FUNCTION(i2c2),
4705         SH_PFC_FUNCTION(i2c3),
4706         SH_PFC_FUNCTION(iic0),
4707         SH_PFC_FUNCTION(iic1),
4708         SH_PFC_FUNCTION(iic2),
4709         SH_PFC_FUNCTION(iic3),
4710         SH_PFC_FUNCTION(intc),
4711         SH_PFC_FUNCTION(mlb),
4712         SH_PFC_FUNCTION(mmc0),
4713         SH_PFC_FUNCTION(mmc1),
4714         SH_PFC_FUNCTION(msiof0),
4715         SH_PFC_FUNCTION(msiof1),
4716         SH_PFC_FUNCTION(msiof2),
4717         SH_PFC_FUNCTION(msiof3),
4718         SH_PFC_FUNCTION(pwm0),
4719         SH_PFC_FUNCTION(pwm1),
4720         SH_PFC_FUNCTION(pwm2),
4721         SH_PFC_FUNCTION(pwm3),
4722         SH_PFC_FUNCTION(pwm4),
4723         SH_PFC_FUNCTION(pwm5),
4724         SH_PFC_FUNCTION(pwm6),
4725         SH_PFC_FUNCTION(qspi),
4726         SH_PFC_FUNCTION(scif0),
4727         SH_PFC_FUNCTION(scif1),
4728         SH_PFC_FUNCTION(scif2),
4729         SH_PFC_FUNCTION(scifa0),
4730         SH_PFC_FUNCTION(scifa1),
4731         SH_PFC_FUNCTION(scifa2),
4732         SH_PFC_FUNCTION(scifb0),
4733         SH_PFC_FUNCTION(scifb1),
4734         SH_PFC_FUNCTION(scifb2),
4735         SH_PFC_FUNCTION(sdhi0),
4736         SH_PFC_FUNCTION(sdhi1),
4737         SH_PFC_FUNCTION(sdhi2),
4738         SH_PFC_FUNCTION(sdhi3),
4739         SH_PFC_FUNCTION(ssi),
4740         SH_PFC_FUNCTION(tpu0),
4741         SH_PFC_FUNCTION(usb0),
4742         SH_PFC_FUNCTION(usb1),
4743         SH_PFC_FUNCTION(usb2),
4744         SH_PFC_FUNCTION(vin0),
4745         SH_PFC_FUNCTION(vin1),
4746         SH_PFC_FUNCTION(vin2),
4747         SH_PFC_FUNCTION(vin3),
4748 };
4749
4750 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4751         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4752                 GP_0_31_FN, FN_IP3_17_15,
4753                 GP_0_30_FN, FN_IP3_14_12,
4754                 GP_0_29_FN, FN_IP3_11_8,
4755                 GP_0_28_FN, FN_IP3_7_4,
4756                 GP_0_27_FN, FN_IP3_3_0,
4757                 GP_0_26_FN, FN_IP2_28_26,
4758                 GP_0_25_FN, FN_IP2_25_22,
4759                 GP_0_24_FN, FN_IP2_21_18,
4760                 GP_0_23_FN, FN_IP2_17_15,
4761                 GP_0_22_FN, FN_IP2_14_12,
4762                 GP_0_21_FN, FN_IP2_11_9,
4763                 GP_0_20_FN, FN_IP2_8_6,
4764                 GP_0_19_FN, FN_IP2_5_3,
4765                 GP_0_18_FN, FN_IP2_2_0,
4766                 GP_0_17_FN, FN_IP1_29_28,
4767                 GP_0_16_FN, FN_IP1_27_26,
4768                 GP_0_15_FN, FN_IP1_25_22,
4769                 GP_0_14_FN, FN_IP1_21_18,
4770                 GP_0_13_FN, FN_IP1_17_15,
4771                 GP_0_12_FN, FN_IP1_14_12,
4772                 GP_0_11_FN, FN_IP1_11_8,
4773                 GP_0_10_FN, FN_IP1_7_4,
4774                 GP_0_9_FN, FN_IP1_3_0,
4775                 GP_0_8_FN, FN_IP0_30_27,
4776                 GP_0_7_FN, FN_IP0_26_23,
4777                 GP_0_6_FN, FN_IP0_22_20,
4778                 GP_0_5_FN, FN_IP0_19_16,
4779                 GP_0_4_FN, FN_IP0_15_12,
4780                 GP_0_3_FN, FN_IP0_11_9,
4781                 GP_0_2_FN, FN_IP0_8_6,
4782                 GP_0_1_FN, FN_IP0_5_3,
4783                 GP_0_0_FN, FN_IP0_2_0 }
4784         },
4785         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4786                 0, 0,
4787                 0, 0,
4788                 GP_1_29_FN, FN_IP6_13_11,
4789                 GP_1_28_FN, FN_IP6_10_9,
4790                 GP_1_27_FN, FN_IP6_8_6,
4791                 GP_1_26_FN, FN_IP6_5_3,
4792                 GP_1_25_FN, FN_IP6_2_0,
4793                 GP_1_24_FN, FN_IP5_29_27,
4794                 GP_1_23_FN, FN_IP5_26_24,
4795                 GP_1_22_FN, FN_IP5_23_21,
4796                 GP_1_21_FN, FN_IP5_20_18,
4797                 GP_1_20_FN, FN_IP5_17_15,
4798                 GP_1_19_FN, FN_IP5_14_13,
4799                 GP_1_18_FN, FN_IP5_12_10,
4800                 GP_1_17_FN, FN_IP5_9_6,
4801                 GP_1_16_FN, FN_IP5_5_3,
4802                 GP_1_15_FN, FN_IP5_2_0,
4803                 GP_1_14_FN, FN_IP4_29_27,
4804                 GP_1_13_FN, FN_IP4_26_24,
4805                 GP_1_12_FN, FN_IP4_23_21,
4806                 GP_1_11_FN, FN_IP4_20_18,
4807                 GP_1_10_FN, FN_IP4_17_15,
4808                 GP_1_9_FN, FN_IP4_14_12,
4809                 GP_1_8_FN, FN_IP4_11_9,
4810                 GP_1_7_FN, FN_IP4_8_6,
4811                 GP_1_6_FN, FN_IP4_5_3,
4812                 GP_1_5_FN, FN_IP4_2_0,
4813                 GP_1_4_FN, FN_IP3_31_29,
4814                 GP_1_3_FN, FN_IP3_28_26,
4815                 GP_1_2_FN, FN_IP3_25_23,
4816                 GP_1_1_FN, FN_IP3_22_20,
4817                 GP_1_0_FN, FN_IP3_19_18, }
4818         },
4819         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4820                 0, 0,
4821                 0, 0,
4822                 GP_2_29_FN, FN_IP7_15_13,
4823                 GP_2_28_FN, FN_IP7_12_10,
4824                 GP_2_27_FN, FN_IP7_9_8,
4825                 GP_2_26_FN, FN_IP7_7_6,
4826                 GP_2_25_FN, FN_IP7_5_3,
4827                 GP_2_24_FN, FN_IP7_2_0,
4828                 GP_2_23_FN, FN_IP6_31_29,
4829                 GP_2_22_FN, FN_IP6_28_26,
4830                 GP_2_21_FN, FN_IP6_25_23,
4831                 GP_2_20_FN, FN_IP6_22_20,
4832                 GP_2_19_FN, FN_IP6_19_17,
4833                 GP_2_18_FN, FN_IP6_16_14,
4834                 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
4835                 GP_2_16_FN, FN_IP8_27,
4836                 GP_2_15_FN, FN_IP8_26,
4837                 GP_2_14_FN, FN_IP8_25_24,
4838                 GP_2_13_FN, FN_IP8_23_22,
4839                 GP_2_12_FN, FN_IP8_21_20,
4840                 GP_2_11_FN, FN_IP8_19_18,
4841                 GP_2_10_FN, FN_IP8_17_16,
4842                 GP_2_9_FN, FN_IP8_15_14,
4843                 GP_2_8_FN, FN_IP8_13_12,
4844                 GP_2_7_FN, FN_IP8_11_10,
4845                 GP_2_6_FN, FN_IP8_9_8,
4846                 GP_2_5_FN, FN_IP8_7_6,
4847                 GP_2_4_FN, FN_IP8_5_4,
4848                 GP_2_3_FN, FN_IP8_3_2,
4849                 GP_2_2_FN, FN_IP8_1_0,
4850                 GP_2_1_FN, FN_IP7_30_29,
4851                 GP_2_0_FN, FN_IP7_28_27 }
4852         },
4853         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4854                 GP_3_31_FN, FN_IP11_21_18,
4855                 GP_3_30_FN, FN_IP11_17_15,
4856                 GP_3_29_FN, FN_IP11_14_13,
4857                 GP_3_28_FN, FN_IP11_12_11,
4858                 GP_3_27_FN, FN_IP11_10_9,
4859                 GP_3_26_FN, FN_IP11_8_7,
4860                 GP_3_25_FN, FN_IP11_6_5,
4861                 GP_3_24_FN, FN_IP11_4,
4862                 GP_3_23_FN, FN_IP11_3_0,
4863                 GP_3_22_FN, FN_IP10_29_26,
4864                 GP_3_21_FN, FN_IP10_25_23,
4865                 GP_3_20_FN, FN_IP10_22_19,
4866                 GP_3_19_FN, FN_IP10_18_15,
4867                 GP_3_18_FN, FN_IP10_14_11,
4868                 GP_3_17_FN, FN_IP10_10_7,
4869                 GP_3_16_FN, FN_IP10_6_4,
4870                 GP_3_15_FN, FN_IP10_3_0,
4871                 GP_3_14_FN, FN_IP9_31_28,
4872                 GP_3_13_FN, FN_IP9_27_26,
4873                 GP_3_12_FN, FN_IP9_25_24,
4874                 GP_3_11_FN, FN_IP9_23_22,
4875                 GP_3_10_FN, FN_IP9_21_20,
4876                 GP_3_9_FN, FN_IP9_19_18,
4877                 GP_3_8_FN, FN_IP9_17_16,
4878                 GP_3_7_FN, FN_IP9_15_12,
4879                 GP_3_6_FN, FN_IP9_11_8,
4880                 GP_3_5_FN, FN_IP9_7_6,
4881                 GP_3_4_FN, FN_IP9_5_4,
4882                 GP_3_3_FN, FN_IP9_3_2,
4883                 GP_3_2_FN, FN_IP9_1_0,
4884                 GP_3_1_FN, FN_IP8_30_29,
4885                 GP_3_0_FN, FN_IP8_28 }
4886         },
4887         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4888                 GP_4_31_FN, FN_IP14_18_16,
4889                 GP_4_30_FN, FN_IP14_15_12,
4890                 GP_4_29_FN, FN_IP14_11_9,
4891                 GP_4_28_FN, FN_IP14_8_6,
4892                 GP_4_27_FN, FN_IP14_5_3,
4893                 GP_4_26_FN, FN_IP14_2_0,
4894                 GP_4_25_FN, FN_IP13_30_29,
4895                 GP_4_24_FN, FN_IP13_28_26,
4896                 GP_4_23_FN, FN_IP13_25_23,
4897                 GP_4_22_FN, FN_IP13_22_19,
4898                 GP_4_21_FN, FN_IP13_18_16,
4899                 GP_4_20_FN, FN_IP13_15_13,
4900                 GP_4_19_FN, FN_IP13_12_10,
4901                 GP_4_18_FN, FN_IP13_9_7,
4902                 GP_4_17_FN, FN_IP13_6_3,
4903                 GP_4_16_FN, FN_IP13_2_0,
4904                 GP_4_15_FN, FN_IP12_30_28,
4905                 GP_4_14_FN, FN_IP12_27_25,
4906                 GP_4_13_FN, FN_IP12_24_23,
4907                 GP_4_12_FN, FN_IP12_22_20,
4908                 GP_4_11_FN, FN_IP12_19_17,
4909                 GP_4_10_FN, FN_IP12_16_14,
4910                 GP_4_9_FN, FN_IP12_13_11,
4911                 GP_4_8_FN, FN_IP12_10_8,
4912                 GP_4_7_FN, FN_IP12_7_6,
4913                 GP_4_6_FN, FN_IP12_5_4,
4914                 GP_4_5_FN, FN_IP12_3_2,
4915                 GP_4_4_FN, FN_IP12_1_0,
4916                 GP_4_3_FN, FN_IP11_31_30,
4917                 GP_4_2_FN, FN_IP11_29_27,
4918                 GP_4_1_FN, FN_IP11_26_24,
4919                 GP_4_0_FN, FN_IP11_23_22 }
4920         },
4921         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4922                 GP_5_31_FN, FN_IP7_24_22,
4923                 GP_5_30_FN, FN_IP7_21_19,
4924                 GP_5_29_FN, FN_IP7_18_16,
4925                 GP_5_28_FN, FN_DU_DOTCLKIN2,
4926                 GP_5_27_FN, FN_IP7_26_25,
4927                 GP_5_26_FN, FN_DU_DOTCLKIN0,
4928                 GP_5_25_FN, FN_AVS2,
4929                 GP_5_24_FN, FN_AVS1,
4930                 GP_5_23_FN, FN_USB2_OVC,
4931                 GP_5_22_FN, FN_USB2_PWEN,
4932                 GP_5_21_FN, FN_IP16_7,
4933                 GP_5_20_FN, FN_IP16_6,
4934                 GP_5_19_FN, FN_USB0_OVC_VBUS,
4935                 GP_5_18_FN, FN_USB0_PWEN,
4936                 GP_5_17_FN, FN_IP16_5_3,
4937                 GP_5_16_FN, FN_IP16_2_0,
4938                 GP_5_15_FN, FN_IP15_29_28,
4939                 GP_5_14_FN, FN_IP15_27_26,
4940                 GP_5_13_FN, FN_IP15_25_23,
4941                 GP_5_12_FN, FN_IP15_22_20,
4942                 GP_5_11_FN, FN_IP15_19_18,
4943                 GP_5_10_FN, FN_IP15_17_16,
4944                 GP_5_9_FN, FN_IP15_15_14,
4945                 GP_5_8_FN, FN_IP15_13_12,
4946                 GP_5_7_FN, FN_IP15_11_9,
4947                 GP_5_6_FN, FN_IP15_8_6,
4948                 GP_5_5_FN, FN_IP15_5_3,
4949                 GP_5_4_FN, FN_IP15_2_0,
4950                 GP_5_3_FN, FN_IP14_30_28,
4951                 GP_5_2_FN, FN_IP14_27_25,
4952                 GP_5_1_FN, FN_IP14_24_22,
4953                 GP_5_0_FN, FN_IP14_21_19 }
4954         },
4955         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4956                              1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
4957                 /* IP0_31 [1] */
4958                 0, 0,
4959                 /* IP0_30_27 [4] */
4960                 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
4961                 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
4962                 0, 0, 0, 0, 0, 0, 0, 0, 0,
4963                 /* IP0_26_23 [4] */
4964                 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
4965                 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
4966                 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
4967                 /* IP0_22_20 [3] */
4968                 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
4969                 FN_I2C2_SCL_C, 0, 0,
4970                 /* IP0_19_16 [4] */
4971                 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
4972                 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
4973                 0, 0, 0, 0, 0, 0, 0, 0, 0,
4974                 /* IP0_15_12 [4] */
4975                 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
4976                 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
4977                 0, 0, 0, 0, 0, 0, 0, 0, 0,
4978                 /* IP0_11_9 [3] */
4979                 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
4980                 0, 0, 0,
4981                 /* IP0_8_6 [3] */
4982                 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
4983                 0, 0, 0,
4984                 /* IP0_5_3 [3] */
4985                 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
4986                 0, 0, 0,
4987                 /* IP0_2_0 [3] */
4988                 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
4989                 0, 0, 0, }
4990         },
4991         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4992                              2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
4993                 /* IP1_31_30 [2] */
4994                 0, 0, 0, 0,
4995                 /* IP1_29_28 [2] */
4996                 FN_A1, FN_PWM4, 0, 0,
4997                 /* IP1_27_26 [2] */
4998                 FN_A0, FN_PWM3, 0, 0,
4999                 /* IP1_25_22 [4] */
5000                 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
5001                 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
5002                 0, 0, 0, 0, 0, 0, 0, 0, 0,
5003                 /* IP1_21_18 [4] */
5004                 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
5005                 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
5006                 0, 0, 0, 0, 0, 0, 0, 0, 0,
5007                 /* IP1_17_15 [3] */
5008                 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
5009                 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
5010                 0, 0, 0,
5011                 /* IP1_14_12 [3] */
5012                 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
5013                 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
5014                 0, 0,
5015                 /* IP1_11_8 [4] */
5016                 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
5017                 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
5018                 0, 0, 0, 0, 0, 0, 0, 0, 0,
5019                 /* IP1_7_4 [4] */
5020                 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
5021                 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
5022                 0, 0, 0, 0, 0, 0, 0, 0, 0,
5023                 /* IP1_3_0 [4] */
5024                 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5025                 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5026                 0, 0, 0, 0, 0, 0, 0, 0, 0, }
5027         },
5028         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5029                              3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
5030                 /* IP2_31_29 [3] */
5031                 0, 0, 0, 0, 0, 0, 0, 0,
5032                 /* IP2_28_26 [3] */
5033                 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
5034                 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5035                 /* IP2_25_22 [4] */
5036                 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
5037                 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
5038                 0, 0, 0, 0, 0, 0, 0, 0,
5039                 /* IP2_21_18 [4] */
5040                 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
5041                 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
5042                 0, 0, 0, 0, 0, 0, 0, 0,
5043                 /* IP2_17_15 [3] */
5044                 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
5045                 0, 0, 0, 0,
5046                 /* IP2_14_12 [3] */
5047                 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5048                 /* IP2_11_9 [3] */
5049                 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5050                 /* IP2_8_6 [3] */
5051                 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
5052                 /* IP2_5_3 [3] */
5053                 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5054                 /* IP2_2_0 [3] */
5055                 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
5056         },
5057         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5058                              3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
5059                 /* IP3_31_29 [3] */
5060                 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5061                 0, 0, 0,
5062                 /* IP3_28_26 [3] */
5063                 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
5064                 0, 0, 0, 0,
5065                 /* IP3_25_23 [3] */
5066                 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5067                 /* IP3_22_20 [3] */
5068                 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5069                 /* IP3_19_18 [2] */
5070                 FN_A16, FN_ATAWR1_N, 0, 0,
5071                 /* IP3_17_15 [3] */
5072                 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
5073                 0, 0, 0, 0,
5074                 /* IP3_14_12 [3] */
5075                 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
5076                 0, 0, 0, 0,
5077                 /* IP3_11_8 [4] */
5078                 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
5079                 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
5080                 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5081                 /* IP3_7_4 [4] */
5082                 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
5083                 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
5084                 0, 0, 0, 0, 0, 0, 0, 0, 0,
5085                 /* IP3_3_0 [4] */
5086                 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5087                 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5088                 0, 0, 0, 0, 0, 0, 0, 0, }
5089         },
5090         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5091                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5092                 /* IP4_31_30 [2] */
5093                 0, 0, 0, 0,
5094                 /* IP4_29_27 [3] */
5095                 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
5096                 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5097                 /* IP4_26_24 [3] */
5098                 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
5099                 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5100                 /* IP4_23_21 [3] */
5101                 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
5102                 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5103                 /* IP4_20_18 [3] */
5104                 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
5105                 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5106                 /* IP4_17_15 [3] */
5107                 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
5108                 0, 0, 0,
5109                 /* IP4_14_12 [3] */
5110                 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
5111                 FN_VI2_FIELD_B, 0, 0,
5112                 /* IP4_11_9 [3] */
5113                 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
5114                 FN_VI2_CLKENB_B, 0, 0,
5115                 /* IP4_8_6 [3] */
5116                 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5117                 /* IP4_5_3 [3] */
5118                 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5119                 /* IP4_2_0 [3] */
5120                 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5121                 }
5122         },
5123         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5124                              2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
5125                 /* IP5_31_30 [2] */
5126                 0, 0, 0, 0,
5127                 /* IP5_29_27 [3] */
5128                 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
5129                 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5130                 /* IP5_26_24 [3] */
5131                 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
5132                 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
5133                 FN_MSIOF0_SCK_B, 0,
5134                 /* IP5_23_21 [3] */
5135                 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
5136                 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
5137                 /* IP5_20_18 [3] */
5138                 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
5139                 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5140                 /* IP5_17_15 [3] */
5141                 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5142                 FN_INTC_IRQ4_N, 0, 0,
5143                 /* IP5_14_13 [2] */
5144                 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5145                 /* IP5_12_10 [3] */
5146                 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
5147                 0, 0,
5148                 /* IP5_9_6 [4] */
5149                 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
5150                 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
5151                 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
5152                 /* IP5_5_3 [3] */
5153                 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
5154                 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
5155                 FN_INTC_EN0_N, FN_I2C1_SCL,
5156                 /* IP5_2_0 [3] */
5157                 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5158                 FN_VI2_R3, 0, 0, }
5159         },
5160         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5161                              3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
5162                 /* IP6_31_29 [3] */
5163                 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5164                 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5165                 /* IP6_28_26 [3] */
5166                 FN_ETH_LINK, 0, FN_HTX0_E,
5167                 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5168                 /* IP6_25_23 [3] */
5169                 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
5170                 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
5171                 /* IP6_22_20 [3] */
5172                 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
5173                 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5174                 /* IP6_19_17 [3] */
5175                 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
5176                 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
5177                 /* IP6_16_14 [3] */
5178                 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
5179                 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
5180                 FN_I2C2_SCL_E, 0,
5181                 /* IP6_13_11 [3] */
5182                 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
5183                 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
5184                 /* IP6_10_9 [2] */
5185                 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
5186                 /* IP6_8_6 [3] */
5187                 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
5188                 FN_SSI_SDATA8_C, 0, 0, 0,
5189                 /* IP6_5_3 [3] */
5190                 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
5191                 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5192                 /* IP6_2_0 [3] */
5193                 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
5194                 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
5195         },
5196         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5197                              1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
5198                 /* IP7_31 [1] */
5199                 0, 0,
5200                 /* IP7_30_29 [2] */
5201                 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
5202                 /* IP7_28_27 [2] */
5203                 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
5204                 /* IP7_26_25 [2] */
5205                 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5206                 /* IP7_24_22 [3] */
5207                 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5208                 0, 0, 0,
5209                 /* IP7_21_19 [3] */
5210                 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5211                 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5212                 /* IP7_18_16 [3] */
5213                 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5214                 FN_GLO_SS_C, 0, 0, 0,
5215                 /* IP7_15_13 [3] */
5216                 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5217                 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5218                 /* IP7_12_10 [3] */
5219                 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5220                 FN_GLO_SCLK_C, 0, 0, 0,
5221                 /* IP7_9_8 [2] */
5222                 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5223                 /* IP7_7_6 [2] */
5224                 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5225                 /* IP7_5_3 [3] */
5226                 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5227                 /* IP7_2_0 [3] */
5228                 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5229                 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
5230         },
5231         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5232                              1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
5233                              2, 2, 2, 2, 2, 2, 2) {
5234                 /* IP8_31 [1] */
5235                 0, 0,
5236                 /* IP8_30_29 [2] */
5237                 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5238                 /* IP8_28 [1] */
5239                 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5240                 /* IP8_27 [1] */
5241                 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5242                 /* IP8_26 [1] */
5243                 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5244                 /* IP8_25_24 [2] */
5245                 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
5246                 FN_AVB_MAGIC, 0,
5247                 /* IP8_23_22 [2] */
5248                 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5249                 /* IP8_21_20 [2] */
5250                 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5251                 /* IP8_19_18 [2] */
5252                 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5253                 /* IP8_17_16 [2] */
5254                 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5255                 /* IP8_15_14 [2] */
5256                 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5257                 /* IP8_13_12 [2] */
5258                 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5259                 /* IP8_11_10 [2] */
5260                 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5261                 /* IP8_9_8 [2] */
5262                 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5263                 /* IP8_7_6 [2] */
5264                 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5265                 /* IP8_5_4 [2] */
5266                 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5267                 /* IP8_3_2 [2] */
5268                 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5269                 /* IP8_1_0 [2] */
5270                 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
5271         },
5272         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5273                              4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
5274                 /* IP9_31_28 [4] */
5275                 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5276                 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
5277                 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5278                 /* IP9_27_26 [2] */
5279                 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5280                 /* IP9_25_24 [2] */
5281                 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5282                 /* IP9_23_22 [2] */
5283                 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5284                 /* IP9_21_20 [2] */
5285                 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5286                 /* IP9_19_18 [2] */
5287                 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5288                 /* IP9_17_16 [2] */
5289                 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5290                 /* IP9_15_12 [4] */
5291                 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
5292                 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5293                 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5294                 /* IP9_11_8 [4] */
5295                 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
5296                 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5297                 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5298                 /* IP9_7_6 [2] */
5299                 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5300                 /* IP9_5_4 [2] */
5301                 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5302                 /* IP9_3_2 [2] */
5303                 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5304                 /* IP9_1_0 [2] */
5305                 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
5306         },
5307         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5308                              2, 4, 3, 4, 4, 4, 4, 3, 4) {
5309                 /* IP10_31_30 [2] */
5310                 0, 0, 0, 0,
5311                 /* IP10_29_26 [4] */
5312                 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5313                 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5314                 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5315                 /* IP10_25_23 [3] */
5316                 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5317                 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5318                 /* IP10_22_19 [4] */
5319                 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5320                 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5321                 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5322                 /* IP10_18_15 [4] */
5323                 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5324                 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5325                 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5326                 0, 0, 0, 0, 0, 0,
5327                 /* IP10_14_11 [4] */
5328                 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5329                 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5330                 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5331                 0, 0, 0, 0, 0, 0, 0,
5332                 /* IP10_10_7 [4] */
5333                 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5334                 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5335                 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5336                 0, 0, 0, 0, 0, 0, 0,
5337                 /* IP10_6_4 [3] */
5338                 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5339                 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5340                 FN_VI3_DATA0_B, 0,
5341                 /* IP10_3_0 [4] */
5342                 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5343                 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5344                 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
5345         },
5346         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5347                              2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
5348                 /* IP11_31_30 [2] */
5349                 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5350                 /* IP11_29_27 [3] */
5351                 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5352                 0, 0, 0,
5353                 /* IP11_26_24 [3] */
5354                 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
5355                 0, 0, 0,
5356                 /* IP11_23_22 [2] */
5357                 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5358                 /* IP11_21_18 [4] */
5359                 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
5360                 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5361                 /* IP11_17_15 [3] */
5362                 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5363                 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5364                 /* IP11_14_13 [2] */
5365                 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5366                 /* IP11_12_11 [2] */
5367                 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5368                 /* IP11_10_9 [2] */
5369                 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5370                 /* IP11_8_7 [2] */
5371                 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5372                 /* IP11_6_5 [2] */
5373                 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5374                 /* IP11_4 [1] */
5375                 FN_SD3_CLK, FN_MMC1_CLK,
5376                 /* IP11_3_0 [4] */
5377                 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5378                 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5379                 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
5380         },
5381         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5382                              1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5383                 /* IP12_31 [1] */
5384                 0, 0,
5385                 /* IP12_30_28 [3] */
5386                 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5387                 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5388                 FN_CAN_DEBUGOUT4, 0, 0,
5389                 /* IP12_27_25 [3] */
5390                 FN_SSI_SCK5, FN_SCIFB1_SCK,
5391                 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5392                 FN_CAN_DEBUGOUT3, 0, 0,
5393                 /* IP12_24_23 [2] */
5394                 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5395                 FN_CAN_DEBUGOUT2,
5396                 /* IP12_22_20 [3] */
5397                 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5398                 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5399                 /* IP12_19_17 [3] */
5400                 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5401                 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5402                 /* IP12_16_14 [3] */
5403                 FN_SSI_SDATA3, FN_STP_ISCLK_0,
5404                 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5405                 /* IP12_13_11 [3] */
5406                 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5407                 FN_CAN_STEP0, 0, 0, 0,
5408                 /* IP12_10_8 [3] */
5409                 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5410                 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5411                 /* IP12_7_6 [2] */
5412                 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5413                 /* IP12_5_4 [2] */
5414                 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5415                 /* IP12_3_2 [2] */
5416                 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5417                 /* IP12_1_0 [2] */
5418                 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
5419         },
5420         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5421                              1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
5422                 /* IP13_31 [1] */
5423                 0, 0,
5424                 /* IP13_30_29 [2] */
5425                 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5426                 /* IP13_28_26 [3] */
5427                 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5428                 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5429                 /* IP13_25_23 [3] */
5430                 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5431                 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5432                 /* IP13_22_19 [4] */
5433                 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5434                 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
5435                 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5436                 /* IP13_18_16 [3] */
5437                 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5438                 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5439                 /* IP13_15_13 [3] */
5440                 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5441                 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5442                 /* IP13_12_10 [3] */
5443                 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5444                 FN_CAN_DEBUGOUT8, 0, 0,
5445                 /* IP13_9_7 [3] */
5446                 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5447                 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5448                 /* IP13_6_3 [4] */
5449                 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5450                 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
5451                 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5452                 /* IP13_2_0 [3] */
5453                 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5454                 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
5455         },
5456         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5457                              1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
5458                 /* IP14_30 [1] */
5459                 0, 0,
5460                 /* IP14_30_28 [3] */
5461                 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
5462                 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5463                 FN_HRTS0_N_C, 0,
5464                 /* IP14_27_25 [3] */
5465                 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5466                 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5467                 /* IP14_24_22 [3] */
5468                 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5469                 FN_LCDOUT9, 0, 0, 0,
5470                 /* IP14_21_19 [3] */
5471                 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5472                 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5473                 /* IP14_18_16 [3] */
5474                 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
5475                 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5476                 /* IP14_15_12 [4] */
5477                 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
5478                 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
5479                 0, 0, 0, 0, 0, 0, 0,
5480                 /* IP14_11_9 [3] */
5481                 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5482                 0, 0, 0,
5483                 /* IP14_8_6 [3] */
5484                 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5485                 0, 0, 0,
5486                 /* IP14_5_3 [3] */
5487                 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
5488                 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
5489                 /* IP14_2_0 [3] */
5490                 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5491                 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5492                 FN_REMOCON, 0, }
5493         },
5494         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5495                              2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
5496                 /* IP15_31_30 [2] */
5497                 0, 0, 0, 0,
5498                 /* IP15_29_28 [2] */
5499                 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5500                 /* IP15_27_26 [2] */
5501                 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5502                 /* IP15_25_23 [3] */
5503                 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5504                 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5505                 /* IP15_22_20 [3] */
5506                 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5507                 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5508                 /* IP15_19_18 [2] */
5509                 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5510                 /* IP15_17_16 [2] */
5511                 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5512                 /* IP15_15_14 [2] */
5513                 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5514                 /* IP15_13_12 [2] */
5515                 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5516                 /* IP15_11_9 [3] */
5517                 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5518                 0, 0, 0,
5519                 /* IP15_8_6 [3] */
5520                 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
5521                 FN_IIC2_SDA, FN_I2C2_SDA, 0,
5522                 /* IP15_5_3 [3] */
5523                 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
5524                 FN_IIC2_SCL, FN_I2C2_SCL, 0,
5525                 /* IP15_2_0 [3] */
5526                 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5527                 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
5528         },
5529         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5530                              4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
5531                 /* IP16_31_28 [4] */
5532                 0, 0, 0, 0, 0, 0, 0, 0,
5533                 0, 0, 0, 0, 0, 0, 0, 0,
5534                 /* IP16_27_24 [4] */
5535                 0, 0, 0, 0, 0, 0, 0, 0,
5536                 0, 0, 0, 0, 0, 0, 0, 0,
5537                 /* IP16_23_20 [4] */
5538                 0, 0, 0, 0, 0, 0, 0, 0,
5539                 0, 0, 0, 0, 0, 0, 0, 0,
5540                 /* IP16_19_16 [4] */
5541                 0, 0, 0, 0, 0, 0, 0, 0,
5542                 0, 0, 0, 0, 0, 0, 0, 0,
5543                 /* IP16_15_12 [4] */
5544                 0, 0, 0, 0, 0, 0, 0, 0,
5545                 0, 0, 0, 0, 0, 0, 0, 0,
5546                 /* IP16_11_8 [4] */
5547                 0, 0, 0, 0, 0, 0, 0, 0,
5548                 0, 0, 0, 0, 0, 0, 0, 0,
5549                 /* IP16_7 [1] */
5550                 FN_USB1_OVC, FN_TCLK1_B,
5551                 /* IP16_6 [1] */
5552                 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5553                 /* IP16_5_3 [3] */
5554                 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5555                 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5556                 /* IP16_2_0 [3] */
5557                 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5558                 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
5559         },
5560         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5561                              3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
5562                              2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
5563                 /* SEL_SCIF1 [3] */
5564                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5565                 FN_SEL_SCIF1_4, 0, 0, 0,
5566                 /* SEL_SCIFB [2] */
5567                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5568                 /* SEL_SCIFB2 [2] */
5569                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5570                 /* SEL_SCIFB1 [3] */
5571                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5572                 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5573                 FN_SEL_SCIFB1_6, 0,
5574                 /* SEL_SCIFA1 [2] */
5575                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5576                 FN_SEL_SCIFA1_3,
5577                 /* SEL_SCIF0 [1] */
5578                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5579                 /* SEL_SCIFA [1] */
5580                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5581                 /* SEL_SOF1 [1] */
5582                 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5583                 /* SEL_SSI7 [2] */
5584                 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5585                 /* SEL_SSI6 [1] */
5586                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5587                 /* SEL_SSI5 [2] */
5588                 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5589                 /* SEL_VI3 [1] */
5590                 FN_SEL_VI3_0, FN_SEL_VI3_1,
5591                 /* SEL_VI2 [1] */
5592                 FN_SEL_VI2_0, FN_SEL_VI2_1,
5593                 /* SEL_VI1 [1] */
5594                 FN_SEL_VI1_0, FN_SEL_VI1_1,
5595                 /* SEL_VI0 [1] */
5596                 FN_SEL_VI0_0, FN_SEL_VI0_1,
5597                 /* SEL_TSIF1 [2] */
5598                 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5599                 /* RESERVED [1] */
5600                 0, 0,
5601                 /* SEL_LBS [1] */
5602                 FN_SEL_LBS_0, FN_SEL_LBS_1,
5603                 /* SEL_TSIF0 [2] */
5604                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5605                 /* SEL_SOF3 [1] */
5606                 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5607                 /* SEL_SOF0 [1] */
5608                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
5609         },
5610         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5611                              3, 1, 1, 1, 2, 1, 2, 1, 2,
5612                              1, 1, 1, 3, 3, 2, 3, 2, 2) {
5613                 /* RESERVED [3] */
5614                 0, 0, 0, 0, 0, 0, 0, 0,
5615                 /* SEL_TMU1 [1] */
5616                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5617                 /* SEL_HSCIF1 [1] */
5618                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5619                 /* SEL_SCIFCLK [1] */
5620                 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5621                 /* SEL_CAN0 [2] */
5622                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5623                 /* SEL_CANCLK [1] */
5624                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5625                 /* SEL_SCIFA2 [2] */
5626                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5627                 /* SEL_CAN1 [1] */
5628                 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
5629                 /* RESERVED [2] */
5630                 0, 0, 0, 0,
5631                 /* SEL_SCIF2 [1] */
5632                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
5633                 /* SEL_ADI [1] */
5634                 FN_SEL_ADI_0, FN_SEL_ADI_1,
5635                 /* SEL_SSP [1] */
5636                 FN_SEL_SSP_0, FN_SEL_SSP_1,
5637                 /* SEL_FM [3] */
5638                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5639                 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5640                 /* SEL_HSCIF0 [3] */
5641                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5642                 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5643                 /* SEL_GPS [2] */
5644                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5645                 /* RESERVED [3] */
5646                 0, 0, 0, 0, 0, 0, 0, 0,
5647                 /* SEL_SIM [2] */
5648                 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5649                 /* SEL_SSI8 [2] */
5650                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
5651         },
5652         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5653                              1, 1, 2, 4, 4, 2, 2,
5654                              4, 2, 3, 2, 3, 2) {
5655                 /* SEL_IICDVFS [1] */
5656                 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5657                 /* SEL_IIC0 [1] */
5658                 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
5659                 /* RESERVED [2] */
5660                 0, 0, 0, 0,
5661                 /* RESERVED [4] */
5662                 0, 0, 0, 0, 0, 0, 0, 0,
5663                 0, 0, 0, 0, 0, 0, 0, 0,
5664                 /* RESERVED [4] */
5665                 0, 0, 0, 0, 0, 0, 0, 0,
5666                 0, 0, 0, 0, 0, 0, 0, 0,
5667                 /* RESERVED [2] */
5668                 0, 0, 0, 0,
5669                 /* SEL_IEB [2] */
5670                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5671                 /* RESERVED [4] */
5672                 0, 0, 0, 0, 0, 0, 0, 0,
5673                 0, 0, 0, 0, 0, 0, 0, 0,
5674                 /* RESERVED [2] */
5675                 0, 0, 0, 0,
5676                 /* SEL_IIC2 [3] */
5677                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5678                 FN_SEL_IIC2_4, 0, 0, 0,
5679                 /* SEL_IIC1 [2] */
5680                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5681                 /* SEL_I2C2 [3] */
5682                 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5683                 FN_SEL_I2C2_4, 0, 0, 0,
5684                 /* SEL_I2C1 [2] */
5685                 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
5686         },
5687         { },
5688 };
5689
5690 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
5691         .name = "r8a77900_pfc",
5692         .unlock_reg = 0xe6060000, /* PMMR */
5693
5694         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5695
5696         .pins = pinmux_pins,
5697         .nr_pins = ARRAY_SIZE(pinmux_pins),
5698         .groups = pinmux_groups,
5699         .nr_groups = ARRAY_SIZE(pinmux_groups),
5700         .functions = pinmux_functions,
5701         .nr_functions = ARRAY_SIZE(pinmux_functions),
5702
5703         .cfg_regs = pinmux_config_regs,
5704
5705         .gpio_data = pinmux_data,
5706         .gpio_data_size = ARRAY_SIZE(pinmux_data),
5707 };